PI74SSTV16857AEX - Pericom - Datasheet.Technology

1PS8460H 11/10/08

Product Description

Pericom Semiconductor’s PI74SSTV16857 series of logic circuits

are produced using the Company’s advanced 0.35 micron CMOS

technology, achieving industry leading speed.

The 14-bit PI74SSTV16857 universal bus driver is designed

for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for

the RESET input which is LVCMOS.

Data flow from D to Q is controlled by the differential clock , CLK,

CLK and RESET. Data is triggered on the positive edge of CLK.

CLK must be used to maintain noise margins.

RESET must be supported with LVCMOS levels as VREF may not

be stable during power-up. RESET is asynchronous and is intended

for power-up only and when low assures that all of the registers reset

to the Low State, Q outputs are low, and all input receivers, data and

clock, are switched off.

Pericom’s PI74SSTV16857 is characterized for operation from

0° to 70°C.

Product Features

• PI74 SSTV16857 is designed for low-voltage operation,

VDD

= VDDQ = 2.3V to 2.7V

• Supports SSTL_2 Class I and II specifications

• SSTL_2 Input and Output Levels

• Designed for DDR Memory

• Flow-Through Architecture

• Packaging:

– 48-pin, 240-mil wide plastic TSSOP (A)

– 48-pin, 240-mil wide Lead-Free plastic TSSOP (AE)

Logic Block Diagram

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PI74SSTV16857

14-Bit Registered Buffer

TO 13 OTHER CHANNELS

RESET

CLK 38

39

VREF

D1 48

35 D

RCLK Q1

1

CLK

V

34

1

2

3

4

5

6

7

8

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

32

31

30

29

28

27

26

25

Q1

Q2

GND

VDDQ

Q3

Q4

Q5

GND

VDDQ

Q6

Q7

VDDQ

GND

Q8

Q9

VDDQ

GND

Q10

Q11

Q12

VDDQ

GND

Q13

Q14

D1

D2

GND

VDD

D3

D4

D5

D6

D7

CLK

VDD

GND

VREF

RESET

D8

D9

D10

D11

D12

VDD

GND

D13

D14

Product Pin Configuration

Pin Name Description

RESET Reset (Active Low)

CLK Clock Input

D Data Input

Q Data Output

GND Ground

VDD Core Supply Voltage

VDDQ Output Supply Voltage

VREF Input Reference Voltage

Product Pin Description

08-0291

2PS8460H 11/10/08

PI74SSTV16857

14-Bit Registered Buffer

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stupnIstuptuO

TESERKLCKLCDQ

LXXXL

H↑↓

HH

Η↑↓

LL

HHroLHroLXoQ

)2(

Truth Table(1)

Notes:

1. H = High Signal Level

L = Low Signal Level

↑= Transition LOW-to-HIGH

↓= Transition HIGH-to-LOW

X = Irrelevant

2. Output level before the

indicated steady state

input conditions were

established.

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Notes:

1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.

2. This current will flow only when the output is in the high state level VO > VDDQ.

3. The package thermal impedance is calculated in accordance with JESD 51.

metIsnoitidnoC/lobmySsgnitaRstinU

erutarepmetegarotST

gts 051ot56–C°

egatlovylppuSV

DD Vro QDD 6.3ot5.0–

VegatlovtupnI )1( VIVot5.0– DD 5.0+

egatlovtuptuO )2,1( VOVot5.0– QDD 5.0+

tnerrucpmalctupnII

KI V, I0<05–

Am

tnerrucpmalctuptuOI

KO V, O0<05±

tnerructuptuosuounitnoCI

OV, OVot0= QDD 05±

VDD V, QDD nip/tnerrucDNGroI

DD I, QDD Iro DNG 001±

ecnadepmIlamrehTegakcaP )3( θJA07W/C°

08-0291

PI74SSTV16857

14-Bit Registered Buffer

3PS8460H 11/10/08

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sretemaraPnoitpircseD.niM.moN.xaMstinU

V

DD

egatloVylppuS3.25.27.2

V

QDD

egatloVylppuSO/I3.25.27.2

V

FER

VegatloVecnerefeR

FER

VX5.0=

QDD

51.152.153.1

V

TT

egatloVnoitanimreTV

FER

40.0–V

FER

V

FER

40.0+

V

HI

egatloVhgiHtupnICDstupnIataDV

FER

1.0+5 V

QDD

3.0+

V

LI

egatloVwoLtupnICD3.0–V

FER

51.0–

V

HI

egatloVhgiHtupnI

TESER

7.1V

QDD

3.0+

V

LI

egatloVwoLtupnI3.0–8.0

V

NI

leveLegatloVtupnI

KLC,KLC

3.0–

V

DI

egatloVlaitnereffiDtupnI63.0V

QDD

6.0+

V

XI

riaPkcolClaitnereffiDfoegatloVtnioPssorCV(

QDD

2.0–)2/V(

QDD

2.0+)2/

I

HO

tnerruCtuptuOleveL-hgiH 02–Am

I

LO

tnerruCtuptuOleveL-woL 02

T

A

erutarepmeTriA-eerFgnitarepO007Cº

Recommended Operating Conditions

08-0291

4PS8460H 11/10/08

PI74SSTV16857

14-Bit Registered Buffer

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sretemaraPsnoitidnoCtseTV

CC

.niM.pyT

)1(

.xaMstinU

V

KI

I

81–=mA V3.22.1–

V

O

H

I

OH

=– μ001A V7.2-V3.2V

DD

–V2.0

I

OH

61–=mA V3.259.1

V

O

L

I

OL

=μ001A V7.2-V3.22.0

I

OH

61=mA V3.253.0

I

,stupnIllAV

I

V=

DD

DNGroV7.25

Aμ

I

DD

)citatS(ybdnatSDNG=TESER

I

O

=0 V7.2

01

citatSgnitarepO V

I

V=

HI

)CA(roV

I

,)CA(

V=TESER

DD

65Am

I

DDD

cimanyD

kcolC-gnitarepO

ylno

V=TESER

DD

V

I

V=

HI)CA(

Vro

)CA(LI

,

gnihctiwsKCdnaKC

elcycytud%05

25

/Aμ

kcolc

zHM

cimanyD

rep-gnitarepO

tupniatadhcae

V=TESER

DD

V

I

V=

HI)CA(

Vro

)CA(LI

,

gnihctiwsKCdnaKC

atadenO.elcycytud%05

kcolcflahtagnihctiwstupni

elcycytud%05,ycneuqerf

9

/Aμ

kcolc

zHM

ataD

r

HO

hgiHtuptuOI

HO

Am02–=V7.2-V3.27 02

mhor

LO

woLtuptuOI

LO

Am02=V7.2-V3.27 02

r

O

()

r

HO-

r

LO

I

O

T,Am02=

A

C°52=

V5.2

6

C

I

stupniataDV

I

V=

FER

Vm053±0.25.3

Fp

KCdnaKCV

RCI

V,V52.1=

)PP(I

Vm063=V5.20.25.3

Notes:

4. Typical values are at VDD = Nominal VDD, TA = +25°C.

DC Electrical Characteristics

(Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ±200mV, VDDQ = 2.5V ±200mV)

Δ

08-0291

PI74SSTV16857

14-Bit Registered Buffer

5PS8460H 11/10/08

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VDD 2= .V5V2.0± tinU

.niM.xaM

kcolcfycneuqerFkcolC 002zHM

tWnoitaruDesluP5.2

sn

ttca emitevitcastupnilaitnereffiD )5( 22

ttcani emitevitcanistupnilaitnereffidetarwelstuptuO )6( 22

tUS

etarwelstsaf,emitputeS )9,7(

KC,KCerofebataD

57.0

etarwelswols,emitputeS )9,8( 9.0

th

etarwelstsaf,emitdloH )9,7(

KC,KCerofebataD

57.0

etarwelswols,emitdloH )9,8( 9.0

retemaraP morF )tupnI( oT )tuptuO(

V

DD

V2.0±V5.2= stinU

.niM.pyT.xaM

f

xam

002zHM

t

dp

KLC,KLCQ1.18.2

sn

t

lhp

TESERQ 0.5

Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)

Switching characteristics (over recommended operating free-air temperature range, unless otherwise noted.)

(See test circuits and switching waveforms).

Notes:

5. Data inputs must be held low for a minimum time of tact min , after RESET is taken high

6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low.

7. Data signal input slew rate ≥ 1 V/ns

8. Data signal input slew rate ≥ 0.5V/ns and <1V/ns

9. CLK, CLK input slew rates are ≥ 1 V/ns.

↑

08-0291

6PS8460H 11/10/08

PI74SSTV16857

14-Bit Registered Buffer

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Voltage and Current Waveforms

Input Active and Inactive Times

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Setup and Hold Times

Test Circuit and Switching Waveforms

Notes:

8. CL includes probe and jig capacitance.

9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.

10. All input pulses are supplied by generators having the following characteristics:

PRR ≤10 MHz, ZO = 50Ω. Input slew rate = 1V/ns ±20% (unless otherwise specified).

11. The outputs are measured one at a time with one transition per measurement.

12. VTT = VREF = VDDQ/2

13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input.

14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input.

15. tPLH and tPHL are the same as tpd.

Parameter Measurement Information (VDD = 2.5V ±0.2V)

Load Circuit

Input

VIL

VREF VREF

tw

VIH

Input

Timing

Input

t

h

t

su

VIL

VICR

VREF

VI(PP)

VIH

Voltage Waveforms - Propagation Delay Times

Timing

Input

Output

V

ICR

t

PLH

t

PHL

V

ICR

V

I(PP)

V

OH

V

TT

V

TT

V

OL

LVCMOS

RESET

Input

Output

t

PHL

V

DD

/2

V

OH

V

IH

V

IL

V

TT

V

OL

Voltage Waveforms - Propagation Delay Times

VTT

RL = 50Ω

From Output

Under Test

CL = 30pF(8)

Test Point

LVCMOS

RESET

Input

I

DD(9)

V

DD

V

DD

/2

t

inact

0V

I

DDH

10% 90%

I

DDL

t

act

08-0291

PI74SSTV16857

14-Bit Registered Buffer

7PS8460H 11/10/08

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.236

.244

.488

.496

.002

.006

SEATING PLANE

.007

.010

.0197

BSC

.004

.008

.319

1

48

12.4

12.6

6.0

6.2

0.50 0.17

0.27

8.1

0.05

0.15

0.09

0.20

X.XX

DENOTES DIMENSIONS

IN MILLIMETERS

.018

.030

0.45

0.75

.047

1.20 Max

BSC

48-Pin TSSOP Package (A)

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

Ordering Information

edoCgniredrOepyTegakcaPegnaRgnitarepO

A75861VTSS47IPPOSSTlim-042,niP-84C°07otC°0

EA75861VTSS47IP)eerF-bP(POSSTlim-042,niP-84C°07otC°0

08-0291