1999-2013 Microchip Technology Inc. DS41120C-page 1
PIC16C717/770/771
18/20-Pin, 8-Bit CMOS Microcont rollers with 10/12-Bit A/D
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Interrupt capability (up to 10 internal/external
inter rupt so urc es)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Pow er- on Reset (POR )
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscilla tor f or relia ble opera tion
• Selectable oscillator options:
- INTRC - Internal RC, dual speed (4 MHz and
37 kHz nominal) dynamic ally s witc hable for
power savings
- ER - External resistor, dual speed (user
selectable frequency and 37 kHz nominal)
dynamically switchable for power savings
- EC - External clock
- HS - High speed crystal/resonator
- XT - Crystal/re son ator
- LP - Low power crystal
• Low power, high speed CMOS EPROM
technology
• In-Circuit Serial Programming™(ICSP™
• Wide operating voltage range: 2.5V to 5.5V
• 15 I/O pins with individual control for:
- Direction (15 pins)
- Digital/Analog input (6 pins)
- PORTB interrupt on change (8 pins)
- PORTB weak pull-up (8 pins)
- High voltage open drain (1 pin)
• Commercial and Industrial temperature ranges
• Low power consumption:
- < 2 mA @ 4V, 4 MHz
-11 A typical @ 2.5V, 37 kHz
-< 1 A typical standby current
Pin Diagr am
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be increm ent ed duri ng SLEEP via extern al
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Enhanced Capture, Compare, PWM (ECCP)
module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
- Enhanced PWM:
- Single, Half-Bridge and Full-Bridge Output
modes
- D ig it a lly pr ogra mmable deadband del ay
• Analog-to-Digital converter:
- PIC16C770/771 12-bit resolution
- PIC16C717 10- bit r esolution
• On-chip absolute bandgap voltage reference
generator
• Programmable Brown-out Reset (PBOR)
circuitry
• Programmable Low-Voltage Detection (PLVD)
circuitry
• Master Synchronous Serial Port (MSSP) with two
modes of opera tion:
- 3-wire SPI™ (supports all 4 SPI modes)
-I
2C™ compatible including Master mode
support
• Program Memory Read (PMR) capability for look-
up table, character string storage and checksum
calculation purposes
Device Memory Pins A/D
Resolution A/D
Channels
Program
x14 Data
x8
PIC16C717 2K 256 18, 20 10 bits 6
PIC16C770 2K 256 20 12 bits 6
PIC16C771 4K 256 20 12 bits 6
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
AVDD
AVSS
10 11
PIC16C770/771
20-Pin PDIP, SOIC, SSOP
PIC16C717/770/771
DS41120C-page 2 1999-2013 Microchip Technology Inc.
Pin Diagram s
18-Pin PDIP, SOIC
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PIC16C717
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD(2)
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS(1)
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
PIC16C717
VDD(2)
VSS(1)
10 11
20-Pin SSOP
Note 1: VSS pins 5 and 6 must be tied together.
2: VDD pins 15 and 16 must be tied together.
Key Features
PICmicroTM Mid-Range MCU Family
Reference Manual, (DS33023) PIC16C717 PIC16C770 PIC16C771
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR, MCLR,
WDT (PWRT, OST) POR, BOR, MCLR,
WDT (PWRT, OST) POR, BOR, MCLR,
WDT (PWRT, OST)
Program Memory (14-bit words) 2K 2K 4K
Data Memory (bytes) 256 256 256
Interrupts 10 10 10
I/O Ports Ports A,B Ports A,B Ports A , B
Timers 333
Enhanced Capture/Compare/PWM (ECCP)
modules 111
Serial Communications MSSP MSSP MSSP
12-bit Analog-to-Digital Module –6 input channels 6 input channels
10-bit Analog-to-Digital Module 6 input channels ––
Instruction Set 35 Instructions 35 Instructions 35 Instructions
1999-2013 Microchip Technology Inc. DS41120C-page 3
PIC16C717/770/771
Table of Contents
1.0 Device Overview......................................................................................................................................................5
2.0 Memory Organization...............................................................................................................................................9
3.0 I/O Ports.................................................................................................................................................................25
4.0 Program Memory Read (PMR) ..............................................................................................................................41
5.0 Timer0 Module.......................................................................................................................................................45
6.0 Timer1 Module.......................................................................................................................................................47
7.0 Timer2 Module.......................................................................................................................................................51
8.0 Enhanced Capture/Compare/PWM (ECCP) Modules............................................................................................53
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................65
10.0 Voltage Reference Module and Low-voltage Detect..........................................................................................101
11.0 Analog-to-Digital Converter (A/D) Module..........................................................................................................105
12.0 Special Features of the CPU .............................................................................................................................117
13.0 Instruction Set Summary....................................................................................................................................133
14.0 Development Support ........................................................................................................................................141
15.0 Electrical Characteristics....................................................................................................................................147
16.0 DC and AC Characteristics Graphs and Tables................................................................................................. 179
17.0 Packaging Information .......................................................................................................................................197
APPENDIX A: Revision History ............................................. ...... ..... ...... ...................... ...... ..... ................................207
APPENDIX B: Device Differences ... ..... ...... ..... ...... ...... ...................... ...... ..... ....................... ..... ................................208
Index ..........................................................................................................................................................................209
On-Line Support..........................................................................................................................................................215
Reader Response.......................................................................................................................................................216
PIC16C717/770/771 Product Identification System....................................................................................................217
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PIC16C717/770/771
DS41120C-page 4 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 5
PIC16C717/770/771
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicroTM
Mid-Range MCU Family Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip website. The Reference Manual should
be considered a complementary document to this data
sheet, and is highly recommended reading for a better
understanding o f the device arc hi tec ture a nd operatio n
of the peripheral modules.
There are thr ee devices (PIC16C7 17, P IC16C770 and
PIC16C771) covered by this data sheet. The
PIC16C717 device comes in 18/20-pin packages and
the PIC1 6C770/771 dev ices come in 2 0-p in packages.
The following two figures are device block diagrams of
the PIC16C717 and the PIC16C770/771.
FIGURE 1-1: PIC16C717 BLOCK DIAGRAM
EPROM
Program
Memory
2K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
PORTA
PORTB
RA4/T0CKI
RB0/AN4/INT
RB4/SDI/SDA
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register .
Enhanced CCP Master
Timer0 Timer1 Timer2
Synchronous
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1/LVDIN
RA0/AN0
8
3
Timing
Generation
10-bit
ADC
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Internal
4 MHz, 37 kHz
and ER mode
(ECCP) Serial Port (MSSP)
B andgap
Reference Low-voltage
Detect
RAM
Program Memory
Read (PMR)
PIC16C717/770/771
DS41120C-page 6 1999-2013 Microchip Technology Inc.
FIGURE 1-2: PIC16C770/771 BLOC K DIAGRAM
EPROM
Program
Memory(2)
13 Data B us 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
PORTA
PORTB
RA4/T0CKI
RB0/AN4/INT
RB4/SDI/SDA
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: Program memory for PIC16C770 is 2K x 14. Program memory for PIC16C771 is 4K x 14.
Enhanc ed C CP Master
Timer0 Timer1 Timer2
Synchronous
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1/LVDIN
RA0/AN0
8
3
Timing
Generation
12-bit
ADC
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Internal
4 MHz, 37 kHz
and ER mode
(ECCP) Serial Po rt (MSSP)
Bandgap
Reference Low-voltage
Detect
RAM
Program Memory
Read (PMR)
AVDD
AVSS
1999-2013 Microchip Technology Inc. DS41120C-page 7
PIC16C717/770/771
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input
RA1/AN1/LVDIN
RA1 ST CMOS Bi-directional I/O
AN1 AN A/D input
LVDIN AN LVD input reference
RA2/AN2/VREF-/VRL
RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3/AN3/VREF+/VRH
RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4/T0CKI RA4 ST OD Bi-d irectional I/O
T0CKI ST TMR0 clock input
RA5/MCLR/VPP
RA5 ST Input port
MCLR ST Master clear
VPP Power Programming voltage
RA6/OSC2/CLKOUT
RA6 ST CMOS Bi-directional I/O
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7/OSC1/CLKIN
RA7 ST CMOS Bi-directional I/O
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/ER resistor connection
RB0/AN4/INT
RB0 TTL CMOS Bi-directional I/O(1)
AN4 AN A/D input
INT ST Interrupt input
RB1/AN5/SS
RB1 TTL CMOS Bi-directional I/O(1)
AN5 AN A/D input
SS ST SSP slave select input
RB2/SCK/SCL
RB2 TTL CMOS Bi-directional I/O(1)
SCK ST CMOS S erial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3/CCP1/P1A
RB3 TTL CMOS Bi-directional I/O(1)
CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4/SDI/SDA
RB4 TTL CMOS Bi-directional I/O(1)
SDI ST Serial data in for SP I
SDA ST OD Serial data I/O for I2C
RB5/SDO/P1B
RB5 TTL CMOS Bi-directional I/O(1)
SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
PIC16C717/770/771
DS41120C-page 8 1999-2013 Microchip Technology Inc.
RB6/T1OSO/T1CKI/P1C
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7/T1OSI/P1D
RB7 TTL CMOS Bi-directional I/O(1)
T1OSI XTAL TMR1 crystal/resonator
P1D CMOS PWM P1D output
VSS VSS Power Ground reference for logic and I/O pins
VDD VDD Power Positive supply for logic and I/O pins
AVSS(2) AVSS Power Ground reference for analog
AVDD(2) AVDD Pow er Positive supply for analog
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
1999-2013 Microchip Technology Inc. DS41120C-page 9
PIC16C717/770/771
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these PIC®
microcontrollers. Each block (Program Memory and
Data Memory) has its own bus, so that concurrent
access can occur.
Addit ional informat ion on devi ce memory may be found
in the PICmicro Mid-Range MCU Family Reference
Manual, (DS33023).
2.1 Program Memory Organization
The PIC16C717/770/771 devices have a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. The PIC16C717 and the
PIC16C770 have 2K x 14 words of program memory.
The PIC16C771 has 4K x 14 words of program mem-
ory. Accessing a location above the physically imple-
mented address will cause a wrap-around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C717 AND PIC16C770
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C771
2.2 Data Memory Organization
The data memory is partitioned into multiple banks,
whic h contain th e General Pu rpose Re gisters a nd the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 Bank0
= 01 Bank1
= 10 Bank2
= 11 Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some frequently used special func-
tion registers from one bank are mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The registe r file can be accesse d either dire ctly , or ind i-
rectly, through the File Select Register FSR.
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory Page 0 07FFh
3FFFh
RP1 RP0 (STATUS<6:5>)
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
3FFFh
PIC16C717/770/771
DS41120C-page 10 1999-2013 Microchip Technology Inc.
FIGURE 2-3: REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Indirect addr.(*)
ADRESL
PIR2 PIE2
ADRESH
ADCON0 ADCON1
General
Purpose
Register
General
Purpose
Register
EFh
F0h
accesses
70h-7Fh
96 Bytes
80 Bytes
LVDCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
17Fh
Bank 2
16Fh
170h
File
Address
PCL
STATUS
FSR
PCLATH
INTCON
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1FFh
Bank 3
Indirect addr.(*)
OPTION_REG
1EFh
1F0h
accesses
70h - 7Fh
TRISB
PCL
STATUS
FSR
PCLATH
INTCON
Indirect addr.(*)
TMR0
General
Purpose
Register
accesses
70h - 7Fh
PORTB
80 Bytes
File
Address
File
Address
File
Address
REFCON
SSPCON2
WPUB
IOCB
ANSEL
P1DEL
PMDATL
PMADRL
PMDATH
PMADRH
PMCON1
1999-2013 Microchip Technology Inc. DS41120C-page 11
PIC16C717/770/771
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The spec ial function regi sters can be clas sified into two
sets ; core (CPU) and pe riphera l. Thos e regis ters a sso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
01h TMR0 Timer0 module’s register xxxx xxxx 45
02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
03h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
04h(3) FSR Indirect data memory address pointer xxxx xxxx 23
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 25
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx11 33
07h —Unimplemented — —
08h —Unimplemented — —
09h —Unimplemented — —
0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
0Ch PIR1 —ADIF—— SSPIF CCP1IF TMR2IF TMR1IF -0---0000 18
0Dh PIR2 LVDIF — — —BCLIF— — — 0--- 0--- 20
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx 47
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx 47
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47
11h TMR2 Timer2 module’s reg ister 0000 0000 51
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 70
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67
15h CC PR1L Capture/Co mpare/PWM Register1 (LSB) xxxx xxxx 54
16h CC PR1H Capture/C ompare/PWM Register1 (MSB) xxxx xxxx 54
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53
18h —Unimplemented — —
19h —Unimplemented — —
1Ah —Unimplemented — —
1Bh —Unimplemented — —
1Ch —Unimplemented — —
1Dh —Unimplemented — —
1Eh ADRESH A/D High Byte Result Register xxxx xxxx 107
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 107
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
PIC16C717/770/771
DS41120C-page 12 1999-2013 Microchip Technology Inc.
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15
82h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
83h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
84h(3) FSR Indirect data memory address pointer xxxx xxxx 23
85h TRISA PORTA Data Direction Register 1111 1111 25
86h TRISB POR TB Data Direction Register 1111 1111 33
87h —Unimplemented — —
88h —Unimplemented — —
89h —Unimplemented — —
8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
8Ch PIE1 —ADIE—— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 17
8Dh PIE2 LVDIE — — —BCLIE— — — 0--- 0--- 19
8Eh PCON — — — —OSCF—PORBOR ---- 1-qq 21
8Fh —Unimplemented — —
90h —Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 69
92h PR2 Timer2 Period Register 1111 1111 52
93h SSPADD Synch ro no us Serial Port (I2C mode) Address Regist er 0000 0000 76
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 66
95h WPUB PORTB Weak Pull-up Control 1111 1111 34
96h IOCB PORTB Interr upt on C han ge Contro l 1111 0000 34
97h P1DEL PWM 1 Delay value 0000 0000 62
98h —Unimplemented — —
99h —Unimplemented — —
9Ah —Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 102
9Ch LVDCON —— BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 101
9Dh ANSEL — — Analog Channel Select --11 1111 25
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx 107
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 107
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
1999-2013 Microchip Technology Inc. DS41120C-page 13
PIC16C717/770/771
Bank 2
100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
101h TMR0 Timer0 module’s register xxxx xxxx 45
102h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
103h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
104h(3) FSR Indirect data memory address pointer xxxx xxxx 23
105h —Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx11 33
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
10Ch PMDATL Program memory read data low xxxx xxxx
10Dh PMADRL Program memory read address low xxxx xxxx
10Eh PMDATH —— Program memory read data high --xx xxxx
10Fh PMADRH — — — — Program memory read address high ---- xxxx
110h-
11Fh —Unimplemented — —
Bank 3
180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15
182h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
183h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
184h(3) FSR Indirect data memory address pointer xxxx xxxx 23
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 33
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
18Ch PMCON1 Reserved — — — — — —RD1--- ---0
18Dh-
18Fh —Unimplemented — —
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
PIC16C717/770/771
DS41120C-page 14 1999-2013 Microchip Technology Inc.
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the ar ithmetic st atus of th e ALU, the RESET st atus and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set t he Z bit. T his leav es the STA T US regist er
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affe ct the Z, C or D C bits from th e ST ATUS register. For
other instructions not affecting any status bits, see the
"Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Regist er Bank Select bit (used for indire ct add ressing)
1 = Bank 2, 3 ( 100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instru cti on
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF in st ruct ion s) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 15
PIC16C717/770/771
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register, which cont ains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able re gister known a lso as the pres caler), t he Ext ernal
INT Int errupt, T MR0 and the w eak pul l-up s on POR TB.
REGISTER 2-2: OPTION REGISTER (OPTION_REG: 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit(1)
1 = PORTB weak pull-ups are disabled
0 = PORTB weak pull-ups are enabled by the WPUB register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on RA4/T0 CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: Individua l w ea k pul l-u p on R B pin s ca n be enab led/disable d from the w ea k pu ll-u p
PORTB Register (WPUB).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C717/770/771
DS41120C-page 16 1999-2013 Microchip Technology Inc.
2.2.2.3 INTCON REGISTER
The INTCO N Register is a read able and writ able regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all int erru pts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR 0 interr upt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit(1)
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 regist er has overfl owed (must be clear ed in softw are)
0 = TMR0 reg i ster did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cl eared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:0> pins changed state (must be cleared in software)
0 = None of the RB<7:0> pins have changed state
Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the
Interrupt-on-Change PORTB register (IOCB).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 17
PIC16C717/770/771
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE—— SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as ’0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D inte rru pt
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP inte rru pt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrup t
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 18 1999-2013 Microchip Technology Inc.
2.2.2.5 PIR1 REGISTE R
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF—— SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interru pt condition ha s occurred, and must be c leared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI A transmission/reception has taken place.
I2 C Slave / Master
A transmission/reception has taken place.
I2 C Master
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (Multi-master system).
A STOP condition occurred while the SSP module was IDLE (Multi-master system).
0 = No SSP interrupt condition has occurred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR 1 register capture occurred (must be cleared in softw are)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 reg i ster did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 19
PIC16C717/770/771
2.2.2.6 PIE2 REGISTER
This register contains the individual enable bits for the
SSP bus collision and low voltage detect interrupts.
REGISTER 2-6: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2: 8Dh)
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIE ———BCLIE———
bit 7 bit 0
bit 7 LVDIE: Low Voltage Detect Interrupt Enable bit
1 = LVD Interrupt is enabled
0 = LVD Interrupt is disabled
bit 6-4 Unimplemented: Read as '0'
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Bus Collision interrupt is enabled
0 = Bus Collision interrupt is disabled
bit 2-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 20 1999-2013 Microchip Technology Inc.
2.2.2.7 PIR2 REGISTE R
This register contains the SSP Bus Collision and low-
voltage detect interrupt flag bits.
.
REGISTER 2-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIF ———BCLIF———
bit 7 bit 0
bit 7 LVDIF: Low Voltage Detect Interrupt Flag bit
1 = The supply vo ltage has fallen b elow the spe cified LVD voltage (must be c leared in s oftware)
0 = The supply voltage is greater than the specified LVD voltage
bit 6-4 Unimplemented: Read as '0'
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred while the SSP module configured in I2C Master was
transmitting (must be cleared in software)
0 = No bus collision occurred
bit 2-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 21
PIC16C717/770/771
2.2.2.8 PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con-
tain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
The PCON register also contains the frequency select
bit of the INTRC or ER oscilla tor.
REGISTER 2-8: POWER CONTROL REGISTER (PCON: 8Eh)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
clear, indicati ng a brown-ou t has occurre d.
The BOR status bit is a don't care and is
not necessarily predictable if the bro wn-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-q R/W-q
————OSCF—PORBOR
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 OSCF: Oscillator Speed bit
INTRC Mode
1 = 4 MHz nominal
0 = 37 kHz nominal
ER Mode
1 = Oscillator frequency depends on the external resistor value on the OSC1 pin.
0 = 37 kHz nominal
All other modes
x = Ignored
bit 2 Unimplemented: Read as '0 '
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit (See Section 2.2.2.8 Note)
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend: q = Value depends on conditions
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 22 1999-2013 Microchip Technology Inc.
2.3 PCL and PCLATH
The pr ogra m cou nter (PC) speci fie s th e a ddress of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits an d is n ot d irec tly re ada ble or writ ab le. All upd ate s
to the PCH register occur through the PCLA TH register .
2.3.1 PROGRAM MEMORY PAGING
PIC16C717/770/771 devices are capable of address-
ing a continuous 8K word block of program memory.
The CALL and GOTO instruc tions provi de onl y 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the us er must ensure tha t the page select bit s are
programmed so that the desired program memory
page is addressed. A return instruction pops a PC
address off the stack onto the PC register. Therefore,
manipu lation of the PCLATH<4:3> bit s are not req uired
for the return instructions (which POPs the address
from the stack).
2.4 Stack
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address f rom this b ranch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writ able. The PC is PUSHed ont o the st ack
when a CALL instruction is executed or an interrupt
causes a bran ch . The s t ac k is PO Ped in the ev en t of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH i s n ot mo di fie d wh en t h e s tack i s P US Hed o r
POPed.
Aft er the st ack has been PUSHed e ight times, the nin th
push ov erwrite s the va lue tha t was store d fro m the first
push. The tenth pus h ov erwr i tes the se cond push (an d
so on).
FIGURE 2-4: LOADING OF PC IN
DIFFERENT SITUATIONS
Instruction with
PCL as
Destination
8ALU
12 0
11 Opcode <10:0>
GOTO, CALL
PCLATH<4:3>
PCLATH
PCLATH
87
PCLATH<4:0>
12 1110 870
PCH PCL
PCH PCL
5
2
1999-2013 Microchip Technology Inc. DS41120C-page 23
PIC16C717/770/771
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: How to Clear RAM Using
Indirect Addressing
An effective 9-bit address is obtained by concatenating
the 8-bit FSR reg ister and the IRP bi t (ST A TU S<7>), as
shown in Figure 2-5.
FIGURE 2-5: DIRECT/INDI RECT ADDRE SSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
Note 1: For register file map detail see Figure 2-3.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16C717/770/771
DS41120C-page 24 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 25
PIC16C717/770/771
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O port s ma y be found i n th e
PIC Mid-Range MCU Family Reference Manual,
(DS33023).
3.1 I/O Port Analog/Digital Mode
The PIC16C717/770/771 have two I/O ports: PORTA
and PORTB. Some of th ese port pins are mixed - si gna l
(can be digital or analog). When an analog signal is
prese nt on a pin, the pin must be co nfigured as an ana-
log inpu t to prev ent unn eces sary c urrent d raw from th e
power supply. The Analog Select Register (ANSEL)
allows the user to individually select the Digital/Analog
mode on these pins. When the Analog mode is active,
the port pin will always read 0.
REGISTER 3-1: ANALOG SELECT REGISTER (ANSEL: 9Dh)
3.2 PORTA and the TRISA Register
PORTA is a 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bi t (=1) will m ake t he co rrespon ding POR TA pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISA bit (=0) will
make the correspon ding POR TA pin an out put (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, where as wri tin g to i t wi ll write to th e port latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, thi s valu e is mod ified, and the n writ ten to th e port
data l atch.
Pins RA<3:0> are multiplexed with analog functions,
such as analog inputs to the A/D converter, analog
VREF inputs, and the onboard bandgap reference out-
puts. When the analog peripherals are using any of
these pins as analog input/output, the ANSEL register
must have the proper value to individually select the
Analog mode of the corresponding pins.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schm itt Trigger inp ut and an ope n drai n outpu t.
Pin RA5 i s multi plexed wi th the device RESET (MCLR)
and programming input (VPP) functions. The RA5/
MCLR/VPP input only pin has a Schmitt Trigger input
buffer. All other RA port pins have Schmitt Trigger input
buffers and full CMOS output buffers.
Pins RA6 and RA7 are multiplexed with the oscillator
input and output functions.
The TRISA register controls the direction of the RA
pins, ev en w he n th ey a re being used as ana log inp uts.
The user mu st ensure the bit s in the TRISA registe r are
maintained set when using them as analog inputs.
Note 1: On a Power-on Reset, the ANSEL regis-
ter configures these mixed-signal pins as
Analog mode.
2: If a pin is config ured as Analog mo de, the
RA pin w ill a lways read '0' and RB pi n will
always read '1', even if the digital output is
active.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
bit 7-6 Reserved: Do not use
bit 5-0 ANS<5:0>: Analog Select between analog or digital function on pins AN<5:0>, respectively.
0 = Digital I/O. Pin is assigned to port or special function.
1 = Analog Input. Pin is assigned as analog input.
Note: Setting a pin to an analog input disables the digital input buffer on the pin. The cor-
responding TRIS bit should be set to Input mode when using pins as analog inputs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
Note: Upon RESET, the ANSEL register config-
ures the RA<3:0> pins as analog inputs.
All RA<3:0> pins will read as '0'.
PIC16C717/770/771
DS41120C-page 26 1999-2013 Microchip Technology Inc.
EXAMPLE 3-1: Initializing PORTA
FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0, RA1/AN1/LVDIN
BCF STATUS, RP0 ; Select Bank 0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0Fh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<7:4> as outputs. RA<7:6>availability depends on oscillator selection.
MOVLW 03 ; Set RA<1:0> as analog inputs, RA<7:2> are digital I/O
MOVWF ANSEL
BCF STATUS, RP0 ; Return to Bank 0
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
PORT
WR
TRIS
Data Latch
TRIS Mode
VSS
VDD
Schmitt
Trigger
To A/D Converter input or LVD Module input
RD
TRIS
QD
Q
CK
Analog Select
WR
ANSEL
RD
PORT
VDD
VSS
1999-2013 Microchip Technology Inc. DS41120C-page 27
PIC16C717/770/771
FIGURE 3-2: BLOCK DIAGRAM OF RA2/AN2/VREF-/VRL AND RA3/AN3/VREF+/ VRH
To A/D Converter input
VRH, VRL outputs
(From VREF-LVD-BOR Module)
and VREF+, VREF- inputs
Sense input for
VRH, VRL amplifier
VRH, VRL output enable
Data
Bus
QD
Q
CK
QD
Q
CK P
N
WR
PORT
WR
TRIS
Data Latch
TRIS Mode
VSS
VDD
Schmitt
Trigger
RD
TRIS
QD
Q
CK
Analog Select
WR
ANSEL
RD
PORT
VDD
VSS
QD
EN
PIC16C717/770/771
DS41120C-page 28 1999-2013 Microchip Technology Inc.
FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
N
WR
Port
WR
TRIS
Data Latch
RD
VSS
Schmitt Trigger
Input Buffer
TMR0 clock input
RD
TRIS
TRIS Latch
PORT
VSS
1999-2013 Microchip Technology Inc. DS41120C-page 29
PIC16C717/770/771
FIGURE 3-4: BLOCK DIAGRAM OF RA5/MCLR/VPP
Data
Bus
QD
EN
RD PORT
Schmitt
Trigger
RD
TRIS
VSS
To MCLR Circuit MCLR Filter
VSS
HV Detect
Program Mode
PIC16C717/770/771
DS41120C-page 30 1999-2013 Microchip Technology Inc.
FIGURE 3-5: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
Q
D
Q
CK
Schmitt Trigger
Input Buffer
Oscillator
Circuit
From OSC1
1
0
CLKOUT (Fosc/4)
(INTRC or ER) and CLKOUT
VDD
VSS
DQ
EN
EC or [(ER or INTRC) and CLKOUT]
1999-2013 Microchip Technology Inc. DS41120C-page 31
PIC16C717/770/771
FIGURE 3-6: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Vss
VDD
Q
D
Q
CK
Schmitt Trigger
Input Buffer
Oscillator
Circuit
To OSC2
INTRC
INTRC
Schmitt Trigger
Input Buffer
To Chip Clock Drivers
EC Mode
VDD
DQ
EN
PIC16C717/770/771
DS41120C-page 32 1999-2013 Microchip Technology Inc.
TABLE 3-1: PORTA FUNCTIONS
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Function Input
Type Output
Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input
RA1/AN1/LVDIN
RA1 ST C MOS B i-directional I/O
AN1 AN A/D input
LVDIN AN LVD input reference
RA2/AN2/VREF-/VRL
RA2 ST C MOS B i-directional I/O
AN2 AN A/D input
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3/AN3/VREF+/VRH
RA3 ST C MOS B i-directional I/O
AN3 AN A/D input
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4/T0CKI RA4 ST OD Bi-directional I/O
T0CKI ST TMR0 clock input
RA5/MCLR/VPP
RA5 ST Input port
MCLR ST Master clear
VPP Power Programming voltage
RA6/OSC2/CLKOUT
RA6 ST C MOS B i-directional I/O
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7/OSC1/CLKIN
RA7 ST C MOS B i-directional I/O
OSC1 XTAL Crystal/resonator
CLKIN ST/AN External clock input/ER resistor connection
Address Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
1999-2013 Microchip Technology Inc. DS41120C-page 33
PIC16C717/770/771
3.3 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bi t (=1) will m ake the c orresponding POR TB pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e.,
put the contents of the outpu t latch on the select ed pin).
EXAMPLE 3-2: Initializing PORTB
Each of the PO R TB pins has an inte rnal pul l-up , whic h
can be individually enabled from the WPUB register. A
single global enabl e bit can turn o n/off th e enabled pul l-
ups. Clearing the RBPU bit, (OPTION_REG<7>),
enables t he wea k pul l-up r esi stors. The weak pul l-up i s
automat icall y turned of f when the port pi n is co nfigure d
as an output. The pull-ups are di sabled on a Powe r-on
Reset.
Each of the PORTB pins, if configured as input, also
has an interrupt-on-change feature, which can be indi-
vidually selected from the IOCB register. The RBIE bit
in the INTCON reg ister functio ns as a gl obal enable b it
to turn on/off the interrupt-on-change feature. The
selected inputs are compared to the old value latched
on the l ast read of POR TB. The "m ismatch" out puts are
OR'ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrup t service routin e, can clear the int er-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
a) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
BCF STATUS, RP0;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVLW 0x30 ; Set RB<1:0> as analog
inputs
MOVWF ANSEL ;
BCF STATUS, RP0; Return to Bank 0
PIC16C717/770/771
DS41120C-page 34 1999-2013 Microchip Technology Inc.
REGISTER 3-2: WEAK PULL-UP PORTB REGIS TER (WPU B: 95h)
REGISTER 3-3: INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
bit 7-0 WPUB<7:0>: PORTB Weak Pull-Up Control bits
1 = Weak pull-up enabled
0 = Weak pull-up disabl ed
Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG
register must be cleared.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRIS = 0).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0
bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note: The interrupt enable bits GIE and RBIE in the INTCON Register must be set for indi-
vidual interrupts to be recognized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 35
PIC16C717/770/771
The RB0 pin i s mu ltiple xed w ith th e A /D conv erter an a-
log input 4 and the external interrupt input (RB0/AN4/
INT). Whe n the pin is used as anal og input, the ANSEL
register must have the proper value to select the RB0
pin as Analog mo de.
The RB1 pin i s mu ltiple xed w ith th e A/D co nverte r an a-
log input 5 and the MSSP module slave select input
(RB1/AN5/SS). When the pin is used as analog input,
the ANSEL register must have the proper value to
select the RB1 pin as Analog mode.
FIGURE 3-7: BLOCK DIAGRAM OF RB0/AN4/INT, RB1/AN5/SS PIN
Note: Upon RESET, the ANSEL register config-
ures th e RB1 and RB0 pins as analog inputs.
Both R B1 an d R B0 pi ns w i ll re ad as '1 '.
Data Bus
WR
WR
RD
PORTB Reg
TRIS Reg
To INT input or MSSP module
Q
D
CK
Q
D
CK
EN
QD
EN
RD
RBPU weak
pull-up
TTL
Schmitt
Trigger
P
N
VSS
VDD
Q
D
CK
Q
D
CK
WPUB Reg
IOCB Reg
PORT
TRIS
PORT
TRIS
WR
WPUB
Q
D
Q
EN
D
Q
EN
Q3
Q1
...
Set
RBIF
From
RB<7:0> pins
Q
QD
Q
CK
Analog Select
WR
ANSEL
WR
IOCB
VDD
VSS
Q
P
VDD
Q
To A/D Converter
PIC16C717/770/771
DS41120C-page 36 1999-2013 Microchip Technology Inc.
FIGURE 3-8: BLOCK DIAGRAM OF RB2/SCK/SCL, RB3/CCP1/P1A, RB4/SDI/SDA,
RB5/SDO/P1B
Data Bus
WR
WR
RD
PORTB Reg
TRIS Reg
SCK, SCL, CC, SDI, SDA inputs
Q
D
CK
Q
D
CK
EN
QD
EN
RD
RBPU weak
pull-up
Schmitt
Trigger
P
N
VSS
VDD
Q
D
CK
Q
D
CK
WPUB Reg
IOCB Reg
PORT
TRIS
PORT
TRIS
WR
WPUB
Q
D
Q
EN
D
Q
EN
Q3
Q1
...
Set
RBIF
From
RB<7:0> pins
Q
WR
IOCB
VDD
VSS
Q
P
VDD
Q
1
0
Spec. Func En.
SDA, SDO, SCK, CCP1, P1A, P1B
TTL
1999-2013 Microchip Technology Inc. DS41120C-page 37
PIC16C717/770/771
FIGURE 3-9: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/P1C
Data Latch
TRIS Latch
RD TRISB
P
VSS
Q
D
Q
CK
Q
D
QCK N
VDD
RD PORTB
WR PORTB
WR TRISB
T1OSCEN
TMR1 Clock
RBPU VDD
weak pull-up
P
From R B7
From QD
EN
Set RBIF
RB<7:0> pins RD Port
Q3
Q1
Serial programming clock
TTL
Input
Buffer
TMR1 Oscillator
QD
EN
VDD
Data Bus Q
D
CK
WPUB Reg
WR
WPUB Q
IOCB Reg
WR
IOCB
Q
D
CK Q
Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions.
...
Schmitt
Trigger
CMOS
PIC16C717/770/771
DS41120C-page 38 1999-2013 Microchip Technology Inc.
FIGURE 3-10: BLOCK DIAGRAM OF THE RB7/T1OSI/P1D
Data Latch
TRIS Latch
RD TRISB
P
VSS
Q
D
QCK
Q
D
Q
CK N
VDD
RD PORTB
WR PORTB
WR TRISB
T10SCEN
T1OSCEN
To RB6
RBPU VDD
weak pull-up
P
TTL
Input
Buffer
From QD
EN
QD
EN
Set RBIF
RB<7:0> pins RD Port
Q3
Q1
Serial programming input
Schmitt Trigger
TMR1 Oscillator
VDD
Data Bus Q
D
CK
WPUB Reg
WR
WPUB Q
Q
D
CK
IOCB Reg
WR
IOCB Q
Note: The TMR1 oscillator enable (T1OSCEN = 1) overr ides the RB7 I/O port and P1D functions.
...
1999-2013 Microchip Technology Inc. DS41120C-page 39
PIC16C717/770/771
TABLE 3-3: PORTB FUNCTIONS
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Function Input
Type Output
Type Description
RB0/AN4/INT
RB0 TTL CMOS Bi-directional I/O(1)
AN4 AN A/D input
INT ST Interrupt input
RB1/AN5/SS
RB1 TTL CMOS Bi-directional I/O(1)
AN5 AN A/D input
SS ST S SP slave select input
RB2/SCK/SCL
RB2 TTL CMOS Bi-directional I/O(1)
SCK ST CMOS S erial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3/CCP1/P1A
RB3 TTL CMOS Bi-directional I/O(1)
CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4/SDI/SDA
RB4 TTL CMOS Bi-directional I/O(1)
SDI ST Serial data in for SP I
SDA ST OD Serial data I/O for I2C
RB5/SDO/P1B
RB5 TTL CMOS Bi-directional I/O(1)
SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
RB6/T1OSO/T1CKI/P1C
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7/T1OSI/P1D
RB7 TTL CMOS Bi-directional I/O(1)
T1OSI XTAL T MR1 cry stal/resonator
P1D CMOS PWM P1D output
Note 1: Bit programmable pull-ups.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
V alue on all
other
RESETS
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB 0 xxxx xx11 uuuu uu11
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
95h W PUB PORTB Weak Pull-up Control 1111 1111 1111 1111
96h IOCB PORTB Interrupt on Change Control 1111 0000 1111 0000
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C717/770/771
DS41120C-page 40 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 41
PIC16C717/770/771
4.0 PROGRAM MEMORY READ
(PMR)
Program memory is readable during normal operation
(full VDD range). It is indirectly addressed through the
Special Function Registers:
•PMCON1
•PMDATH
•PMDATL
• PMADRH
• PMADRL
When interfacing the program memory block, the
PMDATH & PMDATL registers form a 2-byte word,
which hold s the 14-bit dat a. The PMADRH & PMADRL
registers form a 2-byte word, which holds the 12-bit
address of the program memory location being
accessed. Mid-range devices have up to 8K words of
program EPROM with an address range from 0h to
3FFFh. When the device contains less memory than
the full address range of the PMADRH:PMARDL regis-
ters, the Most Significant bits of the PMADRH register
are ignored.
4.1 PMCON1 REGISTER
PMCON1 is the control register for program memory
accesses.
Control bit RD initiates a rea d operation. This bit cann ot
be cleared, only set, in software. It is cleared in hard-
ware at completion of the read operation.
REGISTER 4-1: PROGRAM MEMORY READ CONTROL REGISTER 1 (PMCON1: 18Ch)
4.2 PMDATH AND PMDATL
REGISTERS
The PMDATH:PMDATL registers are loaded with the
contents of program memory addressed by the
PMADRH and PMADRL registers upon completion of a
Program Memory Read command.
R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0
Reserved ——————RD
bit 7 bit 0
bit 7 Reserved: Read as ‘1’
bit 6-1 Unimplemented: Read as '0'
bit 0 RD: Read Control bit
1 = Initiates a Program memory read (read takes 2 cycles). RD is cleared in hardware.
0 = Reserved
Legend: S = Settable (cleared in hardware)
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 42 1999-2013 Microchip Technology Inc.
REGISTER 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh)
REGISTER 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch)
REGISTER 4-4: PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh)
REGISTER 4-5: PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh)
U-0 U-0 R-x R-x R-x R-x R-x R-x
—— PMD13 PMD12 PMD11 PMD10 PMD9 PMD8
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL
after a Program Memory Read command.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
R-x R-x R-x R-x R-x R-x R-x R-x
PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0
bit 7 bit 0
bit 7-0 PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after
a Progr am Memory Read command.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
———— PMA11 PMA10 PMA9 PMA8
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3-0 PMA<11:8>: PMR Address bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0
bit 7 bit 0
bit 7-0 PMA<7:0>: PMR Address bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 43
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4.3 READING THE EPROM PROGRAM
MEMORY
To read a program memory location, the user must
write 2 bytes of the address to the PMADRH and
PMADRL registers, then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
Program Memory Read (PMR) controller will use the
second instruction cycle after to read the data. This
causes the second instruction immediately following
the “BSF PMCON1,RD” instruction to be ign ored. Th e dat a
is ava il abl e, in the very nex t c y cle , i n the PM DATH and
PMDATL registers; therefore it can be read as 2 bytes
in the following instructions. PMDATH and PMDATL
registers will hold this value until another Program
Memory Read or until it is written to by the user.
EXAMPLE 4-1: OTP PROGRAM MEMORY Read
4.4 OPERATION DURING CODE
PROTECT
When the device is code protected, the CPU can still
perform the P rogram Memory Read function .
FIGURE 4-1: PROGRAM MEMO RY READ CYCLE EXECUTION
Note: The two instructions that follow setting the
PMCON1 read bit must be NOPs.
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW MS_PROG_PM_ADDR ;
MOVWF PMADRH ; MS Byte of Program Memory Address to read
MOVLW LS_PROG_PM_ADDR ;
MOVWF PMADRL ; LS Byte of Program Memory Address to read
BSF STATUS, RP0 ; Bank 3
BSF PMCON1, RD ; Program Memory Read
NOP ; This instruction must be an NOP
NOP ; This instruction must be an NOP
next instruction ; PMDATH:PMDATL now has the data
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1,RD
Executed here INSTR(PC+1)
Executed here Forced NOP
Executed here
PC PC+1 PMADRH,PMADRL PC+3 PC+5
Program
RD bit
PC+3 PC+4
INSTR(PC-1)
Executed here INSTR(PC+3)
Executed here INSTR(PC+4)
Execut ed her e
PMDATH
PMDATL
register
Memory
ADDR
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TABLE 4-1: PROGRAM MEMORY READ REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
18Ch PMCON1 Reserved ——————RD
1--- ---0 1--- ---0
10Eh PMDATH — — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 --xx xxxx --uu uuuu
10Ch PMDATL PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 xxxx xxxx uuuu uuuu
10Fh PMADRH — — — — PMA11 PMA10 PMA9 PMA8 ---- xxxx ---- uuuu
10Dh PMADRL PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not us ed by Program Memory Read.
1999-2013 Microchip Technology Inc. DS41120C-page 45
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5.0 TIMER0 MODULE
The T imer0 modul e timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual,
(DS33023).
5.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery instruction cycle (w ith ou t pre s-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in below.
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PIC Mid-Range MCU Family Refer-
ence Manual, (DS33023).
5.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 5-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
availa ble which is mutuall y exclusive ly shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
The prescaler is not readable or writable.
The PSA and PS<2:0> bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing b it PSA will assign t he prescaler to the T imer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 regist er (e.g. CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
FIGURE 5-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5- 2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
Fosc/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
PSout
(2 Tcy delay)
PSout
Data Bus
8
PSA
PS2, PS1, PS0 Set interrupt
flag bit T0IF
on overflow
3
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5.2.1 SWITCHING PRESCA LER
ASSIGNMENT
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
5.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in sof tware b y the Timer0 module interrup t ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PIC Mid-Range Reference Manual,
DS33023) must be executed when chang-
ing the prescaler assignment from Timer0
to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
01h,101h TMR0 Timer0 register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Ti mer0.
RA4/T0CKI
T0SE
Pin
M
U
X
CLKOUT (= Fosc/4)
SYNC
2
Cycles TMR 0 re g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS<2:0>
8
Note: T0CS, T0SE, PS A , PS<2:0 > a re (OPTIO N_ R EG< 5:0 > ).
PSA
WDT Enable Bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
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6.0 TIMER1 MODULE
The T imer1 modul e timer/counter has the following fea-
tures:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from ECCP module trigger
Timer1 has a control register, shown in Register 6-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1O N (T1CON <0 >).
Figure 6-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual,
(DS33023).
6.1 Timer1 Operation
Timer1 can ope rate in one of these mo des :
•As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
REGISTER 6-1: TIMER1 CONTROL REGISTER (T1CON: 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillato r is shut off(1)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external cl ock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI /P1C (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: The oscil lator inverter a nd feedback r esistor are turn ed off t o eliminate p ower drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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6.1. 1 TIMER1 COUNTER OPERATION
In this m ode, T imer1 is being incre mented vi a an exter-
nal source. Increments occur on a rising edge. After
Timer1 is enabled in Counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Initially high)
T1CKI
(Initially low)
Note: Arrows indicate counter increments.
First falling edge
of the T1ON enabled
First falling edge
of the T1ON enabled
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS<1:0> SLEE P input
T1OSCEN
Enable
Oscillator(1)
Fosc/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Note 1: W hen the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow TMR1
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6.2 Timer1 Oscillator
A cryst al oscillator circuit is built in be tween pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The o scilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 os cillato r.
The Timer1 oscillator is identical to the LP oscillator.
The user m us t prov id e a so ftware tim e de lay to en su re
proper oscillator start-up.
TABLE 6-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched i n interrupt f lag bit TMR 1IF (PIR1<0>).
This in terrupt ca n be e nabled/di sabled by settin g/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
6.4 Resetting Timer1 using a CCP
Trigger Output
If the ECCP mo dul e is co nfig ure d in C om pare mode to
generate a “special event trigger" (CCP1M<3:0> =
1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the even t that a write to T imer1 coi ncides with a spe-
cial event trigger from ECCP, the write will take prece-
dence.
In this mode of o peration, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
char acteristi cs, the use r should co nsult t he
resonator/crystal manufacturer for appro-
priate values of external components.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
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NOTES:
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7.0 TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 matc h of PR2
• SSP module optional use of TMR2 output to gen-
erate clock sh ift
Timer2 has a control register, shown in Register 7-1.
Timer2 ca n be shut off by cl eari ng control bit T MR2O N
(T2CON<2>) to minimize power consumption.
Figure 7-1 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual,
(DS33023).
7.1 Timer2 Operation
Timer2 can be used as the PWM time-base for PWM
mode of the ECCP module.
The TMR2 register is readable and writable, and is
cleared on any device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 7-1: TIMER2 CONTROL REGISTER (T2CON1: 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as '0 '
bit 6-3 TOUTPS<3:0>: Timer2 Ou tpu t Post s cale Sele ct bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 P ostscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Pres cal e Selec t bit s
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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7.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
7.3 Output of TMR2
The output of TMR2 (before the post scaler) is fed to the
Synchro nou s Seri al Port m odu le w hi ch optio nally uses
it to generate shift clock.
FIGURE 7-1: Timer2 Block Diagram
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2
Sets flag
TMR2 reg
output (1)
RESET
Postscaler
Prescaler
PR2 reg
2
Fosc/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note: TMR2 register output can be software
selected by the SSP Module as a baud
clock.
to
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
11h TMR2 Timer2 register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Time r2 P erio d Re gis te r 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
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8.0 ENHANCED CAPTURE/
COMPARE/PW M (ECCP)
MODULES
The ECCP (Enhanced Capture/Compare/PWM)
module cont ai ns a 16 -bit regi ster w hich c an opera te as
a 16-bit capture register, as a 16-bit compare register
or as a PWM master/slave Duty Cycle register.
Table 8-1 shows the ti mer resources of the ECCP mod-
ule modes.
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON and P1DEL reg-
isters control the operation of ECCP. All are readable
and writable.
REGISTER 8-1: CCP1 CONTROL REGISTER (CCP1CON: 17h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 PWM1M<1:0>: PWM Output Configuration
CCP1M<3:2> = 00, 01, 10
xx = P1A assigned as Capture input, Compare output. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> = 11
00 = Single output. P1A modulated. P1B, P1C, P1D assigned as Port pins.
01 = Full-bridge output forward. P1D modulated. P1A active. P1B, P1C inactive.
10 = Half-bridge output. P1A, P1B modulated with deadband control. P1C, P1D assigned as
Port pins.
11 = Full-bridge output reverse. P1B modulated. P1C active. P1A, P1D inactive.
bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: Th ese bit s are the tw o LSbs of the PWM duty cycl e. The ei ght MSbs are found in
CCPRnL.
bit 3-0 CCP1M<3:0>: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every fallin g edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mo de, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Comp are mode, trigger special event (CCP1IF bit is set; ECCP resets TMR1, and st arts
an A/D conversion, if the A/D module is enabled.)
1100 = PWM mode. P1A, P1C active high. P1B, P1D active high.
1101 = PWM mode. P1A, P1C active high. P1B, P1D active low.
1110 = PWM mode. P1A, P1C active low. P1B, P1D active high.
1111 = PWM mode. P1A, P1C active low. P1B, P1D active low.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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TABLE 8-1: ECCP MODE - TIMER
RESOURCE
8.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit valu e of the TMR1 regi ster when an ev ent occurs on
pin CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cle ared in so ftware. If a nother captu re occurs b efore
the value in register CCPR1 is read, the old captured
value wi ll be los t.
8.1.1 CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<3> bit.
8.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
8.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
8.1.4 ECCP PRESCALER
There are three prescaler settings, specified by bits
CCP1M<3:0>. Whenever the ECCP module is turned
off or the ECCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cl e are d , t h ere f o re t h e f i rs t ca pt u re m ay be f r om
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1: Changing Between
Capture Prescalers
FIGURE 8-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
8.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
• driven High
•driven Low
• toggle output (High to Low or Low to High)
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0>. At the same time, interrupt flag bit
CCP1IF is set.
Changing the ECCP mode select bits to the clear out-
put on Match mode (CCP1M<3.0> = “1000”) presets
the CCP1 output latch to the logic 1 level. Changing the
ECCP mode select bits to the clear output on Match
mode (CCP1M<3:0> = “1001”) presets the CCP1 out-
put latch to the logic 0 level.
8.2.1 CCP1 PIN CONFIGURATION
The user m us t co nfig ure t he CC P1 p in a s an outp ut b y
clearing the appropriate TRISB bit.
8.2.2 TIMER1 MODE SELECTIO N
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
ECCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
Note: If the R B3/C CP1/P1 A pin is conf igur ed as
an output, a write to the port can cause a
capture co ndition.
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port data
latch.
CLRF CCP1CON ; Turn ECCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and ECCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RB3/CCP1/
Prescaler
³ 1, 4, 16
and
edge det ect
P1A Pin
1999-2013 Microchip Technology Inc. DS41120C-page 55
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8.2.3 SOFTWARE INTERRUPT MODE
When gen erat e soft ware i nterrup t is c hosen, the CCP 1
pin is not affected . Only an ECCP interrupt is generate d
(if enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mod e, an internal ha rdware trigg er is generated,
which may be used to initiate an action.
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 re gister to
effe ctively be a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of ECCP module will
also start an A/D conversion if the A/D module is
enabled.
FIGURE 8-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Note: The special event trigger will not set the
interrupt flag bit TMR1IF (PIR1<0>).
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Speci a l Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RB3/CCP1/
TRISB<3> CCP1CON<3:0>
Mode Select
Output Enable
P1A Pin
Special event tri gger will:
RESET Timer1, but not set interrupt flag bit
TMR1IF (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Valu e on
all other
RESETS
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISB PORTB Data Direction Register 1111 1111 1111 1111
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
T1CON —— T1CKPS
1T1CKP
S0 T1OSCEN T1SYNC TMR1CS TMR1O
N--00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer 1.
PIC16C717/770/771
DS41120C-page 56 1999-2013 Microchip Technology Inc.
8.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the ECCP
module produces up to a 10-bit resolu tion PWM outpu t.
Figure 8-3 shows the simplified PWM block diagram.
FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM
8.3.1 PWM PE RIOD
The PWM p eriod i s spec ified by writi ng to th e PR2 re g-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM PERIOD = [(PR2) + 1] • 4 • TOSC •
(TMR2 PRESCALE VALUE)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equa l to PR2, t he followi ng three ev ents
occur on the next increment cycle:
• TMR2 is cl eare d
• The CCP1 pin is set (exception: if PWM duty
cycl e = 0% , the CCP1 pin will not be set)
• The PWM dut y cycl e is latched fro m CCPR1L i nto
CCPR1H
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1 )
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
Note: 8-bit timer TMR2 is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
TRISB<3>
RB3/CCP1/P1A
TRISB<5>
RB5/SDO/P1B
TRISB<6>
RB6/T1OSO/T1CKI/
TRISB<7>
RB7/T1OSI/P1D
P1C
OUTPUT
CONTROLLER
PWM1M1<1:0>
2CCP1M<3:0>
4
P1DEL
CCP1/P1A
P1B
P1C
P1D
Note: The Timer2 posts caler (s ee Se cti on 7.0) i s
not used in the determination of the PWM
frequenc y . T he posts caler could b e used to
have a servo update rate at a different fre-
quency than the PWM output.
1999-2013 Microchip Technology Inc. DS41120C-page 57
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8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CC P1CON <5:4> c an be wri tten to at an y
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycl e. This do uble
buffering is essential for gli tchless P WM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximu m PWM resolu tion (bi ts) f or a given PWM fre-
quency:
8.3.3 PWM OUTPUT CONFIGURATIONS
The PWM1M1 bits in the CCP1CON register allows
one of the following configurations:
• Single output
• Half-Bridge output
• Full-Bridge output, Forward mode
• Full-Bridge output, Revers e mode
In the Single Output mode, the RB3/CCP1/P1A pin is
used as the PWM output. Since the CCP1 output is
multiplexed with the PORTB<3> data latch, the
TRISB<3> bit must be cleared to make the CCP1 pin
an output.
FIGURE 8-4: SINGLE PWM OUTPUT
FIGURE 8-5: EXAMPLE OF SINGLE
OUTPUT APPLICATION
In the Half-Bridge Output mode, two pins are used as
outputs. The RB3/CCP1/P1A pin has the PWM output
signal, while the RB5/SDO/P1B pin has the comple-
mentary PWM output signal. This mode can be used
for half-bri dge appl icati ons, as sho wn on Figure 8-7 , or
for full-bridge applications, where four power switches
are being modulated with two PWM signal.
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> a nd TRISB<5> bit s must be clea red t o co n-
figure P1A and P1B as outputs.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through cur-
rent in bridge power devices. See Section 8.3.5 for
more details of the deadband delay operations.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
FOSC
FPWM
------ ----- ----
log
2log
------ ---- ----------- ---- ---- bits=
Period
Duty Cycle
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
CCP1(2)
2: Output signal is shown as asserted high.
C
PIC16C717/770/771
CCP1 RVout
Using PWM as
a D/A Converter
PIC16C717/770/771
CCP1
Using PWM to
Drive a Power
V+
L
O
A
D
Load
PIC16C717/770/771
DS41120C-page 58 1999-2013 Microchip Technology Inc.
8.3.4 OUTPUT POLARITY
CONFIGURATION
The CCP1M<1:0> bits in the CCP1CON register allow
user to choose the logic conventions (asserted high/
low) for each of the outputs. See Register 8-1 for fur-
ther details.
The PWM outp ut polarities mu st be selected be fore the
PWM outputs are enabled. Charging the polarity con-
figuration while the PWM outputs are active is not rec-
ommended, since it may result in unpredictable
operation.
FIGURE 8-6: HALF-BRIDGE PWM OUTPUT
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Period
Duty Cycle
td
td
(1)
P1A(2)
P1B(2)
td = Deadband Delay
Period
(1) (1)
2: Output signals are shown as asserted high.
1999-2013 Microchip Technology Inc. DS41120C-page 59
PIC16C717/770/771
FIGURE 8-7: EXAMP LE OF HALF-BRI DGE OUTPUT MODE APPLICATIONS
PIC16C717/770/771
P1A
P1B
FET
DRIVER
FET
DRIVER
V+
V-
LOAD
+ -
+
V
-
+
V
-
PIC16C717/770/771
P1A
P1B
FET
DRIVER
FET
DRIVER
V+
V-
LOAD
+ -
FET
DRIVER
FET
DRIVER
PIC16C717/770/771
DS41120C-page 60 1999-2013 Microchip Technology Inc.
In Full-Bridge Output mode, four pins are used as out-
puts; however, only two outputs are active at a time. In
the Forw ard mode, R B3/C CP1/P1A pin is con tinuou sly
active, and RB7/T1OSI/P1D pin is modulated. In the
Reve rse mode , RB6/ T1O SO/ T1CKI /P 1C pi n is c ont in-
uously active, and RB5/SDO/P1B pin is modulated.
P1A, P1B, P1C and P1D outputs are multiplexed with
PORTB< 3> and PORTB<5:7> data latc hes. TRISB<3>
and TRISB<5:7> bits must be cleared to make the P1A,
P1B, P1C, and P1D pins output.
FIGURE 8-8: FULL-BRIDGE PWM OUTPUT
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
FORWARD MODE
(1)
Period
Duty Cycle
P1A(2)
P1C(2)
P1D(2)
P1B(2)
REVERSE MODE
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(1)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
1999-2013 Microchip Technology Inc. DS41120C-page 61
PIC16C717/770/771
FIGURE 8-9: EXAMP LE OF FULL-BRIDGE APPLICATION
PIC16C717/770/771
P1D
P1A
FET
DRIVER
FET
DRIVER
V+
V-
LOAD
+ -
FET
DRIVER
FET
DRIVER
P1C
P1B
PIC16C717/770/771
DS41120C-page 62 1999-2013 Microchip Technology Inc.
8.3.5 PROGRAMMABLE DEADBAND
DELAY
In half-brid ge or ful l-b ridge applicat ion s, dri ven by ha lf-
bridge outputs (see Figure 8-7), the power switches
normally require longer time to turn off than to turn on.
If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches will be on for a short
period of time, until one switch completely turns off.
During this time, a very high current, called shoot-
through cu rrent, will flow throu gh bo th powe r switc hes,
shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on the power switch is normally
delayed to all ow the o ther swi tch to compl etely turn of f.
In the Half-Bridge Output mode, a digitally program-
mable deadband delay is available to avoid shoot-
through current from destroying the bridge power
switches . The delay oc curs at the sig nal transition from
the non-active state to the active state. See Figure 8-6
for illustration. The P1DEL register sets the amount of
delay.
REGISTER 8-2: PWM DELAY REGISTER (P1DEL: 97H)
8.3.6 DIRECTION CHANGE IN FULL-
BRIDGE OUTPUT MODE
In the Full -Bridge Outp ut mode, the PWM 1M1 bit in the
CCP1CON regi ste r allo w s us er to con trol the Forwa r d/
Reverse direction. When the application firmware
changes this direction control bit, the ECCP module will
assum e the new d irec ti on on the next PWM cycle. The
current PWM cycle still continues, however, the non-
modulated outputs, P1A and P1C signals, will transition
to the new direction TOSC, 4TOS C or 16TO SC (for
Timer2 prescale T2CKRS<1:0> = 00, 01 and 1x
resp ec ti v el y) ea r lie r, befor e the en d of the pe r i od . Du r -
ing this transition cycle, the modulated outputs, P1B
and P1D, will go to the inactive state. See Figure 8-10
for illustration.
FIGURE 8-10: PWM DIRECTION CHANGE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1DEL7 P1DEL6 P1DEL5 P1DEL4 P1DEL3 P1DEL2 P1DEL1 P1DEL0
bit 7 bit 0
bit 7-0 P1DEL<7:0>: PWM Delay Count for Half-Bridge Output Mode: Number of FOSC/4 (Tosc4)
cycles between the P1A transition and the P1B transition.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
DC PERIOD
SIGNAL
P1A (Active High)
Note 1: The Direction bit in the ECCP Control Register (CCP1CON<PWM1M1>) is written anytime during the PWM cycle.
2: The P1A and P1C signals switch TOSC, 4*Tosc or 16*TOSC, depending on the Timer2 prescaler value, earlier when
changing direction. The modulated P1B and P1D signals are inactive at this time.
(1)
PERIOD
(2)
P1D (Active High)
P1C (Active High)
P1B (Active High)
1999-2013 Microchip Technology Inc. DS41120C-page 63
PIC16C717/770/771
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any deadband delay. In gen-
eral, since only one output is modulated at a time,
deadban d delay is not requ ired. However , there is a sit-
uation w here a deadb and delay mig ht be required. This
situation occurs when all of the following conditions are
true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off ti me of the power swi tch, in cluding
the power device and driver circuit, is greater
than turn on time.
Figure 8-11 shows an example, where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cy cle. At time t1, the outpu t P1A and P1D bec ome
inactive, while output P1C becomes active. In this
exampl e, si nce th e turn of f ti me of the p ower devices is
longer than the turn on time, a shoot-through current
flows through the power devices, QB and QD, for the
duration of t = toff-ton. The same phenomenon will occur
to power devices, QC and QB, for PWM direction
change from reverse to forward.
If changing PWM direction at high duty cycle is required
for the user ’s application, one of the following require-
ments mu st be met:
1. Avoid c hangi ng PWM output dire ction at or ne ar
100% duty cycle.
2. Use switch drivers that com pensa te for the slow
turn off of the power devices. The total turn off
time (toff) of the power device and the driver
must be less than the turn on time (ton).
FIGURE 8-11: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
FORWARD PERIOD REVERSE PERIOD
(PWM)
P1A 1
0
(PWM) ton
toff
t = toff - ton
1
0
1
0
1
0
1
0
1
0
1
0
P1B
P1C
P1D
Ext er nal Switch D
Potential
Shoot Through
Current
Note 1: All signals are shown as active high.
2: ton is the turn on delay of power switch and driver.
3: toff is the turn off delay of power switch and driver.
Ext er nal Switch C
t1
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DS41120C-page 64 1999-2013 Microchip Technology Inc.
8.3. 7 SYSTEM IMPLEMENTATION
When the ECCP mo dule is used in the PWM mo de, the
applic ation hardware m ust use the p roper external pull-
up and/or pull-down resistors on the PWM output pins.
When the mic roc on trol ler pow e rs up , all of the I/O pin s
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
8.3.8 START-UP CONSIDERATIONS
Prior to en ablin g the PW M output s, th e P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISB bits for output at the same time
with t he C C P m odu le may cause damage to the power
switch devices. The CCP1 module must be enabled in
the proper Output mode with the TRISB bits enabled as
inputs. Once the CCP1 completes a full PWM cycle,
the P1A, P1B, P1C and P1D output latches are prop-
erly initialized. At this time, the TRISB bits can be
enabled for outputs to start driving the power switch
devices. The completion of a full PWM cycle is indi-
cated by the TMR2IF bit going from a '0' to a '1'.
8.3.9 SET UP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM module:
a) Disable the CCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective
TRISB bits.
b) Set the PWM period by loading the PR2
register.
c) Set the PWM duty cycle by loading the
CCPR1L register and CCP1CON<5:4>
bits.
d) Config ure the EC CP mod ule for t he desired
PWM operation by loading the CCP1CON
register. With the CCP1M<3:0> bits select
the active high/low levels for each PWM
output. With the PWM1M<1:0> bits select
one of the available Output modes: Single,
Half-Bridge, Full-Bridge, Forward or Full-
Bridge Reverse.
e) For Half-Br idge Ou tput mode, s et the dead-
band delay by loading the P1DEL register.
2. Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescal e value by loa ding the
T2CKPS<1:0> bits in the T2CON register.
c) Enable Timer2 by setting the TMR2ON bit
in the T2CON register.
3. Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
become s a ’1’). T he new PWM cyc le begins
here.
b) Enable the CCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISB bits.
TABLE 8-3: REGISTERS ASSOCIATED WITH PWM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
1 0 Bh, 1 8 Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 register 0000 0000 0000 0000
92h PR2 Timer2 pe riod re gister 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
97h P1DEL PWM1 Delay value 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by ECCP module in PWM mode.
1999-2013 Microchip Technology Inc. Advance I n formation DS41120C-page 65
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9.0 MASTER SYNCHRONOUS
SERIAL PORT (MS SP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
periphera l or m icroc ontroll er dev ices. Th ese p eriphera l
devices may be serial EEPROMs, shift registers, dis-
play dri vers, etc. The M SSP module can op erate in one
of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I2C™)
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DS41120C-page 66 Advance Information 1999-2013 Microchip Technology Inc.
REGISTER 9-1: SYNC SERIAL PORT STATUS REGISTER (SSPSTAT: 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bi t 0
bit 7 SMP: Sa m ple bit
SPI Master Mode
1 = Input data sampled at end of da ta output time
0 = Input data sampled at mid dl e of data out put tim e
SPI S l ave Mode
SMP m ust be c le ar ed when SPI is us ed i n Slave mode
In I2C Master or Slave mode:
1= Slew rate control dis abled for Standar d Speed mode (10 0 kH z and 1 MHz)
0= Slew rate control enabled for High Speed mode (40 0 kH z )
bit 6 CKE: SPI Clock Edg e Select (Figure 9 -3 , Fig ure 9-5, and Figure 9-6)
CKP = 0
1 = Data transmi tte d on rising edge of S CK
0 = Data transmit ted on falling ed ge of SCK
CKP = 1
1 = Data transmit ted on falling ed ge of SCK
0 = Data transmi tte d on rising edge of S CK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicate s th at th e la st byt e received or transmitted was data
0 = Indicate s th at th e la st byt e received or transmitted was addr ess
bit 4 P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicate s th at a STOP bi t has been detecte d l ast (thi s bit is '0' on RE SET)
0 = STOP bit was not detected last
bit 3 S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates th at a START bit has bee n detected las t (this bit is '0' on RE SET)
0 = START bit w as not detected last
bit 2 R/W: Read/Write bit informatio n (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit, or NACK bit.
In I2 C Slave mod e:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Tran sm i t is no t in pr ogress.
ORing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode
bit 1 UA: Update Address (10-bit I2C mode only)
1 = Indicate s th at th e user need s to update the ad dress in the SSPADD reg is ter
0 = Address do es not nee d to be update d
bit 0 BF: Buffer Full St atus bit
Receive (SPI and I2 C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode onl y)
1 = Data Transmi t in progress (does not include t he ACK and STOP bits), S SPBUF is full
0 = Data Tra n s mit c o mp lete (d oes not in clude th e ACK and STOP bits), S SPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemen te d bi t , read as ‘0’
- n = Value at P O R ’1’ = Bit is set ’0’ = Bit is cle ar ed x = Bit is unknown
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REGISTER 9-2: SYNC SERIAL PORT CONTROL REGI STER (SSPCON: 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
Master Mode:
1 = A write to th e SSPBUF r egi ster wa s atte mp ted whi le th e I2C cond itions were not vali d for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new b yte is rec eived while th e SSPBUF regist er is stil l hold ing the p reviou s dat a. In c ase
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user m ust read th e SSPBUF, even if o nly trans mitting dat a, to avoid se tting ov er-
flow. In Mas ter m ode, th e over flow bit i s not se t sinc e each new r ecepti on (a nd tran smis-
sion) is initiated by writing to the SSPBUF register. (Must be cleared in software).
0 = No overflow
In I2 C mode
1 = A byte is receive d while the SSPBUF regis ter is still hol ding the previou s byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the I/O pins must be properly configured as input or output.
In SPI mode
1 = Enables s erial port and configure s SCK, SDO, SDI, an d SS a s the s ourc e of th e s eri al po rt
pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial
port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
In I2 C Slave mode SCK release control
1 = Enable clock
0 = Holds clock low (clock st retch) (use d to ensure data setup time)
In I2 C Master mode
Unused in this mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h) (CONTINUED)
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI S lave m od e, c lock = SC K pi n. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / ( 4 (SSPADD+1) )
1001 = Reserved
1010 = Reserved
1011 = Firmware controlled Master mode (slave idle)
1100 = Reserved
1101 = Reserved
1110 = 7-bit Slave mode with START and STOP condition interrupts
1111 = 10-bit Slave mode with START and STOP condition interrupts
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-3: SYNC SERIAL PORT CONTROL REGISTER2 (SSPCON2: 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (In I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge (NACK)
0 = Acknowledge (ACK)
bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only).
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence IDLE
bit 3 RCEN: Receive Enable bit (In I2C Master mode only).
1 = Enables Receive mode for I2C
0 = Receive IDLE
bit 2 PEN: STOP Condition Enable bit (In I2C Master mode only).
SCK Release Control
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
bit 1 RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
hardware.
0 = Repe ated START co ndition IDLE
bit 0 SEN: START Condition Enabled bit (In I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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DS41120C-page 70 Advance Information 1999-2013 Microchip Technology Inc.
9.1 SPI Mode
The SPI mode allows eight bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Ser ial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Sla ve Select (SS)
9.1.1 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase
(middle or end of data output t ime)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Figure 9-1 shows the block diagra m of the MSSP mod-
ule when in SPI mode.
FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The MSSP cons ists of a trans mit/recei ve Sh ift Regist er
(SSPSR) and a Buffer Register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR, until the received data is ready. Once the eig ht
bits of data have been received, that byte is moved to
the SSPBUF regi ster. Then the buf fer full dete ct bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF registe r com ple ted su cc es sfu lly.
Read Write
Internal
Data Bus
SSPSR reg
SSPBUF reg
SSPM<3:0>
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
Tosc
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX i n SSPSR
Data direction bit
2
SMP:CKE
SDI
SDO
SS
SCK
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When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSP-
BUF has bee n loaded with the recei ved data (trans mis-
sion is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be rea d and/or written. If the
inter rupt metho d is not going to be used, the n softw are
polling can be d one to ensure that a write collision does
not o ccu r. Example 9-1 shows the loading of the SSP-
BUF (SSPSR) for data transmission.
EXAMPLE 9-1: Loading the SSPBUF
(SSPSR) Register
The SSPSR is not directly readable or writable, and
can onl y be acce ss ed b y addressing the SSPBUF re g-
ister. Additionally, the MSSP STATUS register
(SSPSTAT) indicates the various status conditions.
9.1.2 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. Fo r the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is a utom at ic all y c ontrolled by t he SPI module
• SDO must have TRISB<5> cleared
• SCK (Master mode) must have TRISB<2>
cleared
• SCK (Slave mode) must have TRISB<2> set
•SS
must have TRISB<1> set, and ANSEL<5>
cleared
Any serial po rt function that is not desired may be ov er-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
9.1.3 TY PIC AL CONNEC TION
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (SSPCON<4>), then
both controllers would send and receive data at the
same tim e. Whet her the dat a is meaningful (or dum m y
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data—Slave sends dumm y data
• Master sends data—Slave sends data
• Master sends dummy data—Slave sends data
FIGURE 9-2: SPI MAST E R/S LAVE CONNECTION
BSF STATUS, RP0 ;Specify Bank 1
LOOP BTFSS SSPSTAT, BF ;Has data been
;received
;(xmit complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;Save SSPBUF...
MOVWF RXDATA ;...in user RAM
MOVF TXDATA, W ;Get next TXDATA
MOVWF SSPBUF ;New data to xmit
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM<3:0> = 00xx b
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCE SSO R 2
SCK
SPI Slave SSPM<3:0> = 010xb
Serial Clock
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9.1.4 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to broad-
cast dat a by the so ftware protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will conti nue to shif t in the signa l present on th e
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropr iately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSb
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the follow-
ing:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allo ws a maximu m bit clock freq uency (at 20 MHz)
of 8.25 MHz.
Figure 9-3 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
modes
Input
Sample
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
Next Q4 cycle
after Q 2
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9.1.5 SLAVE MODE
In Slave m ode , the data is trans mitted and receiv ed a s
the external clock pulses appear on SCK. When the
last bi t is latc hed th e inte rrupt flag bit SSPIF (PIR1<3 >)
is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
9.1.6 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISB<1> must be set. When the SS pin is low,
transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desir-
able, depending on the application.
When the SPI module RESETS, the bit counter is
forced to 0. This can be done by either forcing the SS
pin to a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it cann ot cre ate a bus con flict.
FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI module is in Slave mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
RESET if the SS pin is set to VDD.
2: If the SPI is used in Slave Mode with
CKE = '1', then SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7
SDO bit7 bit6 bit7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPS R to
SSPBUF
SS
Flag
bit0
bit7 bit0
Next Q4 cycle
after Q2
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FIGURE 9-5: SPI SLAVE MODE WAVEFORM (CKE = 0)
FIGURE 9-6: SPI SLAVE MODE WAVEFORM (CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
optional
Next Q4 cycle
after Q 2
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
not optional
Next Q4 cycle
after Q2
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9.1.7 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the SSPIF
interrupt flag bit will be set and if enabled will wake the
device from SLEEP.
9.1.8 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF —— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE ——SSPIECCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/T ransmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
9Dh ANSEL --11 1111 --11 1111
86h TRISB 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Sha ded cells are not used by the MSSP in SPI mode.
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9.2 MSSP I 2C Operation
The MSSP module in I2C mode fully implements all
master an d sla ve func tion s (in cl udi ng general call su p-
port) and pro vid es interrup ts on STAR T and ST O P bits
in hardware to determine when the bus is free (multi-
master function). The MSSP module implements the
Standard mode specifications, as well as 7-bit and 10-
bit addr essing.
Two pins are used to transfer data. They are the SCL
pin (clock) and the SDA pin (data). The MSSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>). The SCL and SDA pins are
"glitch" filtered when operating as inputs. This filter
functions in both the 100 kHz and 400 kHz modes.
When these pins operate as outputs in the 100 kHz
mode, ther e is a slew rate control of the pin that is inde-
pendent of device frequency.
Before selecting any I2C mode, the SCL and SDA pins
must be programmed as inputs by setting the appropri-
ate TRIS bits. This allows the MSSP module to configure
and drive the I/O pins as required by the I2C protocol.
The MSSP module has six registers for I2C operation.
They are list ed below.
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP STATUS Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not di rec tl y ac c essi ble
• SSP Address Register (SSPADD)
The SSPCON register allows for control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
configure the MSSP as any one of the following I2C
modes:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Master mode
SCL Freq = FOSC / [4 (SSPADD + 1)]
•I2C Slav e mode w ith START and STOP i nterrupt s
(7-bit address)
•I2C Slav e mode w ith START and STOP i nterrupt s
(10-bit address)
• Firmware Controlled Master mode
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit. It specifies whether the
received byte was data or address, if the next byte is
the completion of 10-bit address, and if this will be a
read or write data transfer.
SSPBUF is the register to which the transfer data is
written, and from which the transfer data is read. The
SSPSR register shifts the data in or out of the device.
In receive op eration s, the SSPBUF and SSPSR create
a doubled, buffered receiver. This allows reception of
the next byte to begin before reading the last byte of
receive d data. Whe n the complete byte is receiv ed, it is
transferred from the SSPSR register to the SSPBUF
register and flag bit SSPIF is set. If another complete
byte is received before the SSPBUF register is read a
receiver ov erflow occurs , in which cas e, the SSPOV bit
(SSPCON<6>) is set and the byte in the SSPSR is lost.
FIGURE 9-7: I2C SLAVE MODE BLOCK
DIAGRAM
9.2.1 UPWARD COMPATIBILITY WITH
SSP MODULE
The MSSP module in clude s three SSP modes of op er-
ation to maintain upward compatibility with the SSP
module. These modes are:
• Firmware controlled Master mode (slave idle)
• 7-bit Slave mode with START and STOP
conditi on inte rrupts.
• 10-bit Slave mode with START and STOP
conditi on inte rrupts.
The firmware controlled Master mode enables the
START and STOP condition interrupts but all other I2C
function s are gen erated through firmware inclu din g:
• Generating the START and STOP conditions
• Generating the SCL clock
• Supplying the SDA bits in the proper time and
phase relationship to the SCL signal.
In firmware controlled Ma st er m ode , the SCL an d SD A
lines a re manipu lated by c learing an d setting the corre-
spondin g TR IS bit s. The output level is al ways l ow i rre-
spective of the value(s) in the PORT register. A ‘1’ is
output by setting the TRIS bit and a ‘0’ is output by
clearing the TRIS bit
The 7-bit and 10-bit Slave modes with START and
STOP condition interrupts operate identically to the
MSSP Slave modes except that START and STOP
conditions generate SSPIF interrupts.
Read Write
SSPSR reg
Match detect
SSPADD reg
START and
STOP bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, RESET
S, P bits
(SSPSTAT reg)
RB2/SCK/
Shift
Clock
MSb LSb
SCL
RB4/SDI/
SDA
1999-2013 Microchip Technology Inc. Advance I n formation DS41120C-page 77
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For more information about these SSP mod es see Sec-
tion 15 of the PIC Mid-Range MCU Family Reference
Manual (DS33023).
9.2.2 SLAVE MODE
When an address is matched or the data transfer after
an add res s mat ch i s rece ived , th e ha rdw are au tom ati -
cally will generate the Acknowledge (ACK) pulse.
Then, it loads the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module to generate a NACK pulse in lieu of
the ACK pulse:
a) The buffer full bit BF (SSPSTAT<0>) is set
before the transfer is received.
b) The overflow bit SSPOV (SSPCON<6>) is set
before the transfer is received.
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF. However , both t he SSPIF and
SSPOV bits are set. Table 9-2 shows what happens
when a data transfer byte is received, given the status
of bit s BF and SSPOV. The sha ded cells show the co n-
dition where user software did not properly clear the
overflow condition. The BF flag bit is cleared by reading
the SSPBUF register. The SSPOV flag bit is cleared
through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of th e I2C specification as well as the requirements of
the MSSP module are shown in timing parameters
#100 and #101 of the Electrical Specifications.
9.2.2.1 7-BIT ADDRESSING
Once the MSSP module has been enabled
(SSPEN=1), the slave module waits for a START con-
dition to occur. Following the START condition, eight
bits are shifted into the SSPSR register. All incoming
bits are sampled on the rising edge of the clock (SCL)
line. The received address (register SSPSR<7:1>) is
compared to the stored address (register
SSPADD<7:1>). SSPSR<0> is the R/W bit and is not
consid ere d in the co mparison. Comparison is mad e o n
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
a) The SSPSR register value is transferred to the
SSPBUF register on the falling edge of the
eighth SCL pulse.
b) The bu ffer ful l bit; BF is set o n the falling e dge of
the eighth SCL pulse.
c) An ACK pulse is generated during the ninth
clock cycle.
d) SSP interrupt flag bit; SSPIF (PIR1<3>) is set
(interrupt is genera ted if e nabled ) - on the fallin g
edge of the ninth SCL pulse.
9.2.2.2 10-BIT ADDRESSING
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match are more complex.
Two address bytes need to be received by the slave.
The five Most Significant bits (MSbs) of the first
address byte specify that this is a 10-bit address. The
LSb of the first received address byte is the R/W bit,
which must be zero, specifying a write so the slave
device will receive the second address byte. For a 10-
bit address, the first byte equals ‘11110 A9 A8 0’,
where A9 and A8 are the two MSbs of the address. The
sequence of events for a 10-bit address is as follows,
with steps 7 through 9 applicable only to the slave-
transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT <1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the f irst (high)
byte of Address. This will clear bit UA and
release the SCL line.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive fi rst (hi gh) by te of Address w ith R/W bit
set to 1 (bits SSPIF and BF are set). This also
puts the MSSP module in the Slave-transmit
mode.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note: Following the Repeated START condition
(step 7) in 10-bit mode, the user only
needs to match th e first 7-bi t address. Th e
user does not update the SSPADD for the
second half of the address.
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9.2.2.3 SLAVE RECEPTION
When the R/W bit of the address byte is clear
(SSPSR<0> = 0) and an a ddre ss mat ch o ccurs , the R/
W bit of the SSPSTAT register is cleare d. The re ceived
address is loaded into the SSPBUF register on th e fall-
ing edge of the eighth SCL pulse.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) or
bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. F lag bit SSPIF (PIR1<3>) must be cle ared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS
FIGURE 9-8: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is update d.
Status Bits as Data
Transfer is Received
SSPSR SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
0 0 Yes Yes Yes
1 0 No No Yes
1 1 No No Yes
0 1 Yes No Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
P
9
8
76
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
NACK
NACK is sent because of overflow
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FIGURE 9-9: I2C SLAVE MODE FOR RECEPTION (10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456 789 1 23456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in softwa re
Bus Master
terminates
transfer
D2
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
Cleared in software
Dummy read of SSPBUF
to clear BF flag Read of SSPBUF
clears BF flag
Cleared by hardware when
SSPADD is updated with high
byte of address.
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9.2.2.4 SLAVE TRANSMISSION
When the R/W bit of th e incoming addres s byte is se t
and an address match occurs, the R/W bit of the SSP-
STAT register is set. The received address is loaded
into the SSPBUF register on the falling edge of the
eighth SCL pulse. The ACK pulse will be sent on the
ninth bit , and the SCL pin i s held low . Th e slave modul e
automatically stretches the clock by holding the SCL
line low so that the master will be unable to assert
another c lock pulse u ntil the slav e is fin ished prep aring
the transmit data. The transmit data must be loaded
into the SSPBUF register, which a lso loads th e SSPSR
register. The CKP bit (SSPCON<4>) must then be set
to release the SCL pin from the forced low condition.
The eight data bits are shifted out on the falling edges
of the SCL input. This ensures that the SDA signal is
valid during the SCL high time (Figure 9-10).
The ACK or NACK signal from the master-receiver is
latched on the rising edge o f the ni nth SC L inpu t pulse.
The master-receiver terminates slave transmission by
sending a NACK. If the SDA line is high (NACK), then
the data transfer is complete. When the NACK is
latched by the slave, the slave logic is RESET which
also resets the R/W bit to '0'. The slave module then
monitors for another occurrence of the START bit. The
slave firmware knows not to load another byte into the
SSPBUF register by sensing that the buffer is empty
(BF = 0) and the R/W bit has gone low. If the SDA line
is low (ACK), the R/W bit remains high indicating that
the next transmit data must be loaded into the SSPBUF
register.
An MSSP interrupt (SSPIF flag) is generated for each
data transfer byte on the falling edge of the ninth clock
pulse. The SSPIF flag bit must be cleared in software.
The SSPSTAT register is used to determine the status
of the byte transfer.
For more information about the I2C Slav e mode, re fer
to Application Note AN734, “Using the PIC® SSP for
Slave I2C™ Communication”.
FIGURE 9-10: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
Transmitting Data
R/W = 1
Receiving Address
123456789 123456789 P
cleared in software
SSPBUF is written in software From SSP interrupt
service ro utine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
until SSPBUF
is written
(the SSPBUF must be written-to
before the CKP bit can be set)
R/W 0
Master terminates transmission
by responding with NACK
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FIGURE 9-11: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S1234567891
2345678912345 789 P
11110A9A8 A7A6A5A4A3A2A1A0 11110 A8
R/W=1ACK
ACK
ACK
Receive First Byte of Address
Cleared in software
Master sends NACK
A9
6
(PIR1<3>)
Receive Second Byte of Addre ss
Cleared by hardware when
SSPADD is updated.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1 NACK
D2
6
Transmitting Data Byte D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Transmit is complete
CKP has to be set for clock to be released
Master releases
bus with STOP
condition
R/W=0 R/W0
Restart condition
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9.2.3 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is su ch that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is set (SSPCON2<7> is
set). Fo llowing a START bit detect, eight bits are shif ted
into the SSPSR, and the address is compared against
SSPADD. It is also compared to the general call
address, fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF flag is set.
When the i nterrupt is servic ed, t he sou r ce f or the int er-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific or a gener al call address.
If the general call address is sampled with GCEN set
and the slave configured in 10-bit Address mode, the
second half of th e address is not n ecessary. The UA b it
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 9-12).
FIGURE 9-12: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7- OR 10-BIT MODE)
SDA
SCL S
SSPIF
BF
SSPOV
Cleared in softwa re
SSPBUF is read
R/W = 0ACK
General Call Address
Address is compared to General Call Address
GCEN
Receiving data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt flag
'0'
'1'
(SSPSTAT<0>)
(SSPCON<6>)
(SSPCON2<7>)
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9.2.4 SLEEP OPERATION
While in SLEEP mode, the I2C slave module can
receive addresses or data. When an address match or
complete byte transfer occurs, it wakes the processor
from SLEEP (if the SSP interrupt bit is enabled).
9.2.5 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
9.2.6 MASTER MODE
Master mode operation supports interrupt generation
on the detection of the START and STOP conditions.
The STOP (P) and START (S) bits are cleared from a
RESET or when the MSSP module is disabled. Control
of t he I2C bus may be t aken wh en the P bit is s et or the
bus is idle with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit
(SSPIF) to be set (SSP Interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeat ed START
FIGURE 9-13: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Read Write
SSPSR
START bit, STO P bi t,
START bit detect,
SSPBUF
Internal
Data Bus
Set/RESET, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
STOP bit detect
Write collision detect
Clock Arbitration
S tate counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable
clock cntl
clock arbitrate/WCOL detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
RESE T ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM<3:0>,
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9.2.7 MULTI-MASTER OPERATION
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP modul e is dis abl ed . Contro l of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expect ed output level. This c heck is perfo rmed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Refer to Application Note AN578, "Use of the SSP
Module in the I2C™ Multi-Master Environment."
9.2.8 I2C MASTER OPERATION
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has si x opti ons .
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to th e SSPBUF register initiati ng transmis-
sion of data/address.
4. Generate a STOP condition on SDA a nd SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
The master device g enerates all serial clock pulses an d
the START and STOP conditions. A transfer is ended
with a ST OP c ondit ion or with a Repeated START con-
dition. Since the R epeate d START condi tion i s also th e
beginni ng of the next serial tra nsfer , the I2C bus will not
be released.
9.2.9 BAUD RATE GENERATOR
The baud rate generator used for SPI mode operation
is used in the I2C Mas ter mode to set th e SCL clock f re-
quency. Standard SCL clock frequencies are 100 kHz,
400 kHz, and 1 MH z. One of the se frequ enc ies can be
achiev ed b y setti ng th e SSPADD registe r to the app ro-
priate number for the selected Fosc frequency. One
half of the SCL period is equal to
[(SSPADD+1) 2]/Fosc.
The baud rate generator reload value is contained in
the lower seven bits of the SS PADD register (Figure 9-
14). When the BRG is loaded with this value, the BRG
count s down to 0 a nd stops u ntil another relo ad occurs.
The BRG count is decremented twice per instruction
cycle (TCY) on the Q2 and Q4 clock.
In I2C Mas ter mode, the BRG is rel oaded autom aticall y
provided that the SCL line is sampled high. For exam-
ple, if Clock Arbitration is taking place, the BRG reload
will be s up pres s ed unti l t he SCL line is rel ea sed by th e
slave allowing the pin to float high (Figure 9-15).
FIGURE 9-14: BAUD RATE GENERATOR
BLOCK DIAGRAM
Note: The MSSP Module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
SSPM<3:0>
BRG Down Counter
BRG CLKOUT Fosc/2
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control Reload
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FIGURE 9-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
9.2.10 I2C MASTER MODE START
CONDITION TIMING
To initiate a START co nditio n, the user set s the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL p ins are sam pled h igh, ind icating th at the bu s
is available, the baud rate generator is loaded with the
contents of SSPADD<6:0> and starts its count. If SCL
and SDA are both sampled high when the baud rate
generator times out (TBRG) indicating the bus is still
available, the SDA pin is driven low . The SDA transition
from high to lo w w hil e SCL is hi gh i s th e START cond i-
tion. This causes the S bit (SSPSTAT<3>) to be set.
When the S bit is set, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
resume s its count. Whe n the ba ud rate generator time s
out (TBRG) the START condition is complete, concur-
rent with the following events:
• The SEN bit (SSPCON2<0>) is automatically
cleared by hardware,
• The baud rate genera tor is sus pended l eaving th e
SDA line held low.
• The SSPIF flag is set.
9.2.10.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a START
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur ).
FIGURE 9-16: FIRST START BIT TIMING
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place, and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
reload
BRG
value
SCL low (clock arbitration) SCL allowed to transition hig h
BRG decrements
(on Q2 and Q4 cycles)
Note: If at the begi nni ng of START co nd itio n, th e
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs.
Thus, the Bus Collision Interrupt Flag
(BCLIF) is set, the START condition is
aborted, a nd the I2C module i s RESET into
its IDLE state.
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPCON2 is disabled until the START
conditi on is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, At com pletion of START bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here. Set S bit (SSPSTAT<3>)
and sets SSPI F bit
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9.2.11 I2C MASTER MODE REPEA TED
START CONDITION T IMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is set high while the I2C module is
in the id le st ate. W hen the RSEN bit is set , the SC L pin
is asserted low. When the SCL pin is sampled low, the
baud rate generator is loaded with the contents of
SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (TBRG). Wh en the baud ra te gene rator tim es out,
if SDA i s samp led high, the SCL pi n will be de-asserte d
(brought high). When SCL is sampled high, the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled h igh for o ne TBRG peri od. Thi s actio n
is then followed by assertion of the SDA pin (SDA is
low) fo r one TBRG period while SCL is high. As soon as
a START condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. Following
this, the baud rate generator is reloaded with the con-
tents of SSPAD<6:0> and begins counting. When the
BRG times out a third time, the RSEN bit in the
SSPCON2 registe r is auto maticall y cleare d and SCL is
pulled low. The SSPIF flag is set, which indicates the
Restart sequence is complete.
Immediately following the SSPIF bit transition to true,
the user may write the SSPBUF with the 7-bit address
in 7-bit mode, or the default first address in 10-bit
mode. After the first eight bits are transmitted and an
ACK is receiv ed , the use r ma y th en perform one of th e
following:
• Transmit an additional eight bits of address (if the
user transmitted the first half of a 10-bit address
with R/W = 0),
• Transmit eight bits of data (if the user transmitted
a 7-bit address with R/W = 0), or
• Receive eight bits of data (if the user transmitted
either the first half of a 10-bit address or a 7-bit
address with R/W = 1).
9.2.11.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated
START sequence is in progre ss, then WCOL i s set and
the contents of the buffer are unchanged (the write
doesn’t occur).
FIGURE 9-17: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is set while another event is in
progre ss, it will not t ake ef fect. Que uing of
events is not allowed.
2: A bus collision during the Repeated
START condition occurs if either of the
following is true:
a) SDA is sampled low when SCL
goes from low to high.
b) SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data “1”.
Note: Because queueing of events is not
allowed, writing of the lower five bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
SDA
SCL
Sr = Repeated START
Write to SSPCON2
Write to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of START bit,
hardware clears RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change) SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
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9.2.12 I2C MASTER MODE
TRANSMISSION
In Master-transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains seven bits of address
data and the Read/Write (R/W) bit. In this case, the R/
W bit will be logic '0'. Subsequent serial data is trans-
mitted eight bits at a time. After each byte is transmit-
ted, an Ac knowledge bit is rec eived. START and ST OP
conditions are output to indicate the beginning and the
end of a seria l transfe r.
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit a dd ress i s ac com pl is hed b y s im pl y writ-
ing a val ue to the SSPBUF regi ste r. This action wil l s et
the buf fe r full fl ag (BF) and allow th e baud ra te gene ra-
tor to begin counting and start the next transmission.
Each bit of address/data will be shifted out onto the
SDA pin after the falling edge of SCL is asserted (see
data hold t ime s pec). SCL is he ld low for o ne bau d rate
generator roll over count (TBRG). Data should be valid
before SCL is released high (see data setup time
spec). Wh en the SCL pin is rel eased high, it is he ld that
way for TBRG, the data on the SDA pin must remain st a-
ble for that duration and some hold time after the next
falling edge of SCL. After the eighth bit is shifted out
(the falling edge of the eighth clock), the BF flag is
clear ed a nd th e ma ste r rel eas es SD A. T his allow s t he
slave device being addressed to respond with an ACK
bit during the ninth bit time. The status of ACK is re ad
into the ACKDT on the risi ng edg e of the ni nth cl oc k. If
the master receives an Acknowledge, the Acknowl-
edge status bit (ACKSTAT) is cleared. Otherwise, the
bit is set. The SSPIF is set on the falling edge of the
ninth cl ock, a nd the ma ster cl ock (b aud rate generat or)
is suspended until the next data byte is loaded into the
SSPBUF leaving SCL low and SDA unchanged
(Figure 9-18).
A typical transmit sequence would go as follows:
a) The user generates a START Condition by set-
ting the STAR T enab le bit (SEN) in SSPCON2.
b) SSPIF is set at the completion of the START
sequence.
c) The user resets the SSPIF bit and loads the
SSPBUF with seven b its of add ress plus R/W bit
to transmit.
d) Addres s and R/W is shifted out the SDA pin until
all eight bits are transmitted.
e) The MSSP Modu le shift s in the ACK bi t from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) Th e mo dul e generates a n i nte rrup t at the en d of
the ninth clock cycle by setting SSPIF.
g) The user resets the SSPIF bit and loads the
SSPBUF with eight bits of data.
h) DAT A is shif ted out the SDA pin until all eight bits
are transmitted.
i) The MSSP M odule shift s in the ACK bi t f rom th e
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The M SSP mo dule g enerate s an int errupt a t th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
k) The user resets the SSPIF bit and generates a
STOP co nditi on by se ttin g t he STOP ena ble bi t
PEN in SSPCON2.
l) SSPIF is set when the ST OP condition is complete.
9.2.12.1 BF STATUS FLAG
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
9.2.12.2 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.2.12.3 ACKSTAT STATUS FLAG
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the sl ave does not Acknowl-
edge (ACK = 1). A slave sends an Ac knowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
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FIGURE 9-18: I2C MASTER MODE WAVEFORMS FOR TRANSMISSION (7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0
NACK
Transmittin g Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
cleared in software service routine
SSPBUF is written in software
From SSP in ter rup t
After START condition SEN c leared by hardware.
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
SEN = 0
of 10-bit Addre ss
Write SSPCON2 < 0> SEN = 1
START condition begins ACK from slave clea rs ACKSTAT bit (SSPCON2<6>)
cleared in software
SSPBUF written
PEN
Cleared in software
PEN is set to initiate STOP condition
NACK from slave sets ACKSTAT bit (SSPCON2<6>)
until SSPBUF is
written.
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9.2.13 I2C MASTER MODE RECE PTI ON
In Master-receive mode, the first byte transmitted con-
ta ins seve n bits of address data an d the R/W bit. In this
case, the R/W bit will be logic '1'. Thus, the first byte
tran sm it te d i s a 7- bit s la ve ad d res s f o ll ow ed by a ' 1' to
indicate receive. Serial data is received via SDA, while
SCL outputs the serial clock. Serial data is received
eight bits at a time. After each byte is received, an
Acknowledge bit is transmitted. The START condition
indicates the beginning of a transmission. The master-
receiver terminates slave transmission by responding
to the last byte with a NACK Acknowledge and follows
this with a STOP condition to indicate to other masters
that the bus is free.
Master mode reception is enabled by setting the
receive enable bit, RCEN (SSPCON2<3>), immedi-
ately following the Acknowledge sequence.
The baud rate generator b egi ns cou nti ng, and on eac h
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the fallin g edge of the eighth cl ock, the follow ing event s
occur:
• The receive enable bit is automatically cleared.
• The contents of the SSPSR are loaded into the
SSPBUF.
• The BF flag is set.
• The SSPIF is set.
• The baud rate generator is suspended from
counting, holding SCL low.
The SSP is now in IDLE state, awaiting the next com-
mand. Whe n the buf fer is read by the CPU, the BF flag
is automatically cleared. The user can then send an
Acknow ledge bit a t the e nd of recept ion by clea ring th e
ACKDT bit (SSPCON2<5>) and setting the Acknowl-
edge sequence enable bit, ACKEN (SSPCON2<4>).
A typical receive sequence would go as follows:
a) The user generates a START Condition by set-
ting the STAR T enab le bit (SEN) in SSPCON2.
b) SSPIF is set at the completion of the START
sequence.
c) The user resets the SSPIF bit and loads the
SSPBUF with seven b its of a ddress in the MSbs
and the LSb (R/W bit) set to '1' for receive.
d) Addres s and R/W is shifted out the SDA pin until
all eight bits are transmitted.
e) The MSSP Modu le shift s in the ACK bi t from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) Th e mo dul e generates a n i nte rrup t at the en d of
the ninth clock cycle by setting SSPIF.
g) The user resets the SSPIF bit and sets the
RCEN bit to enable reception.
h) DATA is shifted into the SDA pin until all eight
bits are received.
i) The MSSP module set s the SSPIF bit and clears
the RCEN bit at the falling edge of the eighth
clock.
j) The user resets the SSPIF bit and sets the
ACKDT bit to '0' (ACK), if another byte is antici-
pated. Otherwise, the ACKDT bit is set to '1'
(NACK) to terminate reception. The user sets
ADKEN to start the Acknowledge sequence.
k) The MSSP module sets the SSPIF bit at the
completion of the Acknow ledge.
l) If a NACK was sent in step ( j), then the user pro-
ceeds with step ( m). Otherwise, reception con-
tinues by repeating steps ( g) through ( j).
m) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
n) SSPIF is set when the STOP condition is complete.
9.2.13.1 BF STATUS FLAG
In receiv e operation, BF is se t when an addr ess or data
byte is loaded into SSPBUF from SSPSR. It is cleared
by hardware when SSPBUF is read.
9.2.13.2 SSPOV STATUS FLAG
In receive operation, SSPOV is set when eight bits are
received in to the SSPSR and the BF flag is alread y set
from a previous reception.
9.2.13.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP Module must be in an IDLE
STATE before the RCEN bit is set or the
RCEN bit will be disregarded.
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FIGURE 9-19: I2C MASTER WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus Master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
Master sends NACK to
Write to SSPCO N2<0 >, (SEN = 1)
Write to SSPBUF ACK from Slave
Master configured as a receiv e r
by programming SSPCON2<3>, (RCEN = 1) PEN bit = 1
written her e
Data shifted in on falling edge of CLK
starts transmit
SEN = 0
(SSPSTAT<0>)
NACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPIF occurs
at end of receive
SSPIF occurs at end
ACK from Master
SSPIF occurs at
SSPIF occurs
at end of Acknowledge
sequence
SSPIF occurs
at end of Acknow-
ledge sequ en ce
end of receive
RCEN clear ed
automatically
RCEN = 1 to start
next receive
and set ACKEN (SSPCON2<4>) = 1
to start ACK Acknowledge sequence
Set ACKDT (SSPCON2<5>) = 0
RCEN clear ed
automatically
ACKEN
Begin START Condition
Cleared in software
SDA = ACKDT = 0
Writing SSPBUF causes
BF to go high
SSPIF occurs at end of transmit
SSPIF occurs at end of Start
terminate slave transmission
and set ACKEN (SSPCON2<4>) = 1
to start NACK Acknowledge sequence
Set ACKDT (SSPCON2<5>) = 1
of STOP sequence
SSPBUF is read
clearing BF flag
ACKEN bit is set to initiate
Acknowledge sequence ACKEN is cleared by hardware
BF clears automatically
when the last bit is shifted out.
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9.2. 14 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
ACKDT (SSPCON2<5>) is presented on the SDA pin.
If the user wishes to generate an Acknowledge (ACK),
then the ACKDT bit should be cleared. Otherwise, the
user should set the ACKDT bit (NACK) before starting
an Ackno wledge seq uence. The baud rat e generator i s
then loaded from SSPADD<6:0> and counts for one
rollove r period (TBRG). The SCL pin is then de-asserted
(pulled hig h). When the SCL pin is sa mpled high (cl ock
arbitration), the baud rate generator is reloaded and
count s for anothe r TBRG. At the comp letion of the TBRG
period, the following events occur (see Figure 9-20):
• The SCL pin is pulled low.
• The ACKEN bit is automatically cleared.
• The baud rate generator is turned off.
• The MSSP module goes into IDLE mode.
9.2.14.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an Acknowledge
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-20: ACKNOWLEDGE SEQUEN CE WAVEFORM
Note: TBRG = one baud rate generator period.
SDA
SCL
SSPIF occ u rs at the
Acknowledge sequence starts here,
Write to SSPCON 2 ACKEN automatically cleared
Cleared in
TBRG TBRG
end of receive
ACK
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SS PIF occ urs at the end
of Acknowledge sequence
Cleared in
software
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9.2.15 STOP CONDITION TIMING
The master asserts a STOP condition on the SDA and
SCL pin s at th e end o f a rece ive/tra nsmit by settin g the
S top Sequence Enable bit PEN (SSPCON2<2>). At the
end of a receive/transmit plus Acknowledge, the SCL
line is he ld low immediat ely followi ng the falling edg e of
the ninth SCL pu lse. Wh en the PEN bit is se t, the ma s-
ter will assert the SDA line low. When the SDA line is
sampled low, the baud rate generator is loaded from
SSPADD<6:0> and counts down to 0. When the baud
rate generator times out, the SCL pin is brought high,
the BRG is relo ade d and one TBRG (bau d rate gene ra-
tor rollover count) later, the SDA pin is de-asserted.
The SDA pin transition from low to high while SCL is
high is the ST OP co ndi tio n and cause s the P bit (SSP-
STAT<4>) to be set. Following this the baud rage gen-
erator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the baud rate generator
times out (TBRG) th e STOP cond ition is complete and
the PEN bit is cleared and the SSPIF bit is set
(Figure 9-21).
Whenever the firmware decides to take control of the
bus, it should f irst determ ine if the bus is busy by ch eck-
ing the S a nd P bit s in the SSPSTAT register. When the
MSSP module detect s a START or ST OP con dition th e
SSPIF flag is set. If the bus is busy (S bit is set), then
the CPU can be configured to be interrupted when
when the bus is free by enab ling the SSPIF interrup t to
detect the STOP bit.
9.2.15.1 WCOL STATUS FLAG
If the use r writes t he SSPBUF when a STO P sequenc e
is in progress, then WCOL is set and the content s of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-21: STOP COND ITION RECEIVE OR TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON 2
Set PEN
Falling edge of
9th clock
SCL brought high after TBRG
Note: TBRG = one baud rate generator period.
TBRG TBRG
P bit (SSPSTAT<4>) is set
TBRG
to setup STOP condition.
NACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
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9.2.16 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin i s actua ll y sa mpled high. Wh en the SC L p in i s
sample d high, the baud rate gen erator is reloa ded wi th
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least on e BRG rollov er count in th e event tha t the cloc k
is held low by an external device (Figure 9-22).
FIGURE 9-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count BRG overflow occur s,
Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting
clock high interval.
SCL line sampled once every machine cycle (Tosc 4).
Hold off BRG until SCL is sampled high.
TBRG TBRG TBRG
to measure high time interval
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9.2.17 MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, bus ar bi trati on is init iate d w hen one ma s-
ter outputs a '1' on SDA (by letting SDA float high) and
another master asserts a '0'. If the expected data on
SDA is a '1 ' and the da ta s ampled o n the SD A pin = '0',
then a bus collision has taken place. The master that
expected a ‘1’ will set the Bus Collision Interrupt Flag,
BCLIF, and reset the I2C port to its IDLE state.
(Figure 9-23).
A bus collision during transmit results in the following
events:
• The transmission is halted.
• The BF flag is cleared
• The SDA and SCL lines are de-asserted
• The restriction on writing to the SSPBUF during
transmission is lifted.
When the user services the bus collision interrupt ser-
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.
A bus collision during a START, Repeated START,
STOP or Acknowledge condition results in the foll owing
events:
• The condition is aborted.
• The SDA and SCL lines are de-asserted.
• The respect ive cont rol bit s in th e SSPCON2 regis -
ter are cleared.
When the user services the bus collision interrupt ser-
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.
The Master will continue to monitor the SDA and SCL
pins, an d if a ST OP cond ition occ urs, the SSPIF b it will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be t aken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 9-23: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt.
by the master.
by master
Data changes
while SCL = 0
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9.2.17.1 BUS COLLISION DURING A START
CONDITION
During a START condition, a bus collision occurs if:
a) SDA or SC L are sampled low at the begi nning of
the START condition (Figure 9-24).
b) SCL is sampled low before SDA is asserted low.
(Figure 9-25).
During a START condition both the SDA and the SCL
pins are monitored.
If: the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
whil e SD A is hi g h, a bus co l li si o n oc cur s, be ca use it is
assumed that another master is attempting to drive a
data '1 ' during the START cond iti on.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-26). If however a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
count s down to 0, and during thi s time, if the SCL pin is
sampled as '0', a bus collision does not occur. At the
end of the BRG count the SCL pin is asserted low.
FIGURE 9-24: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus mas ters can a ssert a START condi tion
at the exact same time. Therefore, one
master will always assert SDA before the
other. This conditio n does no t cause a bus
collis ion, because the two masters must be
allow ed to arbitrate t he first addres s follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continu e in to t he d ata portio n, REPEATED
START or STOP conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into IDLE state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable START
condition if SDA = 1, SCL=1
SDA = 0, SCL = 1
BCLIF
S
SSPIF
SDA = 0, SCL = 1
SSPI F an d BCLIF ar e
cleared in software.
SSPIF and BCLIF are
cleared in software.
Set BCLIF,
Set BCLIF.
START condition.
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FIGURE 9-25: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 9-26: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA
SCL
SEN Bus collision occurs, Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable START
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupts cleared
in software.
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
'0'
'0'
'0'
'0'
SDA
SCL
SEN
Set S
Set SEN, enable START
sequence if SDA = 1, SCL = 1
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
s
Interrupts cleared
in software.
Set SS PIF
SDA = 0, SCL = 1
SDA pulled low by other master.
Reset BRG and assert SDA
SCL pulled low after BRG
Time-out
Set SS PIF
'0'
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9.2.17.2 BUS COLLISION DURING A REPEATED
START CONDITION
During a Repeated START condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’ .
When the master module de-asserts SDA and the pin
is allowed to float high, the BRG is loaded with
SSPADD<6:0>, and count s dow n to ‘0’. The SCL pin is
then de-asserted, and when sampled high, the SDA pin
is sampled. If SDA is low, a bus collision has occurred
(i.e., another master is attempting to transmit a data
’0’). If however SDA is sampled high, then the BRG is
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs,
becaus e no tw o maste rs can a ssert SDA at exactl y the
same time.
If, however, SCL goes from hig h to low before the BRG
times ou t and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
START condition.
If at the end of the BRG time-out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is
reloaded , and begins cou nting. At the end of the c ount,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is com-
plete (Figure 9-27).
FIGURE 9-27: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 9-28: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
Cleared in software
'0'
'0'
'0'
'0'
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
TBRG TBRG
'0'
'0'
'0'
'0'
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9.2.17.3 BUS COLLISION DURING A STOP
CONDITION
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low bef ore SDA goes hig h.
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the baud rate generator is loaded with SSPADD<6:0>
and count s down to ‘0’. After the BRG tim es out SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a d at a '0 ' (Fig ure 9-29 ). If the SCL pin is s am ple d
low before SDA is allowed to float high, a bus collision
occurs. This is an other case of another master attempt-
ing to drive a data '0' (Figure 9-30).
FIGURE 9-29: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 9-30: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
Set BCLIF
'0'
'0'
'0'
'0'
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high
Set BCLIF
'0'
'0'
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9.2.18 CONNE CTION CONSIDERATIONS
FOR I2C BUS
For Standard mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-31 depends on the fol-
lowing parameters
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
leakage current).
The sup ply v olt age limi ts the m inimu m va lue of res istor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
example, with a supply voltage of VDD = 5V+10% a nd
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 k VDD as a function of Rp is shown in Figure 9-31.
The desired noise margin of 0.1VDD for the low level
limits the maximum value of Rs. Series resistors are
optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connec tions, and p ins. This c apacit ance limit s the m ax-
imum value of Rp due to the specified rise time
(Figure 9-31).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
FIGURE 9-31: SAMPLE DEVICE CONFIGURATION FOR I2C BUS
TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF ——SSPIFCCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE —— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Dh PIR2 LVDIF — — —BCLIF — — CCP2IF 0--- 0--0 0--- 0--0
8Dh PIE2 LVDIE — — —BCLIE — — CCP2IE 0--- 0--0 0--- 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/T ransmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
93h SSPADD Synchronous Serial Port (I2C Mode) Address Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the MSSP in I2C mode.
RpRp
VDD + 10%
SDA
SCL
Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
DEVICE
Cb=10 pF to 400 pF
RsRs
connected.
PIC16C717/770/771
DS41120C-page 100 Advance Information 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 101
PIC16C717/770/771
10.0 VOLTAGE REFERENCE
MODULE AND LOW-VOLTAGE
DETECT
The Voltage Reference module provides reference
voltages for the Brown-out Reset circuitry , the Low-volt-
age Detect circuitry and the A/D converter.
The source for the reference voltages comes from the
bandgap ref erence circu it. The band gap ci rcuit is en er-
gized anytime the reference voltage is required by the
other sub-modules, and is powered down when not in
use. The c ontrol re giste rs fo r this mo dule are LVDCON
and REFCON, as shown in Register 10-1 and
Figure 10-2.
REGISTER 10-1: LOW-VOLTAGE DETECT CONTROL REGISTER (LV DCON: 9Ch)
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
—— BGST LVDEN LV3 LV2 LV1 LV0
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5 BGST: Bandgap Stable Status Flag bit
1 = Indicates that the bandgap voltage is stable, and LVD interrupt is reliable
0 = Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled
bit 4 LVDEN: Low-volt age Detect Power Enab le bit
1 = Enables LVD, powers up bandgap circuit and reference generator
0 = Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL
bit 3-0 LV<3:0>: Low Voltage Detection Limit bits(1)
1111 = External analog input is used
1110 = 4.5V
1101 = 4.2V
1100 = 4.0V
1011 = 3.8V
1010 = 3.6V
1001 = 3.5V
1000 = 3.3V
0111 = 3.0V
0110 = 2.8V
0101 = 2.7V
0100 = 2.5V
0011 = Reserved. Do not use.
0010 = Reserved. Do not use.
0001 = Reserved. Do not use.
0000 = Reserved. Do not use.
Note: These are the min imum trip points fo r the LVD. See Table 15-8 for the trip point to l-
erances. Selection of reserved setting may result in an inadvertent interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 102 1999-2013 Microchip Technology Inc.
REGISTER 10-2: VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 9BH)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
VRHEN VRLEN VRHOEN VRLOEN ————
bit 7 bit 0
bit 7 VRHEN: Voltage R eference High Enable bit (VRH = 4.096V nominal)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL
bit 6 VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V nominal)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH
bit 5 VRHOEN: High Voltage Reference Output Enable bit(1)
1 = Enabled, VRH analog reference is output on RA3 if enabled (VRHEN = 1)
0 = Disabled, analog reference is used internally only(1)
bit 4 VRLOEN: Low Voltage Reference Output Enable bit
1 = Enabled, VRL analog reference is output on RA2 if enabled (VRLEN = 1)
0 = Disabled, analog reference is used internally only
bit 3-0 Unimplemented: Read as '0’
Note 1: RA2 and RA 3 must be co nfigured as analog in puts when the VREF output functions
are enabled (See ANSEL on page 25).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 103
PIC16C717/770/771
10.1 Bandgap Voltage Reference
The bandgap module gen erat es a st able volt a ge refer-
ence of over a range of temperatures and device sup-
ply voltages. This module is enabled anytime any of the
following are enabled:
• Brown-out Reset
• Low-vo lt a ge D etec t
• Either of the internal analog references (VRH,
VRL)
Whenever the above are all disabled, the bandgap
module is disabled and draws no current.
10.2 Internal VREF fo r A /D C o n verter
The bandgap output voltage is used to generate two
stable references for the A/D converter module. These
references are enabled in software to provide the user
with the means to turn them on and off in order to min-
imize curre nt consumption. Each ref erence can be indi-
vidually enabled.
The V RH re f ere nc e is en a ble d w i th co nt ro l bi t V RH EN
(REFCON<7>). When this bit is set, the gain amplifier
is enabled. After a specified start-up time a stable ref-
erence of 4.096V nominal is generated and can be
used by the A/D converter as a reference input.
The VRL reference is enabled by setting control bit
VRLEN (REFCON<6>). When this bit is set, the gain
amplifier is enabled. After a specified start-up time a
stable reference of 2.048V nominal is generated and
can be use d by the A/D co nverte r as a referen ce input.
Each vol tag e referen ce is a vailable for exte rnal us e via
VRL and VRH pins.
Each reference, if enabled, can be output on an exter-
nal pin by setting the VRHOEN (high reference output
enable) o r VRLOEN (low refe rence output ena ble) con-
trol bit. If the reference is not enabled, the VRHOEN
and VRLOEN bits will have no effect on the corre-
sponding pin. The device specific pin can then be used
as general purpose I/O.
FIGURE 10-1: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT
Note: If VRH or VRL is enabled and the other ref-
erence (VRL or VRH), the BOR, and the
LVD modules are not enabled, the band-
gap will require a start-up time before the
bandgap reference is stable. Before using
the intern al V RH or VRL re ference , ensu re
that the bandgap reference voltage is sta-
ble by moni toring the BGST bit in the LVD-
CON register. The voltage references will
not be reliable until the bandgap is stable
as shown by BGST being set.
VDD
generates
16 to 1 MUX
BGAP
VRH
VRL
LVDEN
LVDCON REFCON
BODEN
LVDEN VRHEN + VRLEN
RA1/AN1/LVDIN LVDIF
PIC16C717/770/771
DS41120C-page 104 1999-2013 Microchip Technology Inc.
10.3 Low Voltage Detect (LVD)
This module is used to generate an interrupt when the
supply voltage falls below a specified “trip” voltage.
This module operates completely under software
control. This allows a user to power the module on
and off to periodically monitor the supply voltage, and
thus minimize total current consumption.
The LVD module is enable d by setting the LVDEN b it in
the LVDCON register. The “trip point” voltage is the
minimum supply voltage level at which the device can
operate before the LVD module asserts an interrupt.
When the supp ly voltage is equa l to or less than the tri p
point, the module will generate an interrupt signal set-
ting inte rrupt flag bit LVDIF. If inter rupt enable bit LVDIE
was set, then an interrupt is generated. The LVD inter-
rupt can wake the device from SLEEP. The "trip point"
volt age is sof tware pr ogrammab le to any one of 16 va l-
ues , five of w h ic h a re r es e rv e d ( See Fi g ur e 10-1) . T he
trip poi nt is selec ted by pr og rammi ng t he LV <3: 0> bi ts
(LVDCON<3:0>).
Once the LV bits have been programmed for the spec-
ified trip volt age, the low-v olt age dete ct circ uitry is the n
enabled by setting the LVDEN (LVDCON<4>) bit.
If the bandgap reference voltage is previously unused
by either the brown-out circuitry or the voltage refer-
ence circuitry, then the bandgap circuit requires a time
to st art-up and becom e stable bef ore a low voltage con-
dition can be reliably detected. The low-voltage inter-
rupt flag is prevented from being set until the bandgap
has reached a stable refe rence voltage.
When the bandgap is stable the BGST (LVDCON<5>)
bit is s et ind icating t hat the lo w-volt age i nterrupt fla g bit
is released to be set if VDD is equal to or less than the
LVD trip point.
10.3.1 EXTERNAL ANALOG VOLTAGE INPUT
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when
LV<3:0> = 1111. When these bits are set the compar-
ator input is multiplexed from an external input pin
(RA1/AN1/LVDIN).
Note: The LVDIF bit can not be cleared until the
supply voltage rises above the LVD trip
point. If interrupts are enabled, clear the
LVDIE bit once the first LVD interrupt
occurs to prevent reentering the interrupt
service routine immediately after exiting
the ISR.
1999-2013 Microchip Technology Inc. DS41120C-page 105
PIC16C717/770/771
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has six
inputs for the PIC16C717/770/771.
The PIC16C717 analog-to-digital converter (A/D)
allows conversion of an analog input signal to a corre-
sponding 10-bit digital value, while the A/D converter
in the PIC16C770/771 allows conversion to a corre-
sponding 12-bit digital value. The A/D module has up
to 6 analog inputs, which are multiplexed into one
sample and hold. The output of the sample and hold is
the input into the converter, which generates the result
via successive approximation. The analog reference
voltages are software selectable to either the device’s
analog positive and negative supply voltages (AVDD/
AVSS), the voltage level on the VREF+ and VREF- pins,
or internal voltage references if ena bled (VRH, VRL).
The A/D converter can be triggered by setting the GO/
DONE bit, or by the special event Compare mode of
the ECCP module. When conversion is complete, the
GO/DONE bit returns to ’0’, the ADIF bit in the PIR1
register is set, and an A/D interrupt will occur, if
enabled.
The A/D converter has a unique feature of being able
to opera te while th e device i s in SLEEP mode. To op er-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The A/D module has four registers. These registers
are: • A/D Result Register Low ADRESL
• A/D Result Register High ADRESH
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conve r si on is aborted .
11.1 Control Registers
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins, the voltage reference configura-
tion and the result format. The ANSEL register, shown
in Register 3-1, selects between the Analog or Digital
Port Pin modes. The port pins can be configured as
analog inputs or as digital I/O.
The combination of the ADRESH and ADRESL regis-
ters contain the result of the A/D conversion. The reg-
ister pair is referred to as the ADRES register. When
the A/D conversion is complete, the result is loaded
into ADRES, the GO/DONE bit (ADCON0<2>) is
cleared, and the A/D interrupt flag ADIF is set. The
block diagram of the A/D module is shown in
Figure 11-3.
PIC16C717/770/771
DS41120C-page 106 1999-2013 Microchip Technology Inc.
REGISTER 11-1: A/D CONTROL REGISTER 0 (ADCON0: 1Fh).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON
bit 7 bit 0
bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits
If internal VRL and/or VRH are not used for A/D reference (VCFG<2:0> = 000, 001, 011
or 101):
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from a dedicated RC oscillator)
If internal VRL and/or VRH are used for A/D reference (VCFG<2:0> = 010, 100, 110 or 111):
00 = FOSC/16
01 = FOSC/64
10 = FOSC/256
11 = FRC/8
bit 5-3, 1 CHS:<3:0>: Analog Channel Select bits
0000 = channel 00 (AN0)
0001 = channel 01 (AN1)
0010 = channel 02 (AN2)
0011 = channel 03 (AN3)
0100 = channel 04 (AN4)
0101 = channel 05 (AN5)
0110 = reserved, do not select
0111 = reserved, do not select
1000 = reserved, do not select
1001 = reserved, do not select
1010 = reserved, do not select
1011 = reserved, do not select
1100 = reserved, do not select
1101 = reserved, do not select
1110 = reserved, do not select
1111 = reserved, do not select
bit 2 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter is shutoff and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 107
PIC16C717/770/771
REGISTER 11-2: A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
The value that is in the ADRESH and ADRESL regis-
ters are not modified for a Power-on Reset. The
ADRESH and ADRESL registers will contain unknown
data after a Power-on Reset.
The A/D conversion results can be left justified (ADFM
bit cleared), or right justified (ADFM bit set).
Figure 11-1 through Figure 11-2 show the A/D result
data format of the PIC16C717/770/771.
FIGURE 11-1: PIC16C770/771 12-BIT A/D RESULT FORMATS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG2 VCFG1 VCFG0 Reserved Reserved Reserved Reserved
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6-4 VCFG<2:0>: Voltage Reference Configuration bits
bit 3-0 Reserved: Do not use.
Note 1: This parameter is VDD for the PIC16C717.
2: This parameter is VSS for the PIC16C717.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
A/D VREF+A/D VREF-
000 AVDD(1) AVSS(2)
001 External VREF+ External VREF-
010 Internal VRH Internal VRL
011 External VREF+AVSS(2)
100 Internal VRH AVSS(2)
101 AVDD(1) External VREF-
110 AVDD(1) Internal VRL
111 Internal VRL AVSS
ADRESH (1Eh) ADRESL (9Eh)
Left Justified
(ADFM = 0) MSB LSB
bit7 bit7
12-bit A/D Result Unused
Right Justified
(ADFM = 1) MSB LSB
bit7 bit7
Unused 12-bit A/D Result
PIC16C717/770/771
DS41120C-page 108 1999-2013 Microchip Technology Inc.
FIGURE 11-2: PIC16C717 10-BIT A/D RESULT FORMAT
After the A/D module has been configured as desired,
the sele cted channe l m ust be acquire d b efore the con-
version is started. The analog input channels must
have their corresponding TRIS and ANSEL bits
select ed as an input. To determine acquisition time, see
Section 11.6. After this acquisition time has elapsed,
the A/D co nv ers ion ca n b e s tarted. Th e following s teps
should be followed for doing an A/D conversion:
11.2 Configuring the A/D Module
11.2.1 CONFIGURING ANALOG PORT
PINS
The ANSEL and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bit
set (input ). If the TRIS bit is cleared (out put) , the digit al
output level (VOH or VOL) will be co nv erted. The prop er
ANSEL bits must be set (analog input) to disable the
digital input buffer.
The A/D operation is independent of the state of the
TRIS bits and the ANSEL bits.
11.2.2 CONFIGURING THE REFERENCE
VOLTAGES
The VCFG bits in the ADCON1 register configure the
A/D module reference inputs. The reference high input
can come from an internal reference (VRH) or (VRL),
an external reference (VREF+), or AVDD. The low refer-
ence inp ut c an co me from an inte rnal refe ren ce (VRL ),
an external reference (VREF-), or AVSS. If an external
reference is chosen for the reference hig h or referenc e
low inputs, the port pin that multiplexes the incoming
external references is configured as an analog input,
regardles s of the val ues co nt ained in the A/D port con-
figuration bits (PCFG<3:0>).
(ADFM = 0) MSB LSB
bit7 bit7
10-bit A/D Result Unused
(ADFM = 1) MSB LSB
bit7 bit7
Unused 10-bit A/D Result Unused
Note 1: When reading the PORT A register , all pins
configured as analog input channels will
read as ’0’.
2: When reading the PORTB register, all
pins configured as analog pins on
PORTB will be read as ’1’.
3: Analog l evels on any p in that is defined a s
a digital input, including the ANx pins, may
cause the inp ut b uffer to consume c urre nt
that is out of the devices specification.
1999-2013 Microchip Technology Inc. DS41120C-page 109
PIC16C717/770/771
After the A/D module has been configured as desired
and the analog input channels have their correspond-
ing TRIS bits selected for port inputs, the selected
channel must be acquired before conversion is
started. The A/D conversion cycle can be initiated by
setting the GO/DONE bit. The A/D conversion begins
and lasts for 13TAD. The f oll owin g ste ps shoul d be f ol-
lowed for performing an A/D conversion:
1. Configure port pins:
• Configure Analog Input mode (ANSEL)
• Configure pin as input (TRISA or TRISB)
2. Configure the A/ D module
• Configure A/D Result Format / voltage refer-
ence (ADCON1)
• Select A/D input channel (ADCON0)
• Selec t A/D conve rsi on clock (ADCON0)
• Turn on A/D module (ADCON0)
3. Confi g ure A /D interrupt (if requir ed)
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
4. Wait the required acquisition time.
5. START conversion
• Set GO/DONE bit (ADCON0)
6. Wa it 13TAD until A/D co nv ers ion is com ple te, b y
either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
7. Read A/D Result registers (ADRESH and
ADRESL), clear ADIF if required.
8. For next co nv ers ion , g o to s tep 1, step 2 or ste p
3 as required.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRESH and
ADRESL registers will be updated with the partially
completed A/D conversion value. That is, the
ADRESH and ADRESL registers will contain the value
of the current incomplete conversion.
FIGURE 11-3: A/D BLOCK DIAGRAM
Note: Do not set the ADON bit and the GO/
DONE bit in the sam e instru ction. Do ing so
will cause the GO/DONE bit to be automat-
ically cleared.
(INPUT VOLTAGE)
VAIN
VREF+
(REFERENCE
VOLTAGE +)
AVDD
VCFG<2:0>
CHS<3:0>
RB1/AN5/SS
RB0/AN4/INT
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
A/D
CONVERTER
VREF-
(REFERENCE
VOLTAGE -) AVSS
VCFG<2:0>
VRH
VRL
VRL
PIC16C717/770/771
DS41120C-page 110 1999-2013 Microchip Technology Inc.
11.3 Selecting the A/D Conversion
Clock
The A/D conversion cycle requires 13T AD: 1 TAD for set-
tling tim e, and 12 TAD for convers ion. The so urce of the
A/D conversion clock is sof tware selected. If neither the
internal VRH nor VRL are used for the A/D converter,
the four possible options for TAD are:
•2 T
OSC
•8 TOSC
•32 TOSC
• A/D RC oscil la tor
If the VR H or VR L are used f or the A /D co nverter ref er-
ence, then the TAD requirement is automatically
increased by a factor of 8.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s. Table 11-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock sou rce selected.
The ADIF bit is set on the rising edge of the 14th TAD.
The GO/DONE bit is cleared on the falling edge of the
14th TAD.
TABLE 11-1: TAD vs. DEVICE OPERATING FREQUENCIES
A/D Reference
Source A/D Clock Source (TAD) Device Frequency
External VREF or
Analog Supply
Operation ADCS<1:0> 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 00 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s
8 TOSC 01 400 ns(2) 1.6 s2.0 s6.4 s
32 TOSC 10 1.6 s6.4 s(3) 8.0 s(3) 25.6 s(3)
A/D RC 11 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4)
Internal VRH or
VRL 16 TOSC 00 800 ns(2) 3.2 s(2) 4 s(2) 12.8 s
64 TOSC 01 3.2 s(2) 12.8 s 16 s 51.2 s(3)
256 TOSC 10 12.8 s51.2 s(3) 64 s(3) 204.8 s(3)
A/D RC 11 16 - 48 s(4,5) 16 - 48 s(4,5) 16 - 48 s(4,5) 16 - 48 s(4,5)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be
performed during SLEEP.
5: A/D RC clock source has a typical TAD time of 32 s f or VDD > 3.0V.
1999-2013 Microchip Technology Inc. DS41120C-page 111
PIC16C717/770/771
11.4 A/D Conversions
Example 11-1 shows an example tha t perfor ms an A/D
conversion. The port pins are configured as analog
input s. The ana log referenc e V REF+ is the device AVDD
and the analog reference VREF- is the device AVSS.
The A/D interrupt is enabled and the A/D conversion
clock i s TRC. The conversion is performed on the AN0
channel.
EXAMPLE 11-1: PERFORMING AN A/D CONVERSI ON
BSF STATUS, RP0 ;Select Bank 1
CLRF ADCON1 ;Configure A/D Voltage Reference
MOVLW 0x01
MOVWF ANSEL ;disable AN0 digital input buffer
MOVWF TRISA ;RA0 is input mode
BSF PIE1, ADIE ;Enable A/D interrupt
BCF STATUS, RP0 ;Select Bank 0
MOVLW 0xC1 ;RC clock, A/D is on,
;Ch 0 is selected
MOVWF ADCON0 ;
BCF PIR1, ADIF ;Clear A/D Int Flag
BSF INTCON, PEIE ;Enable Peripheral
BSF INTCON, GIE ;Enable All Interrupts
;
; Ensure that the required sampling time for the
; selected input channel has lapsed. Then the
; conversion may be started.
BSF ADCON0, GO ;Start A/D Conversion
: ;The ADIF bit will be
;set and the GO/DONE bit
: ;cleared upon completion-
;of the A/D conversion.
; Wait for A/D completion and read ADRESH:ADRESL for result.
PIC16C717/770/771
DS41120C-page 112 1999-2013 Microchip Technology Inc.
11.5 A/D Converter Module Operation
Figure 11-4 shows the flowchart of the A/D converter
module.
FIGURE 11-4: FLOW CHART OF A/D OPERATION
Sample
ADON = 0
ADON = 0?
GO = 0?
A/D Clock
GO = 0
ADIF = 0
Abort Conversion
SLEEP
Power-down A/D
Wake-up
Yes
No
Yes
No
No
Yes
Finish Conversi on
GO = 0
ADIF = 1
SLEEP
No
Yes
Finish Conversi on
GO = 0
ADIF = 1
Stay in SLEEP
Selected Channel
= RC?
Instruction?
SLEEP
No
Yes
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
From SLEEP?
Power-down A/D
Yes
No
Finish Conversion
GO = 0
ADIF = 1
1999-2013 Microchip Technology Inc. DS41120C-page 113
PIC16C717/770/771
11.6 A/D Sample Requirements
11.6.1 RECOMMENDED SOURCE
IMPEDANCE
The maximum recommended impedance for ana-
log sources is 2.5 k. This value is calculated based
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be varied by more than 1/4 LSb or
250 V due to leakage. This places a requirement on
the input impedance of 250 V/100 nA = 2.5 k.
11.6.2 SAMPLING TIME CALCULATION
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-5. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance va rie s over the dev ice vol tag e
(VDD), see Figure 11-5. The maximum recom-
mended impedance for analog sources is 2.5 k.
After the analog input channel is selected (changed)
this sampling must be done before the conversion can
be started.
To calculate the minimum sampling time, Equation 11-
2 may be used. This equation assumes that 1/4 LSb
error is used (16384 steps for the A/D). The 1/4 LSb
error is the maxim um error allowed for the A/D to me et
it s spe ci fie d re so luti on.
The CHOLD is assumed to be 25 pF for the 12-bit
A/D.
EXAMPLE 11-2: A/D SAMPLING TIME
EQUATION
Figure 11-3 shows th e calc ulatio n of the mi nimum time
required to c harge CHOLD. This calc ulatio n is based on
the following system assumptions:
CHOLD = 25 pF
RS = 2.5 k
1/4 LSb error
VDD = 5V RSS = 10 k(worst ca se)
Temp (s yste m Max.) = 50C
Note 1:The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2:The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3:The maximum recommended impedance
for analog sources is 2.5 k. This is
required to meet the pin leakage specifi-
cation.
VHOLD VREF VREF
16384
----------------
–=
VREF VREF
16384
----------------
–VREF1e
TC–
CHOLD RIC RSS RS++
-------------------------------------------------------------------
–
=
VREF 11
16384
----------------
–
VREF1e
TC–
CHOLD RIC RSS RS++
-------------------------------------------------------------------
–
=
TCCHOLD 1kRSS RS++
1
16384
----------------
ln–=
Solving for TC:
PIC16C717/770/771
DS41120C-page 114 1999-2013 Microchip Technology Inc.
EXAMPLE 11 -3: CALCULATING THE
MINIMUM
REQUIRED SAMPLE TIME
FIGURE 11-5: ANALOG INPUT MODEL
TACQ = Amplifier Settling Time
+ Holding Capacitor Charging Time
+Temperature offset †
TACQ =5 s
+ TC
+ [(Temp - 25C)(0.05s/C)] †
TC = Holding Capacitor Charging Time
TC =(CHOLD) (RIC + RSS + RS) In (1/16384)
TC = -25 pF (1 k +10 k + 2.5 k) In (1/16384)
TC = -25 pF (13.5 k) In (1/16384)
TC = -0.338 (-9.704)s
TC =3.3 s
TACQ =5s
+ 3.3 s
+ [(50C - 25C)(0.05s / C)]
TACQ = 8.3 s + 1.25s
TACQ = 9.55 s
† The temperature coefficient is only required for
temperatures > 25C.
CPIN
VA
RSPort Pin
5 pF
VDD
Vt = 0.6V
VT = 0.6V ILEAKAGE
RIC ~ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
6V
Sampling Switch (RSS)
5V
4V
3V
2V
567891011
( k )
VDD
± 100 nA
Legend CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= lea kage cu rrent at the pin due to
= interconnec t resistance
= sampling switch
= sample/h old capacitance
various junctions
~
1999-2013 Microchip Technology Inc. DS41120C-page 115
PIC16C717/770/771
11.7 Use of th e ECCP Trigger
An A/D conversion can be started by the “special
event trigger” of the CCP module. This requires that
the CCP1M<3:0> bits be programmed as 1011b and
that the A/D module is enabled (ADON is set). When
the trigger occurs, the GO/DONE bit will be set on Q2
to start the A/D conversion and the Timer1 counter will
be reset to zero. Timer1 is RESET to automatically
repeat the A/D conversion cycle, with minimal soft-
ware overhead (moving the ADRESH and ADRESL to
the desired location). The appropriate analog input
channel must be selected before the “special event
trigger” sets the GO/DONE bit (starts a conversion
cycle).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still RESET the Timer1 counter.
11.8 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. The value that is in the
ADRESH and ADRESL registers are not modified.
The ADRESH and ADRESL registers will contain
unknown data after a Power-on Reset.
11.9 Faster Conversion - Lower
Resolution Trade-off
Not all applic ation s requi re a resu lt with 12 bit s of reso-
lution, but may instead require a faster conversion
time. The A/D module allows users to make the trade-
off of conversion speed to resolution. Regardless of
the resolution required, the acquisition time is the
same. To speed up the conversion, the A/D module
may be halted by clearing the GO/DONE bit after the
desired number of bits in the result have been con-
verted. Once the GO/DONE bit has been cleared, all
of the remaining A/D result bits are ‘0’. The equation
to determine the time before the GO/DONE bit can be
switched is as follows:
Conversion time = (N+1)TAD
Where: N = number of bits of resolution required,
and 1TAD is the amplifier settling time.
Since TAD is based from the device oscillator, the user
must us e so me meth od (a tim er, software loop, etc .) to
determine when the A/D GO/DONE bit may be
cleared. Ta bl e 1 1 - 4 shows a comparison of time
required for a conversion with 4 bits of resolution, ver-
sus the normal 12-bit resolution conversion. The
example is for devices operating at 20 MHz. The A/D
clock is programmed for 32 TOSC.
EXAMPLE 11-4: 4-BIT vs. 12-BIT
CONVERSION TIME
Example
4-Bit Example:
Conversion Time = (N + 1) TAD
= (4 + 1) TAD
= (5)(1.6 S)
= 8 S
12-Bit Example:
Conversion Time = (N + 1) TAD
= (12 + 1) TAD
= (13)(1.6 S)
= 20.8 S
PIC16C717/770/771
DS41120C-page 116 1999-2013 Microchip Technology Inc.
11.10 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clo ck source be c onfigured for RC
(ADCS<1:0> = 11b). With the RC clock source
selected, when the GO/DONE bit is set the A/D mo dule
waits one instruction cycle before starting the conver-
sion cycle. This allows the SLEEP instructio n to be ex e-
cuted, which eliminates all digital switching noise
during the sample and conversion. When the conver-
sion cycle is completed the GO/DONE bit is cleared,
and the result loaded into the ADRESH and ADRESL
registers. If the A/D inte rrupt is enabled , the dev ic e wil l
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
When the A/D clock sour ce is anoth er clock optio n (not
RC), a SLEEP instruction causes the present conver-
sion to be aborted and the A/D module is turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D mo du le in it s low est
current consumption state.
11.11 Connection Considerations
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input mus t be bet ween VDD and V SS. If the input
volt age exce eds this range by greater th an 0.3V (eith er
direction), one of the diodes becomes forward biased
and it may da mage the device if the inp ut curren t spec-
ification is exceeded.
An external RC f ilt er i s so metimes added for ant i-al ias -
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept un der the 2.5 k recommended sp ecifi cation . I t is
recommended that any external components con-
nected to an analog input pin (capacitor, zener diode,
etc.) have very little leakage current.
TABLE 11-2: SUMMARY OF A/D REGISTERS
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be configured to
RC (ADCS<1:0> = 11).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 0000 ----
05h PORTA PORTA Data Latch when written: PORTA pins when read 000x 0000 000u 0000
06h PORTB PORT B Data Latch when written: PORTB pins when read xxxx xx11 uuuu uu11
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
17h CCP1CON — — — — 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Sha ded cells are not used for A/D conversion.
1999-2013 Microchip Technology Inc. DS41120C-page 117
PIC16C717/770/771
12.0 SPECIAL FEATURES OF THE
CPU
These d evices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes an d offer code protecti on. These are:
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Low-vo lt age detection
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming (ICSP)
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers th at of fe r necessa ry delay s on po wer-up. O ne is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
type RESETS only (POR, BOR), designed to keep the
part in RESET while the power supply stabilizes. With
these two timers on-chip, most applications need no
external RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The INTRC and ER oscillator options
save system cost while the LP crystal option saves
power . A set of c onfigurati on bits are used to s elect var-
ious options.
Additional information on special features is available
in the PIC Mid- Rang e MC U Fam il y Referenc e Manual,
(DS33023).
12.1 Configuration Bits
The con figurat ion bit s ca n be program med (r ead as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space.
Some of the core features provided may not be neces-
sary to ea ch appl ic ati on that a devic e ma y be us ed fo r.
The configuration word bits allow these features to be
configured/enabled/disabled as necessary. These fea-
tures include code protection, Brown-out Reset and its
trip point, the Power-up Timer, the watchdog timer and
the devices Oscillator mode. As can be seen in
Register 12-1, some additional configuration word bits
have been provided for Brown-out Reset trip point
selection.
PIC16C717/770/771
DS41120C-page 118 1999-2013 Microchip Technology Inc.
REGISTER 12-1: CONFIGURATION WORD FOR 16C717/770/771 DEVICE
CP CP BORV1 BORV0 CP CP —BODENMCLREPWRTEWDTE FOSC2 FOSC1 FOSC0
bit13 bit0
bit 13-12,
9-8 CP: Program Memory Code Protection
1 = Code protection off
0 = All program memory is protected(2)
bit 11-10: BORV<1:0>: Brown-out Reset Voltage bits
00 = VBOR set to 4.5 V
01 = VBOR set to 4.2 V
10 = VBOR set to 2.7 V
11 = VBOR set to 2.5 V
bit 7: Unimplemented: Read as '1'
bit 6: BODEN: Brown-out Detect Reset Enable bit(1)
1 = Brown-out Detect Reset enabled
0 = Brown-out Detect Reset disabled
bit 5: MCLRE: RA5/ M C LR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4: PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3: WDTE: Watchdog Timer En able bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator: Crystal/Resonator on RA6/OSC2/CLK OUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
010 = HS oscillator: Crystal/Resonator on RA6/OSC2/CLK OUT and RA7/OSC1/CLKI N
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLK OUT pin, Resistor on RA7/OSC1/CLKIN
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOU T pin, Resistor on RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PW RT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP bits must be given the same value to enable code protection.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 119
PIC16C717/770/771
12.2 Oscillator Configurations
12.2.1 OSCILLATOR TYPES
The PIC16C717/770/771 can be operated in eight dif-
ferent Oscillator modes. The user can program three
configuration bits (FOSC<2:0>) to select one of these
eight modes:
• LP Low Power Crystal
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• ER External Resistor (with and without
CLKOUT)
• INTRC Internal 4 MHz (with and without
CLKOUT)
• EC External Cloc k
12.2.2 LP, XT AND HS MODES
In LP, XT or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16C717/770/771 oscillator design requires the use
of a parallel cut cr ystal. Use of a se ries cut crystal may
give a fre quency o ut of the cry stal m anufacture rs spec-
ifications.
FIGURE 12-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
TABLE 12-1: CERAMIC RESONATORS
T ABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
12.2.3 EC MODE
In applications where the clock source is external, the
PIC16C717/770/771 should be programmed to select
the EC (External Clock) mode. In this mode, the RA6/
OSC2/CLKOUT pin is available as an I/O pin. See
Figure 12-2 for illustration.
FIGURE 12-2: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Note1: See Table 12-1 and Ta b l e 1 2 - 2 for recom-
mended values of C1 and C2.
2: A series re si stor (RS) may b e re qui red for
AT strip cut crystals.
3: RF varies with the Crystal mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
SLEEP
To
logic
PIC16C717/770/771
RS(2)
internal
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
All resonators used did not have built-in capacitors.
Osc Type Crystal
Freq Cap. Range
C1 Cap . Ran ge
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only. See
notes at bottom of page.
Note1: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
2: Higher capacitance increases the stabili ty of
oscillator but also increases the start-up
time.
OSC1
RA6
I/O
Clock from
ext. system PIC16C717/770/771
PIC16C717/770/771
DS41120C-page 120 1999-2013 Microchip Technology Inc.
12.2.4 ER MO DE
For timing insensitive applications, the ER (External
Resistor) Clock mode offers additional cost savings.
Only one external component, a resistor connected to
the OSC1 pin and VSS, is needed to set the operating
frequency of the internal oscillator. The resistor draws
a DC bias current which controls the oscillation fre-
quency. In addition to the resistance value, the oscilla-
tor frequency will vary from unit to unit, and as a
funct ion of supply voltage an d temp erature . Since the
controlling par ameter is a DC current and not a capac-
itanc e, th e par tic ular pa ckag e ty pe a nd l ead f ram e wi ll
not have a signif ica nt e ffect on t he resulta nt frequency.
Figure 12-3 shows how the controlling resistor is con-
nected to the PIC16C717/770/771. For REXT values
below 38 k, the oscillator operation may become
unst able, or sto p completely. For very high REXT values
(e.g. 1M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 38 k and 1 M.
FIGURE 12-3: EXTERNAL RESIS TOR
The Electri ca l Specifi cat ion sect io n sh ows the relation-
ship between the REXT res istan ce va lue an d th e ope r-
ating frequency as well as frequency variations due to
operating temperature for given REXT and VDD values.
The ER Oscillator mode has two options that control
the OSC 2 pin. Th e first allow s it to b e used as a general
purpose I/O port . The othe r co nfi gure s th e pi n as CLK-
OUT. The ER oscillator does not run during RESET.
12.2.5 INTRC MODE
The internal RC oscillato r provide s a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25C, see “Electri-
cal Specifications” section for information on variation
over voltage and temperature. The INTRC oscillator
does not run during RESET.
12.2.6 CLKOUT
In the INTRC and ER modes, the PIC16C717/770/771
can be co nf i gur e d to pr o vi de a cl oc k ou t sig nal by pr o -
gramming the configuration word. The oscillator fre-
quenc y, div id e d by 4, ca n be us ed fo r te st pur p os es or
to synchronize other logic.
In the INTRC and ER modes, if the CLKOUT output is
enabled, CLKOUT is held low during RESET.
12.2.7 DUAL SPEED OPERATION FOR ER
AND INTRC MODES
A soft ware programmable dual speed oscillator is avail-
able in either ER or INTRC Oscillator modes. This fea-
ture allows the applications to dynamically toggle the
oscill ator spee d betwe en normal an d slow frequencies .
The nominal slow frequency is 37 kHz. In ER mode, the
slow speed operation is fixed and does not vary with
resistor size. Applications that require low current
power savings, but cannot tolerate putting the part into
SLEEP, may use this mo de.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See the PCON Register,
Register 2-8, for details.
When changing the INTRC or ER internal oscillator
speed, there is a period of time when the processor is
inactive. When the speed changes from fast to slow,
the pr o ce ss or i na ct i ve pe ri od is in t he r a ng e o f 10 0 S
to 300 S. For speed cha nge from slo w to fast, th e pro-
cessor is in active for 1.25 S to 3.25 S.
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
PIC16C717/770/771
REXT
1999-2013 Microchip Technology Inc. DS41120C-page 121
PIC16C717/770/771
12.3 RESET
The PIC16C717/770/771 devices have several differ-
ent RESETS. These RESETS are grouped into two
classifications; power-up and non-power-up. The
power-up type RESETS are the Power-on and Brown-
out Re sets w hich assume t he device VDD wa s below its
normal operating range for the device’s configuration.
The non po wer-up type RESETS ass ume normal oper-
ating l imits were m aintai ned befo re/during and af ter the
RESET.
• Pow er- on Reset (POR )
• Programmable Brown-out Reset (PBOR)
•MCLR
Reset during normal operation
•MCLR
Reset during SLEEP
• WDT Reset (during normal operation)
Some registers are not affected in any RESET condi-
tion. The ir st at us is un know n on a Power-up R ese t and
unchanged in any other RESET. Most other registers
are placed into an initialized state upon RESET, how-
ever they are not affected by a WDT Reset during
SLEEP, because this is considered a WDT Wake-up,
which is viewed as the resumption of normal operation.
Several status bits have been provided to indicate
which RESET occurred (see Ta bl e 1 2 - 4 ). See
Ta bl e 12 - 6 for a full description of RESET states of all
registers.
A simplifi ed bloc k diagra m of the On-Chip Res et circu it
is shown i n Figure 12-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-4: SIMPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
RESET
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
Dedicated
Oscillator
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Enable OST
Enable PWRT
SLEEP
Brown-out
Programmable BODEN
Time-out
PIC16C717/770/771
DS41120C-page 122 1999-2013 Microchip Technology Inc.
12.4 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected (in the range of 1.5V - 2.1V).
Enable the intern al MCLR feature to eliminate external
RC components usually needed to create a Power-on
Reset. A ma ximum rise tim e for VDD is specified. See
Electric al S pecifications for detail s. For a long ri se time,
enable external MCLR function and use circuit as
shown in Figure 12-5.
Two delay timers, (PWRT on OST), have been pro-
vided which hold the device in RESET after a POR
(depende nt upon d evice c onfigu ration) so that all op er-
ational parameters have been met prior to releasing the
device to resume/begin normal operation.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, fre quency, temperature,...) m ust be m et to ensu re
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start -up conditions, or if necessary an external POR cir-
cuit may be i mplemen ted to delay end o f RESET fo r as
long as needed.
FIGURE 12-5: EX T ERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD RAMP)
12.5 Power-up Timer (PWRT)
The Power-up Timer provides a fixed TPWRT time-out
on power-u p type RESETS only. For a POR, the PW RT
is invoked when the POR pulse is generated. For a
BOR, the PWRT is invoked when the device exits the
RESET condition (VDD rises above BOR trip point).
The Power-up Timer operates on an internal RC oscil-
lator. The chip is kept in RESET as long as the PWRT
is active. The PWRT’s time delay is designed to allow
VDD to rise to an acceptable level. A configuration bit is
provi ded to enable/dis able the PWRT fo r the POR only.
For a BOR th e PWR T i s always a vailabl e regard less of
the configuration bit setting.
The power-up time delay will vary from chip-to -chip due
to VDD, temperature and process variation. See DC
param ete rs for deta ils .
12.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWR T delay is over. This ensu res that t he cryst al os cil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on a powe r-up type RESET o r a wake-
up from SLEEP.
12.7 Programmable Brown-Out Reset
(PBOR)
The Program mable Brown-ou t Reset module is used to
generate a RESET when the su pply volt age falls bel ow
a specif ied t rip v oltage. The trip voltage is confi gu rabl e
to any one of fo ur voltages provided by the BOR V<1:0>
configu r ati on word bit s .
Configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below the specified trip point for
longer th an TBOR, (param eter #35), the b row n -out sit u-
ation will RESET the chip. A RESET may not occur if
VDD falls below the trip point for less than TBOR. The
chip will remain in Brown-out Reset until VDD rises
above VBOR. The Power-up Timer will be invoked at
that poin t and will ke ep the chip in RESET an additiona l
TPWRT. If VDD drops below VBOR while the Power-up
Timer is ru nni ng, the chi p wi ll go back in to a Bro w n-o ut
Reset and the Power-up Timer will be re-initialized.
Once VDD rises above VBOR, the Power-up Timer will
again begin a TPWRT time delay. Even though the
PWRT is always enabled when brown-out is enabled,
the PWRT configuration word bit should be cleared
(enabled) when brown-out is enabled.
Note1: External Power-on Reset circuit is
required only if VDD power-up slope is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not violate
the device’s electrical sp ecification.
3: R1 = 100 to 1 k will limit any current
flowi ng in to M CL R from external capacitor
C in the ev ent of MCLR/VPP pin break-
down due to Electrost a tic Disch arge
(ESD) or Electrical Overstress (EOS).
4: External MCLR must be enabled
(MCLRE = 1).
C
R1
R
D
VDD
MCLR
PIC16C717/770/771
VDD
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12.8 Time-out Sequence
On power-up, the time-out sequence is as follows:
First PWRT time-out is invoked by the POR pulse.
When the PWRT delay expires, the Oscillator Start-up
Timer is activated. The total time-out will vary based on
oscillator configuration and the status of the PWRT.
For example, in RC mode with the PWRT disabled,
there will be no time-out at all. Figure 12-6, Figure 12-
7, Figure 12-8 and Figure 12-9 depict time-out
sequences on power-up.
Since the time-outs oc cur from the PO R pulse, if MCLR
is kep t low long e nough , the ti me-out s w ill e xpire. Then
bringing MCLR high will begin execution immediately
(Figure 12-8). This is useful for testing purposes or to
synchronize more than one PIC® microcontroller oper-
ating in par allel.
Ta bl e 12 - 5 shows the RESET condit ions for so me spe-
cial function registers, while Table 12-6 shows the
RESET conditio ns for all the regist ers .
12.9 Power Control/STATUS Register
(PCON)
The Power Control/STATUS Register, PCON, has two
status bits that provide indication of which power-up
type RESET occurred.
Bit0 is Brown-out Reset Status bit, BO R. The BOR bit
is unkn ow n upo n a PO R. BOR must be set by the user
and chec ked on subseque nt RESETS to see if bit BOR
cleared, indicating a BOR occurred.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Co nfigu ration Power-up Brown-out Wake-up from
SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP TPWRT + 1024TOSC 1024TOSC TPWRT + 1024TOSC 1024TOSC
EC, ER, INTRC TPWRT —TPWRT —
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Reset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operat ion
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- 1-0x
MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- 1-uu
WDT Reset 000h 0000 1uuu ---- 1-uu
WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu
Brown-out Reset 000h 0001 1uuu ---- 1-u0
Interrupt wake-up from SLEEP, GIE = 0 PC + 1 uuu1 0uuu ---- u-uu
Interrupt wake-up from SLEEP, GIE = 1 0004h uuu1 0uuu ---- u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
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TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Power-on Reset or
Brown- out Reset MCLR Reset or
WDT Reset Wake-up via WDT or
Interrupt
Wxxxx xxxx uuuu uuuu uuuu uuuu
INDF 0000 0000 uuuu uuuu uuuu uuuu
TMR0 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000h 0000h PC + 1(1)
STATUS 0001 1xxx 000q quuu(2) uuuq quuu(2)
FSR xxxx xxxx uuuu uuuu uuuu uuuu
PORTA xxxx 0000 uuuu 0000 uuuu uuuu
PORTB xxxx xx11 uuuu uu11 uuuu uuuu
PCLATH ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000x 0000 000u uuuu uuqq
PIR1 -0-- 0000 -0-- 0000 -0-- uuuu
PIR2 0--- 0--- 0--- 0--- q--- q---
TMR1L xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H xxxx xxxx uuuu uuuu uuuu uuuu
T1CON --00 0000 --uu uuuu --uu uuuu
TMR2 0000 0000 0000 0000 uuuu uuuu
T2CON -000 0000 -000 0000 -uuu uuuu
SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 0000 0000 0000 0000 uuuu uuuu
CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 0000 0000 0000 0000 uuuu uuuu
ADRESH xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 0000 0000 0000 0000 uuuu uuuu
OPTION_REG 1111 1111 1111 1111 uuuu uuuu
TRISA 1111 1111 1111 1111 uuuu uuuu
TRISB 1111 1111 1111 1111 uuuu uuuu
PIE1 -0-- 0000 -0-- 0000 -u-- uuuu
PIE2 0--- 0--- 0--- 0--- u--- u---
PCON ---- 1-qq ---- 1-uu ---- u-uu
PR2 1111 1111 1111 1111 1111 1111
SSPADD 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 0000 0000 0000 0000 uuuu uuuu
WPUB 1111 1111 1111 1111 uuuu uuuu
IOCB 1111 0000 1111 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2: See Ta bl e 1 2 - 5 for RESET value for specific condition.
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FIGURE 12-6: TIME-OUT SEQU ENCE ON POWER-UP (MCLR TIED TO VDD)
P1DEL 0000 0000 0000 0000 uuuu uuuu
REFCON 0000 ---- 0000 ---- uuuu ----
LVDCON --00 0101 --00 0101 --uu uuuu
ANSEL --11 1111 --11 1111 --uu uuuu
ADRESL xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 0000 0000 0000 0000 uuuu uuuu
PMDATL xxxx xxxx uuuu uuuu uuuu uuuu
PMADRL xxxx xxxx uuuu uuuu uuuu uuuu
PMDATH --xx xxxx --uu uuuu --uu uuuu
PMADRH ---- xxxx ---- uuuu ---- uuuu
PMCON1 1--- ---0 1--- ---0 1--- ---0
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Power-on Reset or
Brown- out Reset MCLR Reset or
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2: See Ta bl e 1 2 - 5 for RESET value for specific condition.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
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FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 12-9: SLO W VDD RISE TIME (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
0V 5V
TPWRT
TOST
Note 1: Time dependent on oscillator circuit
(1)
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12.10 Interrupts
The devices have up to 11 sources of interrupt. The
interrupt control register (INTCON) records individual
interrupt requests in flag bits. It also has individual and
global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all un-masked interrupts or disables (if
cleared) all int errupts. When bit GIE is enabled and an
inter rupt’s flag bit and mask bit are s et, the int errupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enable s inte rrup t s.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR 0 over flo w interru pt f lag s are co nt a ine d in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial fu nction regis ters PIR1 and PI R2. The co rrespond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interr upt enabl e bit is conta ined in sp ecial function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed onto the s t ac k a nd the PC is loade d
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cy c le ins tru cti ons . Individua l
interrupt flag bits are set regardless of the sta tus of their
corresponding mask bit or the GIE bit
FIGURE 12-10: INTERRUPT LOGIC
Note: Individual interrupt flag bits are set regard-
les s of the status of their corresponding
mask bit or the GIE bit.
ADIF
ADIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Inte rrup t to CPU
LVDIF
LVDIE
BCLIE
BCLIF
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12.10.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or fall ing , if th e IN TEDG bit i s cl ea r. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared i n softwa re in the in terrupt serv ice rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior t o going into SLEEP. The status o f global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 12.13 for details on SLEEP mode.
12.10.2 TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 2.2.2.3)
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:0> sets flag bit RBIF
(INTCON<0>). The PORTB pin(s) which can individu-
ally generate interrupt is selectable in the IOCB regis-
ter. The interrupt can be enabled/disabled by setting/
clearing enable bit RBIE (INTCON<4>).
(Section 2.2.2.3)
12.11 Context Saving During Interrupts
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 12-1 stores and restore s the STATUS, W and
PCLATH registe rs. The regis ter , W_TEMP, is defined in
Common R AM, the last 16 by tes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register in bank 0.
d) Executes the ISR code.
e) Restores the PCLATH register.
f) Restores the STATUS register
g) Rest o res W.
Note that W_TEMP, STATUS_TEMP and
PCLATH_TEMP are de fin ed i n the common RAM are a
(70h - 7Fh) to avoid register bank switchi ng during con-
text save and restore .
EXAMPLE 12-1: Saving STATUS, W, and PCLATH Registers in RAM
#define W_TEMP 0x70
#define STATUS_TEMP 0x71
#define PCLATH_TEMP 0x72
org 0x04 ; start at Interrupt Vector
MOVWF W_TEMP ; Save W register
MOVF STATUS,w
MOVWF STATUS_TEMP ; save STATUS
MOVF PCLATH,w
MOVWF PCLATH_TEMP ; save PCLATH
:
(Interrupt Service Routine)
:
MOVF PCLATH_TEMP,w
MOVWF PCLATH
MOVF STATUS_TEMP,w
MOVWF STATUS
SWAPF W_TEMP,f ;
SWAPF W_TEMP,w ; swapf loads W without affecting STATUS flags
RETFIE
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12.12 Watchdog Timer (WDT)
The W atchdog T imer is a free running on-chip RC oscil-
lator, which does not requ ire any exte rnal co mpone nt s.
This osc illator is indepe ndent from the process or clock.
If enabled, the WDT will run even if the main clock of
the device has been stopped, for example, by execu-
tion of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (W atchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by program-
ming the configuration bit WDTE to ’0’ (Section 12.1).
WDT time -out perio d values may be fou nd in Table 15-
4. Values for the WDT prescaler may be assigned using
the OPTION_REG register.
FIGURE 12-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: The SLEEP instruction clears the WDT and
the postscaler, if assigned to the WDT,
restarting the WDT period.
From TMR0 Clock Source
(Figure 5-2)
To TMR0 (Figure 5-2)
Postscaler
WDT Timer
WDT
Enable Bit(2)
0
1M
U
X
PSA
8 - to - 1 MU X PS<2:0>(1)
01
MUX PSA(1)
WDT
Time-out
Note 1: PSA and PS<2:0> are bits in the OPTION_REG register.
8
2: WDTE bit in the configuration word.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits(1) —BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note1: See Register 12-1 for the full description of the configuration word bits.
PIC16C717/770/771
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12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keep s runni ng, the PD bi t (STATUS<3>) is c lea red , th e
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external cir-
cuitr y is dr awing cu rrent from th e I/O pi n, powe r-down
the A/D, disable external clocks. Pull all I/O pins, that
are h i-impeda nce input s, high or lo w external ly to a void
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
12.13.1 WAKE - UP FR OM SLEE P
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT p in , RB port change, o r som e
Peripheral Interrupts.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execut ion and cause a " wak e-up". The T O and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
powe r-up, is cleared w hen SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The follo wing periph eral interrupt s can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. CCP Capture mode interrupt.
3. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
4. SSP (START/STOP) bit detect interrupt.
5. SSP transmit or receive in Slave mode
(SPI/I2C).
6. A/D conversion (when A/D clock source is RC).
7. Low Voltage detect.
Other per ipherals cannot g enerate interrup ts since d ur-
ing SLEEP, no on-chip clocks are present.
When the SLEEP instruction i s being e xecuted, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-u p thro ugh an int errup t ev ent, the correspondin g
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
ins tructi on after t he SLEEP instruction. If the GIE bit is
set (enabled) , th e device ex ecutes t he instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP afte r the SLEEP instruction.
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occu r:
•If the interrupt occurs before the execution of a
SLEEP instr uct ion, the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
pos tsc aler will not be cleared, the TO bit will not
be set and PD bits will not be cleare d.
•If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postsc aler will be cl eare d, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruct ion completes . To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
If a peripheral can wake the device from SLEEP, then
to ensure that the WDT is cleared, a CLRWDT instr uc-
tion should be executed before a SLEEP instruction.
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FIGURE 12-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
12.14 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
12.15 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identif ication nu mber s. These location s are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
12.16 In-Circuit Serial Programming
(ICSP™)
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and dat a, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS302 77).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency(2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(1)
PC+2
Note 1: TOST = 1024TOSC (drawing not to scale) This delay applies to LP, XT and HS modes only.
2: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
3: CLKOUT is not available in these osc modes, but shown here for timing reference.
Note: Microchip does not recommend code pro-
tecting wi ndo wed devices. Code prote cte d
devices are not reprogrammable.
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NOTES:
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13.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
For byte-oriented inst ruc tio ns, 'f' rep res ents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W reg ister . If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which select s the nu mb er of the bit a ffected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories :
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an osc illator frequency of 4 M Hz, th e normal instruc tion
execut ion tim e is 1 s. If a con dition al tes t is t rue or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 s.
Ta bl e 13 - 2 lists the instructions recognized by the
MPAS M™ asse mbler.
Figur e 13-1 shows the ge neral fo rmats th at the instruc -
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the PIC
Mid-Range MCU Family Reference Manual,
(DS33023).
Field Description
f Register file address (0x00 to 0x7F)
W Working register (acc umulato r)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store re sult in file register f.
Default is d = 1
PC Program Counter
TO Time-out bit
PD Power-down bit
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FIL E #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (l i te r a l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal )
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16C717/770/771
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TABLE 13-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERAT IONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Compleme nt f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nybbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERAT IONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Sk i p if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR liter a l with W
Move literal to W
Re tu r n from inter r upt
Return with literal in W
Return from Subrou tine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1999-2013 Microchip Technology Inc. DS41120C-page 135
PIC16C717/770/771
13.1 Instruction Descri ptions
ADDLW Add Literal and W
Syntax: [label] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are ad ded to the e ight bit litera l 'k'
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [label] ADDWF f,d
Operands: 0 f 12 7
d
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Add the con tents of the W re gister
with register 'f '. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in reg-
ister 'f'.
ANDLW AND Literal with W
Syntax: [label] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [label] ANDWF f,d
Operands: 0 f 12 7
d
Operation: (W) .AND. (f) (destination)
Status Affe cte d: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W regi st er. If 'd' is 1, the re sult
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [label] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affe cte d: None
Description: Bit 'b' in register 'f ' is clear ed.
BSF Bit Set f
Syntax: [label] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affe cte d: None
Description: Bit 'b' in register 'f' is set.
PIC16C717/770/771
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BTFSS Bit Test f, Skip if Set
Syntax: [label] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription: If bit 'b' in register ' f' is '0', th e next
instructi on is exec uted .
If bit 'b' is '1', then the next instruc-
tion is dis ca rded and a NOP is exe-
cuted in stead making this a 2TCY
instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [label] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Desc ription: If bit 'b' in register 'f' is '1', the next
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instruction is discarded, and
a NOP is exec uted instead , making
this a 2TCY instru ction.
CALL Call Subrout ine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate a ddress is loade d into P C bit s
<10:0>. The upper bits of the PC
are load ed from PCLA TH. CALL is
a two cycle inst ructi on.
CLRF Clear f
Syntax: [label] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affe cte d: Z
Description: The contents of register 'f' are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affe cte d: Z
Description: W register is cleared. Zero bit (Z)
is se t.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affe cte d: T O, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
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COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affected: Z
Description: The contents of register 'f' are
complemented. If 'd' is 0, the
result is stored in W. If 'd' is 1, the
result is stored back in register 'f'.
DECF Decrement f
Syntax: [label] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affected: Z
Description: Decrement register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register 'f' are
decremented. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in reg-
ister 'f'.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead
making it a 2TCY instructi on.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affe cte d: No ne
Description: GOTO is an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affe cte d: Z
Description: The contents of register 'f' are
incremented. If 'd' is 0, the result
is placed in the W regis ter. If 'd' is
1, the result is placed back in reg-
ister 'f'.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Affe cted: None
Description: The contents of register 'f' are
incremen ted. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in regis-
ter 'f'.
If the result is 1, the next instruc -
tion is executed. If the result is 0,
a NOP is exec ute d i ns tea d m ak ing
it a 2TCY instruction.
PIC16C717/770/771
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IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Affected: Z
Desc ription: The content s of the W reg ister are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 12 7
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Affected: Z
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destinati on )
Status Affected: Z
Description: The contents of register f are
moved t o a destination dependan t
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destinat ion is fil e register f itself . d
= 1 is useful to test a file register
since status flag Z is affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affe cte d: None
Description: The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affe cte d: None
Descripti on : Move d at a from W re gis ter to re g-
ister 'f'.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affe cte d: None
Description: No operation.
1999-2013 Microchip Technology Inc. DS41120C-page 139
PIC16C717/770/771
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the
eight bit liter al 'k '. The progra m
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed an d t he top o f th e s t a ck
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affe cte d: C
Description: The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the
result is placed in the W register.
If 'd' is 1, the result is stored back
in register 'f'.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 12 7
d [0,1]
Operation: See description below
Status Affe cte d: C
Description: The contents of register 'f' are
rotate d one bit to the righ t through
the C arry Flag. If 'd' is 0 , the result
is place d in the W register. If 'd' is
1, the result is placed back in reg-
ister 'f'.
SLEEP
Syntax: [ label
]SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affe cte d: TO, PD
Description: The power-down status bit, PD
is cleared. Time-out status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The proc essor is put i nto SLEEP
mode wi th the oscillator stopped.
See Section 12.8 for more
details.
Register fC
Register fC
PIC16C717/770/771
DS41120C-page 140 1999-2013 Microchip Technology Inc.
SUBLW Subtract W from Literal
Syntax: [ label ]SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Desc ript ion : The W register is subtra cte d (2’ s
complement method) from the
eight bit literal 'k'. The result is
placed i n the W regist er.
SUBWF Subtract W from f
Syntax: [ label ]SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF Swap Nybbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nybbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is plac ed in
register 'f'.
XORLW Exclusive OR Literal with W
Syntax: [label]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affe cte d: Z
Description: The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [label] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Affe cte d: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
1999-2013 Microchip Technology Inc. DS41120C-page 141
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14.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD
• Device Progra mm ers
-PRO MATE
® II Universa l De vi ce P rogrammer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demons trati on Boar d
- PICDEM 17 Demonstration Board
-KEELOQ® Demonstration Board
14.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• An inte rface to debugging tools
- simulator
- programmer (sold sep arately )
- emulator (so ld separat ely)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
• Customizable toolbar and key mapping
• A status bar
• On-line help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Debug us ing :
- source files
- abs olute listing file
- machine code
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
14.2 MPASM Assembler
The MPASM assembler is a full-featured universal
macro assembler for a ll PIC MCUs.
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be us ed through MPLAB ID E. The MP ASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
• Condit ion al as sem bl y for mult i-p urpo se sourc e
files.
• Directives that allow complete control over the
assembly process.
14.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C1 7 and MP LAB C18 Code De vel op me nt
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microc ontrollers, re spectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC16C717/770/771
DS41120C-page 142 1999-2013 Microchip Technology Inc.
14.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine w ill be linked in with the ap plicatio n. This allo ws
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
• Allows all m emory areas to be defined as se ctio ns
to provide l ink -time flex ibi lity.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
14.5 MPLAB SIM Software Simulator
The MPL AB SIM sof tware sim ulator allow s code de vel-
opment in a PC-hosted environment by simulating the
PIC s eri es m icroc ont roll ers on a n in stru cti on level . On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user-defined key press, to any of the pins. The execu-
tion can be performed in single step, execute until
break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MP ASM assembler . The software simulator
offers the flexibility to develop and debug code outside of
the laborat ory envir onment, making it an excellent mu lti-
project software development tool.
14.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers (MCUs). Software control of the MPLAB ICE
in-circu it emulator is provided by the MPLAB Integrated
Developm en t Environment (IDE), w hic h al lows edi tin g,
building, downloading and source debugging from a
single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC micro co ntrol le rs.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
14.7 ICEPIC In-Circuit Emulator
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular sy stem can su pport d ifferen t subset s of PIC16 C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
applic atio n circ ui try bei ng pres en t.
1999-2013 Microchip Technology Inc. DS41120C-page 143
PIC16C717/770/771
14.8 MPLAB ICD In-Circuit Debugger
Microc hip's In-Circu it Debugger , M PLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC MCUs and can be used to
develop for this and other PIC microcontrollers. The
MPLAB ICD utilizes the in-circuit debugging capability
built into the FLASH devices. This feature, along with
Microchip's In-Circuit Serial ProgrammingTM protocol,
offers cost-effective in-circuit FLASH debugging from
the graphical user interface of the MPLAB Integrated
Devel opm en t Env iron ment. Th is enables a design er to
deve lop and debug s ource c ode b y watchin g variab les,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time.
14.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
Stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In S tand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
devices. It can also set code protection in this mode.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated D evelopm ent Envir onment software m akes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76 X, may be suppor ted with an a dapter socket.
The PICSTART Plus development programmer is CE
compliant.
14.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microc hip’ s m icroc ontrol lers. T he mi croco ntrolle rs su p-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulato r and dow nload the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with t he PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches , a poten tiomet er for simula ted anal og inpu t, a
serial EEPROM to d emonstra te usage o f the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
PIC16C717/770/771
DS41120C-page 144 1999-2013 Microchip Technology Inc.
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-p in PLCC micro controlle rs with an LCD Mo d-
ule. All the necessary hardware and software is
includ ed to r un the basic dem onstrat ion pro grams . The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer , o r a PICST AR T Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided t o the use r for ad ding hardwa re and con necting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commo ns and 1 2 segments , tha t is capable of disp lay-
ing time, temperature and day of the week. The
PICDEM 3 d emons tration board pr ovi des an add itiona l
RS-232 interface and Windows software for showing
the demul tiplexed LC D signals on a PC. A si mple serial
interface allows the user to construct a hardware
demultip lexer for t he LCD signals.
14.14 PICDEM 17 Demonstration Board
The P ICDEM 17 de mo ns t rat i on bo a rd is an ev al u at i on
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hard ware is inc luded to ru n basic d emo progra ms,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstratio n board supports download ing of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMAST ER emulat or and al l of the sample progr ams
can be run and modified using either emulator . Addition-
ally, a generous prototype area is available for user
hardware.
14.15 KEELOQ Evaluati on and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
1999-2013 Microchip Technology Inc. DS41120C-page 145
PIC16C717/770/771
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
PIC18FXXX
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft war e Tool s
MPLAB® Integrated
Development Environment
MPLAB® C17 C Compile r
MPLAB® C18 C Compile r
MPASMTM Assembler/
MPLINKTM Obje ct Lin ke r
Emulators
MPLAB® ICE In-Circuit Emulator
**
ICEPICTM In-Circuit Emulator
Debugger
MPLAB® ICD In-Circuit
Debugger **
Programmers
PICSTART® Plus Entry Level
Devel opment Prog rammer
**
PRO MATE® II
Universal Device Programmer
**
Demo Boards and Eval Kits
PICDEMTM 1 Demonstration
Board
†
PICDEMTM 2 Demonstration
Board ††
PICDEMTM 3 Demonstration
Board
PICDEMTM 14A Demonstration
Board
PICDEMTM 17 Demonstration
Board
KEELOQ® Evaluation Kit
KEELOQ® Transp on d er Kit
microIDTM Programmer’s Kit
125 kHz microIDTM
Developer’s Kit
125 kHz Anticollision microIDTM
Developer’s Kit
13.56 MHz Antic olli sion
microIDTM Developer’s Kit
MCP2510 CAN Developer’s Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC16C717/770/771
DS41120C-page 146 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 147
PIC16C717/770/771
15.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Maximum voltage between AVDD and VDD pins 0.3V
Maximum voltage between AVSS and VSS pins 0.3V
Voltage on MCLR with respect to VSS........................................................................................................-0.3V to +8.5V
Voltage on RA4 with respect to Vss.........................................................................................................-0.3V to +10.5V
Total power dissipati on (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current i nto VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current , IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum current sunk byPORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined) ...........................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {I DD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16C717/770/771
DS41120C-page 148 1999-2013 Microchip Technology Inc.
FIGURE 15-1: PI C16C7 17/7 70/771 VOLTAGE-FREQUE NCY GR APH, -4 0C TA +85C
FIGURE 15-2: PI C16L C7 17/7 70/7 71 VOLTAGE-FREQUENCY GRAPH, 0C TA +70C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
1999-2013 Microchip Technology Inc. DS41120C-page 149
PIC16C717/770/771
FIGURE 15-3: PI C16L C7 17/7 70/7 71 VOLTAGE-FREQUENCY GRAPH,
-40C TA 0C, +70C TA +85C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16C717/770/771
DS41120C-page 150 1999-2013 Microchip Technology Inc.
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C f or industrial
-40°C TA +125°C for extended
PIC16C717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +1 25°C for exte nde d
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.5 — 5.5 V
D001 VDD Supply Voltage 4.0 —5.5 V
D002* VDR RAM Data Retention
Voltage(1) —1.5— V
D002* VDR RAM Data Retention
Voltage(1) —1.5 — V
D003* VPOR VDD start voltage to
ensure internal Power-
on Reset signal
—VSS — V See section on Power-on Reset for details
D003* VPOR VDD start voltage to
ensure internal Power-
on Reset signal
—VSS — V See section on Power-on Reset for details
D004* SVDD VDD rise rate to ensure
internal Po we r-on Re set
signal
0.05 — — V/ms See section on Power-on Reset for details.
PWRT enabled
D004* SVDD VDD rise rate to ensure
internal Po we r-on Re set
signal
0.05 — — V/ms See section on Power-on Reset for details.
PWRT enabled
* These parameters are characterized but not tested.
† Dat a i n " Typ" c ol um n i s a t 5V, 25°C unless ot herwise st ated . These p aram ete rs are for d es ign guidance on ly
and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
1999-2013 Microchip Technology Inc. DS41120C-page 151
PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
(Continued)
PIC16LC717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C f or industrial
-40°C TA +125°C for extended
PIC16C717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +1 25°C for exte nde d
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
IDD Supply Current(2)
D010D
D010E
D010G
D010K
PIC16LC7XX 1.0
0.36
11
2.0
3.0
1.0
45
mA
mA
A
FOSC = 10 MHz, VDD = 3V, -40°C to 85°C
FOSC = 10 MHz, VDD = 3V, -40°C to 125°C
FOSC = 4 MHz, VDD = 2.5V, -40°C to 125°C
FOSC = 32 kHz, VDD = 2.5V, -40°C to 125°C
IDD Supply Current(2)
D010
D010A
D010B
D010C
D010F
D010H
D010J
PIC16C7XX 4.0
2.5
0.55
30
7.5
12.0
5.0
6.0
1.5
80
95
mA
mA
mA
A
FOSC = 20 MHz, VDD = 5.5V, -40°C to 85°C
FOSC = 20 MHz, VDD = 5.5V, -40°C to 125°C
FOSC = 20 MHz, VDD = 4V, -40°C to 85°C
FOSC = 20 MHz, VDD = 4V, -40°C to 125°C
FOSC = 4 MHz, VDD = 4V, -40°C to 125°C
FOSC = 32 kHz, VDD = 4V, -40°C to 85°C
FOSC = 32 kHz, VDD = 4V, -40°C to 125°C
* These parameters are characterized but not tested.
† Dat a in "Typ" col umn is at 5V, 25°C unless o therw ise st ated . These para meters are for des ign gu idanc e only
and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The sup ply cu rrent is main ly a fu nct ion of the operatin g v ol tage and fre que nc y. Other fac tors s uch as I/O p in
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
PIC16C717/770/771
DS41120C-page 152 1999-2013 Microchip Technology Inc.
IPD Power-down Current(3)
D020D
D020E
D020F
D020G
PIC16LC7XX 0.3
0.1
2.0
5.0
1.5
3.0
A
A
VDD = 3V, -40°C to 85°C
VDD = 3V, -40°C to 125°C
VDD = 2.5V, -40°C to 85°C
VDD = 2.5V, -40°C to 125°C
D020
D020A
D020B
D020C
PIC16C7XX 1.4
1.0
4.0
8.0
3.5
6.0
A
A
VDD = 5.5V, -40°C to 85°C
VDD = 5.5V, -40°C to 125°C
VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
* These parameters are characterized but not tested.
† Dat a in "Typ" col umn is at 5V, 25°C unless o therwis e sta ted . These p ara meters are fo r desig n guida nce on ly
and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The sup ply cu rren t is m ain ly a function of t he o perating vol t age and frequenc y. Other factors s uc h as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or V SS.
PIC16LC717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C f or industrial
-40°C TA +125°C for extended
PIC16C717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +1 25°C for exte nde d
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
1999-2013 Microchip Technology Inc. DS41120C-page 153
PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/77 1 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
(Continued)
PIC16LC717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C f or industrial
-40°C TA +125°C for extended
PIC16C717/770/771
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +1 25°C for exte nde d
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
Base plus Module c urrent
D021A IWDT Watchdog Timer 2 10 AVDD = 3V, -40°C to 125°C
D021 IWDT Watchdog Timer 520 A VDD = 4V, -40°C to 125°C
D021 IWDT Watchdog Timer 5 20 AVDD = 4V, -40°C to 125°C
D025 IT1OSC Timer1 Oscillator 3 9 AVDD = 3V, -40°C to 125°C
D025 IT1OSC Timer1 Oscillator 412 A VDD = 4V, -40°C to 125°C
D025 IT1OSC Timer1 Oscillator 4 12 AVDD = 4V, -40°C to 125°C
D026* IAD ADC Conv erter 300 A VDD = 5.5V, A/D on, not converting
D026* IAD ADC Conv erter 300 AVDD = 5.5V, A/D on, not converting
D027
D027A IPLVD Programmable Low
Voltage De tec t 55 125
150
A VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
D027
D027A IPLVD Programmable Low
Voltage De tec t 55 125
150
AVDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
D028
D028A IPBOR Programmable Brown-
out Reset 55 125
150
A VDD = 5V, -40°C to 85°C
VDD = 5V, -40°C to 125°C
D028
D028A IPBOR Programmable Brown-
out Reset 55 125
150
AVDD = 5V, -40°C to 85°C
VDD = 5V, -40°C to 125°C
D029
D029A IVRH Voltage referenc e Hi gh 200 750
1.0
A
mA VDD = 5V, -40°C to 85°C
VDD = 5V, -40°C to 125°C
D029
D029A IVRH Voltage referenc e Hi gh 200 750
1.0
A
mA VDD = 5V, -40°C to 85°C
VDD = 5V, -40°C to 125°C
D030
D030A IVRL Voltage referenc e Low 200 750
1.0
A
mA VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
D030
D030A IVRL Voltage referenc e Low 200 750
1.0
A
mA VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
* These parameters are characterized but not tested.
† Dat a in "Typ" colum n is at 5V, 25°C u nle ss o therwise stated. Th ese parameters ar e f or d es ign g uidance on ly
and are not tested.
PIC16C717/770/771
DS41120C-page 154 1999-2013 Microchip Technology Inc.
15.2 DC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771 (Commercial,
Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unle ss otherwis e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C f or industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in Section 15.1 and
Section 15.2.
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS — 0.15VDD V For entire VDD range
D030A VSS —0.8VV4.5V VDD 5.5V
D031 with Schmitt Trigger buffer VSS —0.2VDD V For entire VDD range
D032 MCLR VSS —0.2VDD V
D033 OSC1 (in XT, HS, LP and EC) VSS —0.3VDD V
Input High Voltage
VIH I/O ports —
D040 with TTL buffer 2.0 — VDD V4.5V VDD 5.5V
D040A (0.25VDD
+ 0.8V) —VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD —VDD V For entire VDD range
D042 MCLR 0.8VDD —VDD V
D042A OSC1 (XT, HS, LP and EC) 0 .7VDD —VDD V
D070 IPURB PORTB weak pull-up current
per pin 50 250 400 AVDD = 5V, VPIN = VSS
Input Leakage Current (1,2)
D060 IIL I/O ports (with digital functions) — — 1AVss VPIN VDD, Pin at hi-impedance
D060A IIL I/O ports (with analog func-
tions) ——100 nA Vss VPIN VDD, Pin at hi-impedance
D061 RA5/MCLR/VPP ——5AVss VPIN VDD
D063 OSC1 — — 5AVss VPIN VDD, XT, HS, LP and EC
osc configuration
Output Low Voltage
D080 VOL I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V
Output High Voltage
D090 VOH I/O ports(2) VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V
D150* VOD Open Drain High Voltage — — 10.5 V RA4 pin
Capacitive Load ing Specs on
Output Pins*
D100 COS
C2 OSC2 pin — — 15 pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102 CIO
CBAll I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode —
——
—50
400 pF
pF
CVRH VRH pin ——
200 pF VRH output enabled
CVRL VRL pin ——
200 pF VRL output enabled
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The le akage current o n th e M CLR pin is s tron gly d ependent on the applied vol t age level. Th e s pec if ied levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.
1999-2013 Microchip Technology Inc. DS41120C-page 155
PIC16C717/770/771
15.3 AC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771
(Commercial, Industrial, Extended)
15.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and t heir meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C (I2C specifications only)
AA output acce ss
BUF Bus free
High High
Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
PIC16C717/770/771
DS41120C-page 156 1999-2013 Microchip Technology Inc.
FIGURE 15-4: LOAD CONDITIONS
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL=464
CL=50 pF for all pins except OSC2
15 pF for OSC2 output
Load condition 1 Load condition 2
1999-2013 Microchip Technology Inc. DS41120C-page 157
PIC16C717/770/771
15.3.2 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 15-5: CLKOUT AND I/O TIMING
TABLE 15-1: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
No. Sym Characteristic Min Typ† Max Unit
sConditions
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT to Port out valid — — 0.5 TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT 0.25TCY + 25 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT 0——nsNote 1
17* TosH2ioV OSC1 (Q1 cycle) to
Port out valid — 50 150 ns
18* TosH2ioI OSC1 (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C717/770/771 100 — — ns
PIC16LC717/770/771 200 — — ns
19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C717/770/771 —1025ns
PIC16LC717/770/771 — — 60 ns
21* TioF P ort output fall time PIC16C717/770/771 —1025ns
PIC16LC717/770/771 — — 60 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB <7:0> change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken ER or INTRC w/CLKOUT mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 15-4 for load conditions.
OSC1
CLKOUT(1)
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
13 14
17
20, 21
19 18
15
12 16
old value new value
PIC16C717/770/771
DS41120C-page 158 1999-2013 Microchip Technology Inc.
FIGURE 15-6: EX TERNAL CLOCK TIMING
OSC1
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param No. Sym Characteristic Min Typ† Max Units Conditions
1A FOSC Ex terna l CLKIN Frequency
(Note 1) DC — 4 MHz XT mode
DC — 20 MHz EC mode
DC — 20 MHz HS mode
DC — 200 kHz LP mode
Oscillator Frequency
(Note 1) 0.1* — 4 MHz XT mode
4*
5* —
—20
200 MHz
kHz HS mode
LP mode
1T
OSC External CLKIN Period
(Note 1) 250 — — ns XT mode
50 — — ns EC mode
50 — — ns HS mode
5— —s LP mode
Oscillator Period
(Note 1) 250 — 10,000* ns XT mode
50 — 250* ns HS mode
5— —s LP mode
2T
CY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC
3* TosL,
TosH External Clock in (OSC1) High or Low
Time 100 — — ns XT mode
2.5 — — s LP mode
15 — — ns HS mode
EC mode
4* TosR,
TosF External Clock in (OSC1) Rise or Fall
Time — — 25 ns XT mode
— — 50 ns LP mode
— — 15 ns HS mode
EC mode
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "Max. Frequency" values with a square wave applied to the OSC1/CLKIN
pin.
When an external clock input is used, the "Min." frequency (or Max . TCY) limit is "DC" (no clock) for all devices.
1999-2013 Microchip Technology Inc. DS41120C-page 159
PIC16C717/770/771
TABLE 15-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC16C717/770/771 AND
PIC16LC717/770/771
FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMI NG
FIGURE 15-8: BROWN-OUT RESET TIMING
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating Voltage VDD range is described in Section and Section
Parameter
No. Sym Characteristic Min Typ(1)* Max Units Conditions
FIRC Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5.0V
Internal RC Frequency* 3.55 4.00 4.31 MHz VDD = 2.5V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 15-4 for load conditions.
VDD VBOR
35
PIC16C717/770/771
DS41120C-page 160 1999-2013 Microchip Technology Inc.
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
FIGURE 15-9: BROWN-OUT RESET CHARACTERISTICS
FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOC K TIMINGS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30* TMCL MCLR Pulse Width (low) 2 — — sVDD = 5V, -40°C to +85°C
31* TWDT Watchdog Timer T ime-out Period
(No Prescaler) 71833msVDD = 5V, -40°C to +85°C
32* TOST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
33* TPWRT P ower up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34* TIOZ I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset ——2.1s
35* TBOR B rown-out Reset pulse width 100 — — sVDD VBOR (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VBOR
RESET (due to BOR)
VDD
(device in Brown-out Reset)
(device not in Brown-out Reset)
72 ms time-out
Note: Refer to Figure 15-4 for load conditio ns.
46
47
45
48
41
42
40
RA4/T0CKI
RB6/T1OSO/T1CKI/PIC
TMR0 o r
TMR1
1999-2013 Microchip Technology Inc. DS41120C-page 161
PIC16C717/770/771
TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
FIGURE 15-11: ENHANCED CAPTURE/COMPARE/PWM TIMINGS (ECCP)
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
paramete r 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
paramete r 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 2 56 )
45* Tt1H T1CKI High Time Synchro nous, Prescaler = 1 0.5TCY + 20 — — ns Mu st also me et
paramete r 47
Synchronous,
Prescaler =
2,4,8
PIC16C717/770/771 15 — — ns
PIC16LC717/770/771 25 — — ns
Asynchronous PIC16C717/770/771 30 — — ns
PIC16LC717/770/771 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Mu st also meet
paramete r 47
Synchronous,
Prescaler =
2,4,8
PIC16C717/770/771 15 — — ns
PIC16LC717/770/771 25 — — ns
Asynchronous PIC16C717/770/771 30 — — ns
PIC16LC717/770/771 50 — — ns
47* Tt1P T1CKI input period Synchronou s PIC16C717/770/771 Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LC717/770/771 Greater of:
50 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C717/770/771 60 — — ns
PIC16LC717/770/771 100 — — ns
Ft1 Timer1 osc illator input frequency range
(oscillator enabled by setti ng bit T1OSCEN) DC — 50 kHz
48 Tcke2tmr1 Delay fro m ext ernal clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 15-4 for load conditions.
RB3/CCP1/P1A
(Capture Mode)
50 51
52
53 54
RB3/CCP1/P1A
(Compare or PWM Mode)
PIC16C717/770/771
DS41120C-page 162 1999-2013 Microchip Technology Inc.
TABLE 15-6: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 input low
time No Prescaler 0.5TCY + 20 — — ns
With Prescaler
PIC16C717/770/771 10 — — ns
PIC16LC717/770/771 20 — — ns
51* TccH CCP1 input high
time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C717/770/771 10 — — ns
PIC16LC717/770/771 20 — — ns
52* TccP CCP1 input period 3TCY + 40
N— — ns N = prescale value
(1, 4 or 16)
53* Tcc R CCP1 output fall time PIC16C717/770/771 —1025ns
PIC16LC717/770/771 —2545ns
54* Tcc F CCP1 output fall time PIC16C717/770/771 —1025ns
PIC16LC717/770/771 —2545ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These paramet ers are for design guidance only and are not
tested.
1999-2013 Microchip Technology Inc. DS41120C-page 163
PIC16C717/770/771
15.4 Analog Peripherals Characteristics: PIC16C717/770/771 & PIC16LC717/770/771
(Commercial, Industrial, Extended)
15.4.1 BANDGAP MODULE
FIGURE 15-12: BANDGAP START-UP T I ME
TABLE 15-7: BANDGAP START-UP TIME
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
36* TBGAP Bandgap start-up time — 19 33 S Defined as the time between the
instant that the bandgap is
enabled and the moment that
the bandgap reference voltage
is stable.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VBGAP = 1.2V
VBGAP
Enable Bandgap
Bandgap stable TBGAP
(internal use only)
PIC16C717/770/771
DS41120C-page 164 1999-2013 Microchip Technology Inc.
15.4.2 LOW VOLTAGE DETECT MODULE (LVD)
FIGURE 15-13: LOW VOLTAGE DETECT CHARACTERISTICS
TABLE 15-8: ELECTRICAL CHARACTERISTICS: LVD
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operati ng tem pera ture -40 °C TA +85°C for industrial and
0°C TA +70°C for commercial
Operati ng voltage VDD range as de scribed in DC Characteristics Sect ion 15.1.
Param.
No. Characteristic Symbol Min Typ† Max Units Conditions
D420* LVD Voltage LVV = 0100
VLVD
2.5 2.58 2.66 V
LVV = 0101 2.7 2.78 2.86 V
LVV = 0110 2.8 2.89 2.98 V
LVV = 0111 3.0 3.1 3.2 V
LVV = 1000 3.3 3.41 3.52 V
LVV = 1001 3.5 3.61 3.72 V
LVV = 1010 3.6 3.72 3.84 V
LVV = 1011 3.8 3.92 4.04 V
LVV = 1100 4.0 4.13 4.26 V
LVV = 1101 4.2 4.33 4.46 V
LVV = 1110 4.5 4.64 4.78 V
* These parameters are characterized but not tested.
Note 1: Production tested at Tamb = 25°C. Specifications over temperature limits ensured by characterization.
VLVD
LVDIF
VDD
(LVDIF set by hardware)
(LVDIF can be cleared in software anytime during
the gray area)
1999-2013 Microchip Technology Inc. DS41120C-page 165
PIC16C717/770/771
15.4.3 PROGRAMMABLE BROWN-OUT RESET MOD ULE (PBOR)
TABLE 15-9: DC CHARACTERISTICS: PBOR
15.4.4 VREF MODULE
TABLE 15-10: DC CHARACTERISTICS: VREF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC Characteristics Section 15.1.
Param.
No. Characteristic Symbol Min Typ Max Units Conditions
D005 BOR Voltage BORV<1:0 > = 11
VBOR
2.5 2.58 2.66
V
BORV<1:0> = 10 2.7 2.78 2.86
BORV<1:0> = 01 4.2 4.33 4.46
BORV<1:0> = 00 4.5 4.64 4.78
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70°C for comme rcial
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC Characteristics
Section 15.1.
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
D400 VRL Output Voltage 2.0 2.048 2.1 V VDD 2.7V, -40°C TA +85°C
VRH 4.0 4.096 4.2 V VDD 4.5V, -40°C TA +85°C
D400A VRL Output Voltage 1.9 2.048 2.2 V VDD 2.7V, -40°C TA +125°C
VRH 4.0 4.096 4.3 V VDD 4.5V, -40°C TA +125°C
D404* IVREFSO External Load S ource — — 5 mA
D405* IVREFSI External Lo ad Si nk — — -5 mA
* CL External Capacitor Load — — 200 pF
D406* Vout/
Iout VRH Load Regulation — 0.6 1 mV/mA VDD 5V ISOURCE = 0 mA to 5 mA
—1 4 I
SINK = 0 mA to 5 mA
VRL Load Regulation — 0.6 1 VDD 3V ISOURCE = 0 mA to 5 mA
—2 4 ISINK = 0 mA to 5 mA
* These parameters are characterized but not tested.
† Dat a in “T yp ” column is at 5V, 25C unles s otherwise sta ted. These p aramet ers are
for design guidance only and are not tested.
PIC16C717/770/771
DS41120C-page 166 1999-2013 Microchip Technology Inc.
15.4.5 A/D CONVERTER MODULE
TABLE 15-11: PIC16C770/771 AND PIC16LC770/771 A/D CONVERTER CHARACTERISTICS:
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 12 bits bit Min. resolution for A/D is 1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A03 EIL Integral error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A04 EDL Differential error — — +2
-1
LSb No missing codes to 12 bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A06 EOFF Offset error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A07 EGN Gain Error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A10 — Monotonicity — Note 3 — — AVSS VAIN VREF+
A20* VREF Reference voltage
(VREF+ - VREF-) 4.096 — VDD
+0.3V V Absolute minimum electrical spec to
ensure 12-bit accuracy.
A21* VREF+ Reference V High
(AVDD or VREF+) VREF-— AVDD V Min. resolution for A/D is 1 mV
A22* VREF- Reference V Low
(AVSS or VREF-) AVSS —VREF+ V Min. resolution for A/D is 1 mV
A25* VAIN Analog input volt-
age VREFL —VREFH V
A30* ZAIN Recommended
impedance of ana-
log voltage source
——2.5k
A50* IREF VREF input current
(Note 2) ——10A During VAIN acquisition.
Based on differential of VHOLD to
VAIN.
To charge CHOLD see Section 11.0.
Durin g A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: When A/D is of f, it w il l not c onsum e any current other than mi nor le ak age curre nt. The power-d ow n curren t
spec includes any such leakage from the A/D module.
2: VREF input current is from External VREF+, or VREF-, or AVSS, o r AV DD pin, whichever is selected as refer-
ence input.
3: The A/D conv ersion resul t neve r decre ases with an incre ase i n the i nput v olt age a nd has no missi ng cod es.
1999-2013 Microchip Technology Inc. DS41120C-page 167
PIC16C717/770/771
FIGURE 15-14: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (NORMAL
MODE)
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
11 10 9 3 2 1 0
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
1/2 TCY
8
134
DONE
PIC16C717/770/771
DS41120C-page 168 1999-2013 Microchip Technology Inc.
TABLE 15-12: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENTS
(NORMAL MODE)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
130*(3) TAD A/D clock period 1.6 — — s Tosc based, VREF 2.5V
3.0 — — s Tosc based, VREF full range
3.0 6.0 9.0 s
ADCS<1:0> = 11
(A/D RC mode)
At VDD = 2.5V
2.0 4.0 6.0 sAt V
DD = 5.0V
131* TCNV Conversion time
(not includin g
acquisition time)
(Note 1)
—13TAD —TAD
132* TACQ Acquisition Time Note 2
5*
11.5
—
—
—
s
s The mini mum time is the ampli-
fier settling time. This may be
used if the “new” input vol t ag e
has not changed by more than
1LSb (i.e., 1mV @ 4.096V) from
the last sampled voltage (as
stated on CHOLD).
134* TGO Q4 to A/D clock
start —TOSC/2 — —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
1999-2013 Microchip Technology Inc. DS41120C-page 169
PIC16C717/770/771
FIGURE 15-15: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (SLEEP MODE)
TABLE 15-13: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENT
(SLEEP MODE)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
130*(3) TAD A/D Internal RC
oscillator period 3.0 6.0 9.0 sADCS<1:0> = 11 (RC mode)
At VDD= 3.0V
2.0 4.0 6.0 sAt V
DD = 5.0V
131* TCNV Conversion time (not
including acquisition
time) (Note 1)
— 13TAD ——
132* TACQ Acquisition T ime (Note 2)
5*
11.5
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D cl ock start — TOSC/2 + TCY — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRE S regist er may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMP LING STOPPED
NEW_DATA
11 9 3 2 1 0
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
134
8
10
132
DONE
PIC16C717/770/771
DS41120C-page 170 1999-2013 Microchip Technology Inc.
TABLE 15-14: PIC16C717 AND PIC16LC717 A/D CONVERTER CHARACTERISTICS:
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 10 bits bit Min. resolution for A/D is 4.1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A03 EIL Integral error — — ±1 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A04 EDL Differential error — — ±1 LSb No missing codes to 10 bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A06 EOFF Offset error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A07 EGN Gain Error — — ±1 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- VAIN VREF+
A10 — Monotonicity — Note 3 — — AVSS VAIN VREF+
A20* VREF Reference voltage
(VREF+ - VREF-) 4.096 — VDD +0.3V V Absolute minimum electrical spec to
ensure 10-bit accuracy.
A21* VREF+Reference V High
(AVDD or VREF+) VREF-— AVDD V Min. resolution for A/D is 4.1 mV
A22* VREF-Reference V Low
(AVSS or VREF-) AVSS —VREF+ V Min. resolution for A/D is 4.1 mV
A25* VAIN Analog input voltage VREFL —VREFH V
A30* ZAIN Recomm ended
impedance of analog
voltage source
——2.5k
A50* IREF VREF input current
(Note 2) ——10A During VAIN acquisition.
Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such
leakage from the A/D module.
2:VREF current is from External VREF+, or VREF-, or AVSS, or AVDD pin, whichever is selected as reference input.
3:The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
1999-2013 Microchip Technology Inc. DS41120C-page 171
PIC16C717/770/771
FIGURE 15-16: PIC16C717 A/D CONVERSION TIMING (NORMAL MODE)
TABLE 15-15: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (NORMAL MODE)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
130*(3) TAD A/D clock period 1.6 — — s Tosc based, VREF 2.5V
3.0 — — s Tosc based, VREF full range
3.0 6.0 9.0 sADCS<1:0> = 11 (A/D RC mode)
At VDD = 2.5V
2.0 4.0 6.0 sAt V
DD = 5.0V
131* TCNV Conversion time (not
including
acquisition time)
(Note 1)
—11TAD —TAD
132* TACQ Acquisition T ime (No te 2)
5*
11.5
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) fro m the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 — —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3:These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
987 3210
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
1/2 TCY
6
134
DONE
PIC16C717/770/771
DS41120C-page 172 1999-2013 Microchip Technology Inc.
FIGURE 15-17: PIC16C717 A/D CONVERSI ON TIMING (SLEEP MODE)
TABLE 15-16: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (SLEEP MODE)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
130*(3) TAD A/D clock period 3.0 6.0 9.0 s ADCS<1:0> = 11 (A/D RC mode)
At VDD = 3.0V
2.0 4.0 6.0 sAt V
DD = 5.0V
131* TCNV Conversion time (not
including acquisition
time) (Note 1)
—11TAD ——
132* TACQ Acquisition Time (Note 2)
5*
11.5
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 + TCY — — If the A/D RC clock source is
selected, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMP LING STOPPED
DONE
NEW_DATA
9 7 3210
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
134
6
8
132
1999-2013 Microchip Technology Inc. DS41120C-page 173
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15.5 Master SSP SPI Mode Timing Waveforms and Requireme nts
FIGURE 15-18: SPI MASTER MODE TIMING (CKE = 0)
TABLE 15-17: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
70* TssL2scH,
TssL2scL SS to SCK or SCK input TCY ——ns
71* TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — — ns
71A* Single Byte 40 — — ns Note 1
72* TscL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — — ns
72A* Single Byte 40 — — ns Note 1
73* TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns
73A* TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 — — ns Note 1
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75* TdoR SDO data output rise time PIC16CXXX — 10 25 ns
PIC16LCXXX — 20 45 ns
76* TdoF SDO data outp ut fall time — 10 25 ns
78* TscR SCK output rise time
(Master mo de) PIC16CXXX — 10 25 ns
PIC16LCXXX — 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV,
TscL2doV SDO data outp ut val id
after SCK edge PIC16CXXX — — 50 ns
PIC16LCXXX — — 100 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Re fe r to Figure 15-4 for load conditions.
PIC16C717/770/771
DS41120C-page 174 1999-2013 Microchip Technology Inc.
FIGURE 15-19: SPI MASTER MODE TIMING (CKE = 1)
TABLE 15-18: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
71* TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — — ns
71A* Single Byte 40 — — ns Note 1
72* TscL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — — ns
72A* Single Byte 40 — — ns Note 1
73* TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 100 — — ns
73A* TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 — — ns Note 1
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75* TdoR SDO data output rise
time PIC16CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
76* TdoF SDO data outp ut fall time — 10 25 ns
78* TscR SCK output rise time
(Master mo de) PIC16CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV,
TscL2doV SDO data outp ut val id
after SCK edge PIC16CXXX — — 50 ns
PIC16LCXXX — 100 ns
81* TdoV2scH,
TdoV2scL SDO data output setup to SCK edge TCY ——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 15-4 for load conditions.
1999-2013 Microchip Technology Inc. DS41120C-page 175
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FIGURE 15-20: SPI SLAVE MODE TIMING (CKE = 0)
TABLE 15-19: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
70* TssL2scH,
TssL2scL SS to SCK or SCK input TCY ——ns
71* TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — — ns
71A* Single Byte 40 — — ns Note 1
72* TscL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — — ns
72A* Single Byte 40 — — ns Note 1
73* TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns
73A* TB2BLast clock edge of Byte1 to the 1st clock edge
of Byte2 1.5TCY + 40 — — ns Note 1
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75* TdoR SDO data output rise time PIC16CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
76* TdoF SDO data output fall time — 10 25 ns
77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns
78* TscR SCK output rise time (Master
mode) PIC16CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
79* TscF S CK out put fall time (Master mode) — 10 25 ns
80* TscH2doV,
TscL2doV SDO data output valid after
SCK edge PIC16CXXX — — 50 ns
PIC16LCXXX — 100 ns
83* TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BIT6 - - - -1 LSb IN
83
Note: Re fe r to Figure 15-4 for load conditions.
PIC16C717/770/771
DS41120C-page 176 1999-2013 Microchip Technology Inc.
FIGURE 15-21: SPI SLAVE MODE TIMING (CKE = 1)
TABLE 15-20: SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
70* TssL2scH,
TssL2scL SS to SCK or SCK inp u t TCY ——ns
71* TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — — ns
71A* Single Byte 40 — — ns Note 1
72* TscL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — — ns
72A* Single Byte 40 — — ns Note 1
73A* TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 — — ns Note 1
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75* TdoR SDO data output rise time PIC16 CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
76* TdoF SDO data output fall time — 10 25 ns
77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns
78* TscR SCK output rise time (Mas-
ter mode) PIC16CXXX — 10 25 ns
PIC16LCXXX — 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV,
TscL2doV SDO data output valid after
SCK edge PIC16CXXX — — 50 ns
PIC16LCXXX — — 100 ns
82* TssL2doV SDO data output valid after
SS edge PIC16CXXX — — 50 ns
PIC16LCXXX — — 100 ns
83* TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 — — ns
* T hese parameters are charact erized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb BIT6 - - - - - -1 LSb
77
MSb IN BIT6 - - - -1 LSb IN
80
83
Note: Refer to Figure 15-4 fo r load conditions.
1999-2013 Microchip Technology Inc. DS41120C-page 177
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15.6 Master SSP I2C Mode Timing Waveforms and Requirements
FIGURE 15-22: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
TABLE 15-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 15-23: MASTER SSP I2C BUS DATA TIMING
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
90* TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns Only relevant for a Repeated
START
condition
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — —
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
91* THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns Af ter this period the first clock
pulse is generated
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — —
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
92* TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — —
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
93* THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — —
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
* These parameters are characterized but not tested. For the value required by the I2C specification, please refer to the PICmi-
croTM Mid-Range MCU Family Reference Manual (DS33023).
Maximum pin capacitance = 10 pF for all I2C pins.
Note: Refer to Figure 15-4 for load conditions.
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
Note: Refer to Figure 15-4 for load conditions.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
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DS41120C-page 178 1999-2013 Microchip Technology Inc.
TABLE 15-22: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100* THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
101* TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
102* TRSDA and SCL
rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF 400 kHz mode 20 + 0.1Cb 300 ns
1 MHz mode(1) — 300 ns
103* TFSDA and SCL
fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF 400 kHz mode 20 + 0.1Cb 300 ns
1 MHz mode(1) — 100 ns
90* TSU:STA START condition
setup time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Repeated
START
condition
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
91* THD:STA START condition
hold time 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period the first clock
pulse is generated400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
106* THD:DAT Data input
hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 ms
1 MHz mode(1) TBD — ns
107* TSU:DAT Data input
setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
1 MHz mode(1) TBD — ns
92* TSU:STO STOP condition
setup time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
109* TAA Output valid from
clock 100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(1) ——ns
110 TBUF Bus free time 100 kHz mode 4.7 ‡ — ms Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 ‡ — ms
1 MHz mode(1) TBD‡ — ms
D102 ‡ Cb Bus capacitive loading — 400 pF
* These parameters are characterized but not tested. For the value required by the I2C specification, please refer to the
PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
‡ These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Maxim um pin capacitance = 10 pF for all I2C pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but (TSU:DAT) 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
[(TR)+(TSU:DAT) = 1000 + 250 = 1250 ns], for 100 kHz mode, before the SCL line is released.
1999-2013 Microchip Technology Inc. DS41120C-page 179
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16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3 ) or
(mean - 3) respectively, where is a standard deviation, over the whole temperature range.
The FOSC IDD was determined using an external sinuso idal clock source with a peak amplitu de ranging from VSS to VDD.
FIGURE 16-1: MAX IMU M IDD VS . FOSC OVER VDD (HS MOD E )
The graphs and tables provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not tested or
guarante ed. In som e graphs or tab les, the data presen ted may be ou tsi de the sp ecifie d operati ng range (e.g. , outs ide
specified power supply range) and therefore outside the warranted range.
0.0
1.0
2.0
3.0
4.0
5.0
6.0
4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
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FIGURE 16-2: TYPICAL IDD VS. FOSC OVER VDD (HS MODE)
FIGURE 16-3: MAX IMU M IDD VS . FOSC OVER VDD (X T MOD E)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)
IDD (mA)
5.5V
4.0V
3.0V
2.5V
4.5V
3.5V
5.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
1999-2013 Microchip Technology Inc. DS41120C-page 181
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FIGURE 16-4: TYPICAL IDD VS. FOSC OVER VDD (XT MODE)
FIGURE 16-5: MAX IMU M IDD VS. F OSC OVER VDD (L P MODE)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.000
0.020
0.040
0.060
0.080
0.100
0.120
0.140
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
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FIGURE 16-6: TYPICAL IDD VS. FOSC OVER VDD (LP MODE)
FIGURE 16-7: MAX IMU M IDD VS. F OSC OVER VDD (EC MODE)
0.000
0.020
0.040
0.060
0.080
0.100
0.120
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
FOSC (MHz)
IDD (mA)
5.5V
4.0V
3.0V
2.5V
4.5V
3.5V
5.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
1999-2013 Microchip Technology Inc. DS41120C-page 183
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FIGURE 16-8: TYPICAL IDD VS. FOSC OVER VDD (EC MODE)
FIGURE 16-9: MAX IMU M IDD VS. F OSC OVER VDD (ER MODE)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (mA)
R = 38.3 K
R = 100 K
R = 200 K
R = 499 K
R = 1 M
R = 38.3 k
R = 100 k
R = 200 k
R = 499 k
PIC16C717/770/771
DS41120C-page 184 1999-2013 Microchip Technology Inc.
FIGURE 16-10: TYPICAL IDD VS. FOSC OVER VDD (ER MODE)
FIGURE 16-11: TYP ICAL FOSC VS. VDD (ER MODE)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (mA)
R = 38.3 K
R = 100 K
R = 200 K
R = 499 K
R = 1 M
R = 38.3 k
R = 100 k
R = 200 k
R = 499 k
0.1
1.0
10.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vdd (V)
Frequency (MHz)
R = 38.3 K
R = 100 K
R = 200 K
R = 499 K
R = 1 M
R = 38.3 k
R = 100 k
R = 200 k
R = 499 k
VDD (V)
1999-2013 Microchip Technology Inc. DS41120C-page 185
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FIGURE 16-12 : MAXIMU M IDD VS. V DD (INTRC 37 kHZ MODE)
FIGURE 16-13: TYPICAL IDD VS. VDD (INTRC 37 kHZ MODE)
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)
IDD (mA)
Typ (25 °C)
Max (-40 °C)
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (mA)
-40 °C
25 °C
85 °C
125 °C
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FIGURE 16-14: INTERNAL RC FOSC VS. VDD OVER TEMPERATURE (37 kHZ)
FIGURE 16-15: MAXIMUM AND TYPICAL IDD VS. V DD (INTRC 4 MHz MODE)
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0.055
0.060
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FOSC (MHz)
Max (125 °C)
Typ (25 °C)
Min(-40° C)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)
IDD (mA)
Max (-40 °C)
Typ (25 °C)
1999-2013 Microchip Technology Inc. DS41120C-page 187
PIC16C717/770/771
FIGURE 16-16: TYPICAL IDD VS. VDD (INTRC 4 MHz MODE)
FIGURE 16-17: INTERNAL RC FOSC VS. VDD OVER TEMPERATURE (4 MHz)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)
IDD (mA)
-40 °C
25 °C
85 °C
125 °C
3.80
3.85
3.90
3.95
4.00
4.05
4.10
4.15
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FOSC (MHz)
Max (125 °C)
Typ (25 °C)
Min (-40 °C)
PIC16C717/770/771
DS41120C-page 188 1999-2013 Microchip Technology Inc.
FIGURE 16-18 : MAXIMU M IPD VS. V DD (-40°C TO +125°C)
0.01
0.1
1
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
+125°C
+85°C
+25°C -40°C
1999-2013 Microchip Technology Inc. DS41120C-page 189
PIC16C717/770/771
FIGURE 16-19: TYPICAL AND MAXIMUM IWDT VS. V DD (-40°C TO +125°C)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IWDT (A)
Max (-40°C)
Typ (25°C)
PIC16C717/770/771
DS41120C-page 190 1999-2013 Microchip Technology Inc.
FIGURE 16-20: TYPICAL AND MAXIMUM ITMR1 VS. V DD (32 KHZ, -40°C TO +125°C)
FIGURE 16-21: TYPICAL AND MAXIMUM IVRL VS. VDD (- 40 °C TO +125°C)
10.0
30.0
50.0
70.0
90.0
110.0
130.0
150.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ITMR1 (A)
Max (-40°C)
Typ (25°C)
150.0
170.0
190.0
210.0
230.0
250.0
270.0
290.0
310.0
330.0
350.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IVRL (A)
Max (125°C)
Max (85°C)
Typ (25°C)
1999-2013 Microchip Technology Inc. DS41120C-page 191
PIC16C717/770/771
FIGURE 16-22: TYPICAL AND MAXIMUM IVRH VS. VDD (-40°C TO +125°C)
FIGURE 16-23: TYPICAL AND MAXIMUM ILVD VS. VDD (-40°C TO +125°C) (LVD TRIP = 3.0V)
200.0
220.0
240.0
260.0
280.0
300.0
320.0
340.0
360.0
380.0
4.5 5.0 5.5
VDD (V)
IVRH (A)
Max (125°C)
Max (85°C)
Typ (25°C)
30.0
35.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ILVD (A)
Max (125°C)
Max (85°C)
Typ (25°C)
PIC16C717/770/771
DS41120C-page 192 1999-2013 Microchip Technology Inc.
FIGURE 16-24: TYPICAL AND MAXIMUM ILVD VS. VDD (-40°C TO +125°C) (LVD TRIP = 4.5V)
FIGURE 16-25: TYPICAL AND MAXIMUM IBOR VS. VDD (-40°C TO +125°C) (VBOR = 2.5V)
30.0
35.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ILVD (A)
Max (125°C)
Max (85°C)
Typ (25°C)
30.0
40.0
50.0
60.0
70.0
80.0
90.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IBOR (A)
Max (125°C)
Typ (25°C)
Max (125°C)
Typ (25°C)
Device in SleepDevice in Reset Indeterminate
SLEEPRESET
1999-2013 Microchip Technology Inc. DS41120C-page 193
PIC16C717/770/771
FIGURE 16-26: TYPICAL AND MAXIMUM IBOR VS. VDD (-40°C TO +125°C) (VBOR = 4.5V)
FIGURE 16-27 : VOL VS. IOL (-40°C TO +125°C, VDD = 3.0V)
30.0
50.0
70.0
90.0
110.0
130.0
150.0
170.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IBOR (A)
Max (125 °C)
Typ (25 °C)
Max (125 °C)
Typ (25C )
Device in Sleep
Device in Reset Indeterminate
SLEEP
RESET
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0 5.0 10.0 15.0 20.0 25.0
IOL (mA)
VOL (V)
Min (-40°C)
Max (125°C)
Typ (25°C)
PIC16C717/770/771
DS41120C-page 194 1999-2013 Microchip Technology Inc.
FIGURE 16-28 : VOL VS. IOL (-40°C TO +125°C, VDD = 5.0V)
FIGURE 16-29 : VOH VS. IOH (-40 °C TO +125°C, VDD = 3.0 V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 5.0 10.0 15.0 20.0 25.0
IOL (mA)
VOL (V)
Min (-40°C)
Max (125°C)
Typ (25°C)
0.5
1.0
1.5
2.0
2.5
3.0
-16.0-14.0-12.0-10.0-8.0-6.0-4.0-2.00.0
IOH (mA)
VOH (V)
Max (-40°C)
Min (125°C) Typ (25°C)
1999-2013 Microchip Technology Inc. DS41120C-page 195
PIC16C717/770/771
FIGURE 16-30 : VOH VS. IOH (-40 °C TO +125°C, VDD = 5.0V)
FIGURE 16-31: MINIMUM AND MAXIMUM VIH/VIL VS. VDD (TTL INPUT,-40°C TO +125°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-25.0-20.0-15.0-10.0-5.00.0
IOH (mA)
VOH (V)
Max (-40°C)
Min (125°C)
Typ (25°C)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIL / VIH (V)
Min (125°C)
Max (-40°C)
PIC16C717/770/771
DS41120C-page 196 1999-2013 Microchip Technology Inc.
FIGURE 16-32: MINIMUM AND MAXIMUM VIH/VIL VS. VDD (ST INPUT,-40°C TO +125°C)
FIGURE 16-33: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD VS. VDD (-40°C TO +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIL / VIH (V)
Max High (125°C)
Min High (-40°C)
Max Low (-40°C)
Min Low (125°C)
10.0
15.0
20.0
25.0
30.0
35.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
WDT Period ( m S)
Max (125°C)
Typ (25°C)
Max (85°C)
Min (-40°C)
1999-2013 Microchip Technology Inc. DS41120C-page 197
PIC16C717/770/771
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
18-Lead SOIC
XXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXX
YYWWNNN
18-Lead PDIP Example
PIC16C717/P
9917017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXX
YYWWNNN
18-Lead CERDIP Windowed
PIC16C717/JW
Example
9905017
XXXXXXXX
20-Lead PDIP Example
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16C770/P
9917017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXX Example
9910017
PIC16C717/SO
Legend: XX...X Customer-specifi c info rma tio n
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microc hip p art num ber cann ot be marked on one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific infor mation.
3
e
3
e
PIC16C717/770/771
DS41120C-page 198 1999-2013 Microchip Technology Inc.
17.1 Package Marking Information (Cont’d)
YYWWNNN
XXXXXXXXXXX
XXXXXXXXXXX
20-Lead SSOP
9917017
20I/SS
PIC16C770
Example
XXXXXXXX
YYWWNNN
20-Lead CERDIP Windowed
PIC16C770/JW
Example
9905017
XXXXXXXX
20-Lead SOIC
XXXXXXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16C771/SO
9910017
XXXXXXXXXXXXXXXXXXXXXXXX
1999-2013 Microchip Technology Inc. DS41120C-page 199
PIC16C717/770/771
17.2 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 10.929.407.87.430.370.310eBOverall Row Spacing § 0.560.460.36.022.018.014BLower Lea d Width 1.781.461.14.070.058.045B1Upper Lea d Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 22.9922.8022.61.905.898.890DOverall Length 6.606.356.10.260.250.240E1Molded Package Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.38.015
A1
Base to Seating Plane 3.683.302.92.145.130.115A2Molded Package Thickness 4.323.943.56.170.155.140ATop to Seating Plane 2.54
.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
2
D
n
E1
c
eB
E
p
A2
L
B1
B
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per si de.
JEDEC Equivalent: MS-001
Drawing No. C04-007
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC16C717/770/771
DS41120C-page 200 1999-2013 Microchip Technology Inc.
17.3 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
3.30 3.56 3.81
5.335.084.83.210.200.190W2Window Length .150.140.130W1Window Width 10.809.788.76.425.385.345eBOverall Row Spacing 0.530.470.41.021.019.016BLower Lead Width 1.521.401.27.060.055.050B1Upper Lead Width 0.300.250.20.012.010.008
c
Lead Thickness 3.813.493.18.150.138.125LTip to Seating Plane 23.3722.8622.35.920.900.880DOvera ll Length 7.497.377.24.295.290.285E1Ceramic Pkg. Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.760.570.38.030.023.015A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 4.954.644.32.195.183.170A
Top to Seating Plane 2.54.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
1
2
D
n
W2
E1
W1
c
eB
E
p
L
A2
B
B1
A
A1
*Controlling Parameter
JEDEC Equivalent: MO-036
Drawing No. C04-010
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
1999-2013 Microchip Technology Inc. DS41120C-page 201
PIC16C717/770/771
17.4 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot A ngle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.300.270.23.012.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 11.7311.5311.33.462.454.446DOverall Length 7.597.497.39.299.295.291E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 1818
n
Numb er of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
L
c
h
45
1
2
D
p
n
B
E1
E
A2
A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
§ Significant Characteristic
Note: For the most cu rr e nt pac ka ge dr aw i ngs, p le ase se e t he Mi c ro c hi p Pa ck ag ing Specifica t i on lo ca t ed
at http://www.microchip.com/pac kaging
PIC16C717/770/771
DS41120C-page 202 1999-2013 Microchip Technology Inc.
17.5 20-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 10.929.407.87.430.370.310
eB
Overall Row Spacing § 0.560.460.36.022.018.014BLower Lead Width 1.651.521.40.065.060.055
B1
Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.563.303.05.140.130.120LTip to Seating Plane 26.4226.2426.041.0401.0331.025DOverall Length 6.606.356.10.260.250.240E1Molded Package Width 8.267.877.49.325.310.295EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded Package Thickness 4.323.943.56.170.155.140ATop to Seating Plane 2.54
.100
p
Pitch 2020
n
Numb er of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
2
D
n
E1
c
eB
E
p
A2
L
B1
B
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-019
§ Significa nt Char acte risti c
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchi p.c om/p a ck agi ng
1999-2013 Microchip Technology Inc. DS41120C-page 203
PIC16C717/770/771
17.6 20-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
DRAWING NOT AVAILABLE
PIC16C717/770/771
DS41120C-page 204 1999-2013 Microchip Technology Inc.
17.7 20-Lead Plastic Small Outline (SO) – Wide, 300 mi (SOIC)
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-094
Foot Angle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 13.0012.8012.60.512.504.496DOvera ll Length 7.597.497.39.299.295.291E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded P ackage Thick ness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2020
n
Number of Pins MAXNOMMINMAXNOMMINDim en si on Limits MILLIMETERSINCHES*Units
h
L
c
45
1
2
D
p
n
B
E
E1
A2
A
A1
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchi p.c om/p a ck agi ng
1999-2013 Microchip Technology Inc. DS41120C-page 205
PIC16C717/770/771
17.8 20-Lead Plastic Shrink Small Outl ine (SS) – 209 mil, 5.30 mm (SSOP)
10501050
Mold Draft Angle Bottom 10501050
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
Foot Angle 0.250.180.10.010.007.004
c
Lead Thic kness 0.940.750.56.037.030.022LFo ot Len gth 7.347.207.06.289.284.278DOverall Length 5.385.255.11.212.207.201E1Molded Package Width 8.187.857.59.322.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 20
20
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC16C717/770/771
DS41120C-page 206 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 207
PIC16C717/770/771
APPENDIX A: REVISION HISTORY
Version Date Revision Desc ri ption
A 09 /14 /99 This is a new d at a sheet. Ho wev er, the device s de sc rib ed in this data sheet a r e
the upgrades to the devices found in the PIC16C7X Data Sheet, DS30390E.
B1/22/02 Electrical Ch ara cte ris tic s tables comp le ted and characteristic s grap hs add ed.
MSSP I2C (Section 9.2) rew rit ten. General minor changes and correctio ns .
C 1/28/13 Added a note to each package outline drawing.
PIC16C717/770/771
DS41120C-page 208 1999-2013 Microchip Technology Inc.
APPENDIX B: DEVICE
DIFFERENCES
The differences bet we en the de vi ces in th is data sheet
are listed in Ta bl e B - 1 .
TABLE B-1: DEVICE DIFFERENCES
Difference PIC16C717 PIC16C770 PIC16C771
Program Memory 2K 2K 4K
A/D 6 channels, 10 bits 6 channels, 12 bits 6 channels, 12 bits
Dedicated AVDD
and AVSS Not available Available Available
Package s 18-pin PDIP, 18-pin wind owed
CERDIP, 18-pin SOIC,
20-pin SSOP
20-pin PDIP, 20-pin
windowed CERDIP, 20-pin
SOIC, 20-pin SSOP
20-pin PDIP, 20-pin windowed
CERDIP, 20-pin SOIC,
20-pin SSOP
1999-2013 Microchip Technology Inc. DS41120C-page 209
PIC16C717/770/771
INDEX
A
A/D....................................................................................105
A/D Converter Enable (ADIE Bit)................................17
ADCON0 Register.....................................................105
ADCON1 Register .............................................105, 107
ADRES Register.......................................................105
Block Diag ram............................ ........ .......................109
Configuring Analog Port............................................108
Conversi o n time.............. ............... ........ ...................115
Conversions..............................................................111
converter characteristics...................164, 165, 166, 170
Faster Conversion - Lower Resolution Tradeoff.......115
Internal Sampling Switch (Rss) Impedence... ...........113
Operation During Sleep ............................................116
Sampling Requirements........................... .. ....... .... .. ..113
Sampli n g Time...................... ......... ...........................113
Source Impedance............ .... ........... .... ...... ........... ....113
Special Event Trigger (ECCP)....................................55
A/D Convers i o n Clock....... ........ ......... ....................... ........110
ACK.....................................................................................77
Acknowledge Data bit, AKD. ...............................................69
Acknowledge Sequence Enable bit, AKE ...........................69
Acknowledge Status bit, AKS .............................................69
ACKSTAT ...........................................................................87
ADCON0 Register.............................................................105
ADCON1 Register.....................................................105, 107
ADRES..............................................................................105
ADRES Register . ..........................................11, 12, 105, 116
AKD.....................................................................................69
AKE.....................................................................................69
AKS.....................................................................................69
Analog-to-Digital Converter. See A/D
Application Note AN578, "Use of the SSP Module
in the I2C Multi-Master Environment." .............................84
Architecture
PIC16C717/PIC16C717 Block Diagram . ......................5
PIC16C770/771/PIC16C770/771 Block Diagram .........6
Assembler
MPASM Assembler...................................................141
B
Banking, Data Memory ...................................................9, 14
Baud Rate Generator..........................................................84
BF .....................................................................66 , 77, 87, 89
Block Diagrams
Baud Rate Generator..................................................84
I2C Master Mode.........................................................83
I2C Module..................................................................76
RA3:RA0 and RA5 Port Pins . ...................26, 28, 29, 35
SSP (I2C Mode)..........................................................76
SSP (SPI Mode)........................ .......... ........... .............70
BOR. See Brown-out Reset
BRG .................................................................................... 84
Brown-out Reset (BOR)....................................117, 123, 124
Buffe r Full bit, BF................................. ............................. ..77
Buffe r Full Status bit, BF............. ......... ............................. ..66
Bus Arbitration ..... ......... .............. ......... .............. .................94
Bus Collision During a RESTART Condition................. .. ....97
Bus Collision During a Start Condition........... .. .... ....... .. .. ....95
Bus Collision During a Stop Condition................................98
Bus Collision Section ................ ......... ........ ....................... ..94
C
Capture (ECCP Module)............................ .. ....... .. .. .... .. .. .. .. 54
Block Diag ram...... ............... ........ ........ ............... ........ 54
CCP R 1 H :C CPR1 L R eg i s t e r s ........... .. ..... .. ...... ...... .. ... 54
Changing Between Capture Prescalers ..................... 54
ECCP Pin Configuration............................................. 54
Software Interrupt....................................................... 54
Timer1 Mode Selection ............................................... 54
Capture/Compare/PWM (ECCP)
Capture Mode. See Capture
Compare Mode. See Compare
PWM Mode. See PW M
CCP1CON.......................................................................... 13
CCP2CON.......................................................................... 13
CCPR1H Register......................................................... 11, 13
CCPR1L Register............................................................... 13
CCPR2H Register............................................................... 13
CCPR2L Register............................................................... 13
CKE .................................................................................... 66
CKP .................................................................................... 67
Clock Polarity Select bit, CKP............................................. 67
Code Examples
Loading the SSPBUF register .................................... 71
Code Protection........................................................ 117, 131
Compare (ECCP Module)................................. .... .. .. .... .. .. .. 54
Block Diag ram...... ............... ........ ........ ............... ........ 55
CCP R 1 H :C CPR1 L R eg i s t e r s ........... .. ..... .. ...... ...... .. ... 54
ECCP Pin Configuration............................................. 54
Software Interrupt....................................................... 55
Special Event Trigger........................................... 49, 55
Timer1 Mode Selection ............................................... 54
Configurati o n Bi ts ........ ...... ...... ..... .. ...... ...... ..... ...... ...... ..... 117
D
D/A...................................................................................... 66
Data Memor y.............. ............... ........ ........ ............... ........ .... 9
Bank Select (RP Bits)............................................. 9, 14
General Pu rpose Registers .................... ........ ........ ...... 9
Register File Map ....... ......... ........ ........ ......... .............. 10
Spec i a l Func t io n R e g i sters......... ...... ..... ...... ...... ......... 11
Data/Address bit, D/A......................................................... 66
DC Characteristics
PIC16C717/770/771................................. 150, 151, 153
Development Support....................................................... 141
Device Differences............................................................ 208
Direct Addressing ............................................................... 23
E
Enhanced Capture/Compare/PWM (ECCP)
CCP1
CCPR1H Register .............................................. 53
CCPR1L Register............................................... 53
Enable (CCP1IE Bit)........................................... 17
Time r R e so u r ces . ...... .. ..... ...... ...... ...... ..... ...... ...... ...... . 54
Errata.................................................................................... 3
External Power-on Reset Circuit....................................... 122
F
Firm w a r e Instructi o n s ........ .. ..... ...... ...... ...... ..... ...... ...... ..... 133
FSR Register.......................................................... 11, 12, 13
G
GCE.................................................................................... 69
General Call Address Sequence ........................................ 82
General Call Address Support............................................ 82
General Call Enable bit, GCE............................................. 69
PIC16C717/770/771
DS41120C-page 210 1999-2013 Microchip Technology Inc.
I
I/O Ports............. .............. .............................. .............. .......25
I2C.......................................................................................76
I2C Master Mode Reception................................................89
I2C Master Mode Restart Condition....................................86
I2C Mode Selection.............................................................76
I2C Module
Acknowledge Sequence timing...................................91
Addressing..................................................................77
Baud Rate Generator..................................................84
Block Diag ram............................................ ........ .........83
BRG Block Diagram....................................................84
BRG Reset due to SDA Collision................................96
BRG Timing ................................................................85
Bus Arbitration ..... ......... .............. ......... .............. .........94
Bus Collision................. ........ ........ ......... ........ ......... ....94
Acknowledge.......................................................94
Restart Condition................................. ...... .........97
Restart Condition Timing (Case1).......................97
Restart Condition Timing (Case2).......................97
Start Condition......................................... ...........95
Start Condition Timing ..................................95, 96
Stop Condition ............ ........ ................................98
Stop Condition Timing (Case1)...........................98
Stop Condition Timing (Case2)...........................98
Transmit Timing...... ........ ............... ........ .............94
Bus Collision timing....... ........ ........ ................. ......... ....94
Clock Arbitration..........................................................93
Clock Arbi tration Timing (M aster Transmit)............... ..93
Conditions to not give ACK Pulse...............................77
General Call Address Support ....................................82
Master Mode...............................................................83
Master Mode 7-bit Receptio n ti ming ........ ........ ...........90
Master Mode Operation ..............................................84
Master Mode Start Condi tio n...... .............................. ..85
Master Mode Transmission.........................................87
Master Mode Transmit Sequence...............................84
Multi-Master Communication......................................94
Multi-master Mode ......................................................84
Operation ....................................................................76
Repeat Start Condition timing.....................................86
Slave Mode.................................................................76
Slave Reception..........................................................78
Slave Transmission.....................................................80
SSPBUF......................................................................76
Stop Condition Receive or Transmit timing.................92
Stop Condition timing...... ........ ....................................92
Wavefor ms for 7-bit Recep tion . ..................................78
Wavefor ms for 7-bit Trans mission ............... ...............80
I2C Slave Mode...................................................................76
ICEPIC In -Circuit Emulator ............... ......... .............. .........142
ID Locations..............................................................117, 131
In-Circuit Serial Programming (ICSP) .......................117, 131
INDF....................................................................................13
INDF Register ...............................................................11, 12
Indirect Addressing .............................................................23
FSR Register ................................................................9
Instruction Format.............................................................133
Instruction Set...................................................................133
ADDLW.....................................................................135
ADDWF.....................................................................135
ANDLW.....................................................................135
ANDWF.....................................................................135
BCF...........................................................................135
BSF...........................................................................135
BTFSC ......................................................................136
BTFSS...................................................................... 136
CALL......................................................................... 136
CLRF ........................................................................ 136
CLRW....................................................................... 136
CLRWDT .................................................................. 136
COMF....................................................................... 137
DECF........................................................................ 137
DECFSZ ................................................................... 137
GOTO ....................................................................... 137
INCF ......................................................................... 137
INCFSZ..................................................................... 137
IORLW...................................................................... 138
IORWF...................................................................... 138
MOVF ....................................................................... 138
MOVLW.................................................................... 138
MOVWF.................................................................... 138
NOP.......................................................................... 138
RETFIE..................................................................... 139
RETLW..................................................................... 139
RETURN................................................................... 139
RLF........................................................................... 139
RRF .......................................................................... 139
SLEEP...................................................................... 139
SUBLW..................................................................... 140
SUBWF..................................................................... 140
SWAPF..................................................................... 140
XORLW .................................................................... 140
XORWF .................................................................... 140
Summary Ta b l e........ .............. .............................. .... 134
INT Interru p t (R B0 / IN T). See Interrupt Sources
INTCON.............................................................................. 13
INTCON Register................................................................ 16
GIE Bi t....... ............................. ..................... ............... 16
INTE Bit ... ........ ............... ............... ..................... ........ 16
INTF Bit .................... ............................. ..................... 16
PEIE Bit ................................ ............... ............... ........ 16
RBIE Bit...................................................................... 16
RBIF Bit...................... ........ ............... ................... 16, 33
T0IE Bit....................................................................... 16
T0IF Bit....................................................................... 16
Inter-Integrated Circuit (I2C) ............................................... 65
internal sampling switch (Rss) impedence . ...................... 113
Interrupt Sources...................................................... 117, 127
Block Diag ram ............ ....................... ....................... 127
Capture Complete (ECCP)......................................... 54
Compare Complete (ECCP)....................................... 55
RB0/ INT Pin , Exte r n a l .. ...... ...... . ...... ...... ...... .. ..... ...... . 128
TMR0 Overflow................................................... 46, 128
TMR1 Overflow.....................................................47, 49
TMR2 to PR2 Match................................................... 52
TMR2 to PR 2 M atch (PWM ).. ..... .. ...... ...... ..... ...... . 51, 56
Interrupts
Synchronous Serial Port Interrupt............................... 18
Interrupts, Context Saving During..................................... 128
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit)................................ 17
CCP1 Enable (CCP1IE Bit) ................... .. .. ....... .. ..17, 54
Global Interrupt Enable (GIE Bit)........................ 16, 127
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit).............. .............. ............................ 16, 128
Peripheral Interrupt Enable (PEIE Bit)........................ 16
PSP Read/Write Enable (PSPIE Bit).......................... 17
RB0/INT Enable (INTE Bit)......................................... 16
SSP Enable (SSPIE Bit)............................................. 17
TMR0 Overflow Enable (T0IE Bit) .............................. 16
TMR1 Overflow Enable (TMR1IE Bit)......................... 17
1999-2013 Microchip Technology Inc. DS41120C-page 211
PIC16C717/770/771
TMR2 to PR2 Match Enable (TMR2IE Bit) .................17
USART Receive Enable (RCIE Bit) . .... .. .... ......... ..17, 18
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit).............................................54
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit)..................................................16, 33, 128
RB0/INT Flag (INTF Bit)..............................................16
TMR0 Overflow Flag (T0IF Bit)...........................16, 128
INTRC Mode.....................................................................120
K
KEELOQ Evaluation and Programming Tools....................144
L
LVDCON...........................................................................101
M
Master Clear (MCLR)
MCLR Reset, Normal Operation...............121, 123, 124
MCLR Reset, SLEEP................................121, 123, 124
Memory Organization
Data Memor y .............. ............................. ......... ............9
Program Memory..........................................................9
MPLAB C17 and MPLAB C18 C Compilers......................141
MPLAB ICD In-Circuit Debugger ......................................143
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE............................................142
MPLAB Integrated Development Environment Software..141
MPLINK Object Linker/MPLIB Object Librarian................142
Multi-Master Communication..............................................94
Multi-Master Mode ..............................................................84
O
OPCODE Fiel d Descr ip tions. ........ ......... ........ ...................133
OPTION_R EG Re g i ster.... ............................. ......... ............15
INTEDG Bi t........ ............... ......... .............. ...................15
PS Bits......... .............................. .............. .............15, 45
PSA Bit..................................................................15, 45
RBPU Bit....................... ............................. ......... ........15
T0CS Bit................................................................15, 45
T0SE Bit................................................................15, 45
Oscillator Configuration.....................................................119
CLKOUT ...................................................................120
Dual Speed Operation for ER and
INTRC Modes.......................................................120
EC.....................................................................119, 123
ER.....................................................................119, 123
ER Mode...................................................................120
HS.....................................................................119, 123
INTRC...............................................................119, 123
LP.... ..................................................................119, 123
XT .....................................................................119, 123
Oscillato r, Ti mer1............................... ................ ......... ..47, 49
Oscillat o r, WDT..................... ........ ......... ........ ...................129
P
P..........................................................................................66
Packaging .........................................................................197
Pagin g , Program Memory........... ............... ............... ......9, 22
Parallel Slave Port (PSP)
Read/Write Enable (PSPIE Bit)...................................17
PCL Register .................................................................11, 12
PCLATH Register ...................................................1 1, 12, 13
PCON Register...........................................................21, 123
PICDEM 1 Low Cost PIC MCU
Demonstration Board....................................................143
PICDEM 17 Demonstr a tion Board............................ ........144
PICDEM 2 Low Cost PIC16CXX
Demonstration Board....................................................143
PICDEM 3 Low Cost PIC16CXXX
Demons t r a ti o n Bo a r d. ...... ..... .. ...... ...... ...... ..... .. ...... ...... . 14 4
PICSTA R T Plus En try Level
Development Programmer............................................ 143
PIE1 Register ..................................................................... 17
ADIE Bit...................................................................... 17
CCP1IE Bit ......... ............... .............. ............... ............ 17
PSPIE Bit.................................................................... 17
RCIE Bit................................................................ 17, 18
SSPIE Bit.................................................................... 17
TMR1IE Bit................................................................. 17
TMR2IE Bit................................................................. 17
PIE2 Register ..................................................................... 19
Pinout Descriptions
PIC16C770................................................................... 7
PIC16C770/771............................................................ 7
PIC16C771................................................................... 7
PIR1 Register ..................................................................... 18
PIR2 Register ..................................................................... 20
Pointer, FSR....................................................................... 23
POR. See Power-on Reset
PORTA ............................................................................... 13
Initialization................................................................. 26
PORT A R e g i s t e r...... ...... .. ..... ...... .. ...... .. ..... ...... ...... .. ... 25
TRISA Reg i s ter........ .. ...... ..... ...... ...... .. ..... ...... ...... ...... . 25
PORTA Register......................................................... 11, 116
PORTB ............................................................................... 13
Initialization................................................................. 33
PORT B R e g i s t e r...... ...... .. ..... ...... .. ...... .. ..... ...... ...... .. ... 33
Pull-up Enable (RBPU Bit).... .. ...... .. ...... ..... .. ...... ...... .. . 15
RB0/INT Edge Select (INTEDG Bit) . .......................... 15
RB0/ INT Pin , E xtern a l ..... . ...... .. ...... ...... ..... .. ...... ...... . 128
RB7:RB4 Interrupt on Change.......................... .... .... 128
RB7:RB4 Interrupt on Change Enable
(RBIE Bit).... .............. ............................ .......... 16, 128
RB7:RB4 Interrupt on Change Flag
(RBIF Bit).................................................. 16, 33, 128
TRISB Reg i s ter........ .. ...... ..... ...... ...... .. ..... ...... ...... ...... . 33
PORTB Register......................................................... 11, 116
Postscaler, Timer2
Select (TOUTPS Bits) ................................................. 51
Postscaler, WDT................................................................. 45
Assignment (PSA Bit)........................................... 15, 45
Block Diag ram...... ............... ........ ........ ............... ........ 46
Rate Select (PS Bits )..................... ............... ........ 15, 45
Switching Between Timer0 and WDT....................... .. 46
Power-down Mode. See SLEEP
Power-on Reset (POR)..................... 117, 121, 122, 123, 124
Oscillator Start-up Timer (OST)........................ 117, 122
Power Cont r o l (P C O N ) Re g i s t e r..... .. ..... .. ...... ...... ..... 123
Power-down (PD Bit).................................................. 14
Power-on R e se t Circuit, Extern al ..... .. ..... ...... ...... ..... 122
Power-up Ti mer (P W R T)........ .. ...... ...... ..... .. ..... 117, 1 22
Time-out (T O Bit)........................................................ 14
Time-out Sequence .................................................. 123
Time-out Sequence on Power-up................. .... 125, 126
PR2 Register ...................................................................... 12
Prescaler, Capture.............................................................. 54
Prescaler, Timer0 ............................................................... 45
Assignment (PSA Bit)........................................... 15, 45
Block Diag ram...... ............... ........ ........ ............... ........ 46
Rate Select (PS Bits )..................... ............... ........ 15, 45
Switching Between Timer0 and WDT....................... .. 46
Prescaler, Timer1 ............................................................... 48
Select (T1 C KPS Bits).... .. . ...... .. ...... ...... . ...... .. .. ...... .. .. . 47
PIC16C717/770/771
DS41120C-page 212 1999-2013 Microchip Technology Inc.
Presca le r, Timer2........... ......... ............................................57
Select (T2CKPS Bits)...................... ......... ...................51
PRO MATE II Universal Device Programmer ...................143
Program Counter
PCL Register ...............................................................22
PCLATH Register ...............................................22, 128
Reset Conditions............. ........ ..................................123
Program Memory ..................................................................9
Inter rupt Vector...... ......... .............. ............... ........ .........9
Paging.....................................................................9, 22
Program Memory Map ..................................................9
READ (PMR)........ ............... ........ .............................. ..43
Reset Vec tor ................................... ..............................9
Program Verification..........................................................131
Programmable Brown-out Reset (PBOR).................121, 122
Programming, Device Instructions....................................133
PWM (CCP Module)
TMR2 to PR2 Match ...................................................51
TMR2 to PR2 Match Enable (TMR2IE Bit) .................17
PWM (ECCP Modul e )........................................ ........ .........56
Block Diag ram............................................ ........ .........56
CCPR1H:CCPR1L Registers......................................56
Duty Cycle...................................................................57
Output Dia g ram............. ........ ............................. .........57
Period..........................................................................56
TMR2 to PR2 Match ...................................................56
Q
Q Clock ... .............................. ........ ............................. .........57
R
R/W.....................................................................................66
R/W bit................................................................................80
R/W bit................................................................................78
R/W bit ................................................................................77
RAM. See Data Memory
RCE,Receive Enable bit, RCE........................... .. .... .. ....... ..69
RCREG...............................................................................13
RCSTA Regis te r................. ............................................. ....13
Read/Write bit, R/W ............................................................66
Receive Overflow Indicator bit, SSPOV....... ........ ...............67
REFCON...........................................................................102
Register File............... ............... ........ .............................. ......9
Register File Map..... ........ ...................................................10
Registers
FSR Summary ............................................................13
INDF Summary...........................................................13
INTCON Summary......................................................13
PCL Summary.............................................................13
PCLATH Sum mar y ............. ........ ............... ............... ..13
PORTB Summary .......................................................13
SSPSTAT............................................................66, 101
STATUS Sum mary ................. ............................. .......13
TMR0 Summary..........................................................13
TRISB Summary.........................................................13
Reset.........................................................................117, 121
Block Diag ram............................................ ........ .......121
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCL R
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers ............................124
Rese t Condit i o n s for PC O N R e g i s t e r.. .. ...... ...... .. ..... .12 3
Reset Conditions for Program Counter.....................123
Rese t Condit i o n s fo r ST ATUS Reg is te r...... .. ...... ..... .123
WDT Reset. See Watchdog Timer (WDT)
Restart Condition Enabled bit, RSE....................................69
Revision History................................................................207
RSE.....................................................................................69
S
S ......................................................................................... 66
SAE..................................................................................... 69
SCK .................................................................................... 70
SCL..................................................................................... 76
SDA .................................................................................... 76
SDI...................................................................................... 70
SDO.................................................................................... 70
Serial Data In, SDI.............................................................. 70
Serial Data Out, SDO ......................................................... 70
Slave Select Synchron i zation...................... ........ ............... 73
Slave Select, SS................................................................. 70
SLEEP .............................................................. 117, 121, 130
SMP.................................................................................... 66
Software Simulator (MPLAB SIM) .................................... 142
SPE..................................................................................... 69
Special Event Trigger. See Com pare
Special Features of the CPU............................................ 117
Special Function Registers................................................. 11
PIC16C717................................................................. 11
PIC16C717/770/771................................................... 11
PIC16C770................................................................. 11
PIC16C771................................................................. 11
Speed, Operating.................................................................. 1
SPI Master Mode............................................................... 72
Serial Clock................................................................. 70
Serial Data In.............................................................. 70
Serial Data Out...........................................................70
Serial Peripheral Interface (SPI)................................. 65
Slave Select.............. .............. ......... ............... ............ 70
SPI cl o ck. .. ...... ..... ...... .. ...... ...... ..... .. ...... ...... ..... ...... .. ... 7 2
SPI Mo d e...... .. ..... ...... ...... .. ...... ..... ...... .. ...... ..... ...... ..... 70
SPI Clock Edge Select, CKE .................... .......................... 66
SPI Data Input Sample Phase Select, SMP....................... 66
SPI Master/Slave Connection............................................. 71
SPI Module
Master/Slave Connection............................................ 71
Slave Mode...... ......... .............. .............................. ...... 73
Slave Select Synchron i zation.... ........ ......................... 73
Slave Synch Timnig.. .............. ......... ........ ......... .......... 73
SS....................................................................................... 70
SSP..................................................................................... 65
Block Diagram (SPI Mode)....... .................................. 70
Enable (SSPIE Bit) ..................................................... 17
SPI Mo d e...... .. ..... ...... ...... .. ...... ..... ...... .. ...... ..... ...... ..... 70
SSPADD..................................................................... 77
SSPBUF............................................................... 72, 76
SSPCON .................................................................... 67
SSPCON2 ............................................................ 69, 70
SSPS R ... ...... ...... . ...... .. ...... ...... . ...... ...... .. ...... ..... .. . 72, 77
SSPS TAT ......... ..... .. ...... .. ...... ..... .. ...... ...... .. .. 66, 76 , 1 0 1
TMR2 Outpu t fo r C l o ck Shi ft..... ...... ...... ...... .. ..... ... 5 1 , 5 2
SSP I2C
SSP I2C Operation ....... ........ ......... ........ ......... ........ .... 76
SSP Module
SPI Master Mode........................................................ 72
SPI Master./Slave Connection.................................... 71
SPI Slave Mode.......................................................... 73
SSPCON1 Register.................................................... 76
SSP Overflow Detect bit, SS POV.............. ........ ......... ........ 77
SSPADD Regist e r.... ....................... ......... ........ ......... .......... 12
SSPBUF ................................................................. 13, 76, 77
SSPBUF Register............................................................... 11
SSPCON............................................................................. 67
SSPCON Register.............................................................. 11
1999-2013 Microchip Technology Inc. DS41120C-page 213
PIC16C717/770/771
SSPCON1...........................................................................76
SSPCON2.....................................................................69, 70
SSPEN................................................................................67
SSPIF............................................................................18, 78
SSPM..................................................................................68
SSPOV ....................................................................67, 77, 89
SSPSTAT..............................................................66, 76, 101
SSPSTAT Register.............................................................12
Stack...................................................................................22
Start bi t (S)............... ......... .............. ......... ............... ............66
Start Condition Enabled bit, SAE........................................69
STATUS Register .................................................14, 15, 128
C Bit.................................. ......... .............. ......... ..........14
DC Bit....................................................................14, 15
IRP Bit................................. ............... ............... ..........14
PD Bit..........................................................................14
RP Bits........................................................................14
TO Bit..........................................................................14
Z Bit.............................................................................14
Statu s Reg i ster ....................... ........ ............... ......... ............14
Stop bi t ( P)........... ............... ........ ............... .........................66
Stop Condition Enable bit ............... ......... .. .. .... .. ......... .. .. ....69
Synchronous Serial Port .....................................................65
Synchronous Serial Port Enable bit, SSPEN......................67
Synchronous Serial Port Interrupt.......................................18
Synchronous Serial Port Mode Select bits, SSPM .............68
T
T1CON................................................................................13
T1CON Regis te r .... .............................. ........ .................13, 47
T1CKPS Bits...............................................................47
T1OSCEN Bit..............................................................47
T1SYNC Bit...... ............... ............... .............................47
TMR1CS Bi t. ............... ........ ............... .........................47
TMR1ON Bit................................................................47
T2CON Regis te r .... .............................. ........ .................13, 51
T2CKPS Bits...............................................................51
TMR2ON Bit................................................................51
TOUTPS Bits ..............................................................51
Timer0
Block Diag ram............................ ........ .........................45
Clock Source Edge Select (T0SE Bit) . ..................15, 45
Cloc k So u rce Se l ec t (T 0 C S Bit)...... .. ...... .. ..... ...... .15, 45
Overflow Enable (T0IE Bit) .........................................16
Overflow Flag (T0IF Bit)............. .............. ......... ..16, 128
Overflow Interrupt ..... ............................. .............46, 128
Prescaler. See Prescaler, Time r0
Timer1.................................................................................47
Block Diag ram............................ ........ .........................48
Capacitor Selection... .... ...... .... ............. .... ............. .... ..49
Clock Source Select (TMR1CS Bit)............................47
External Clock Input Sync (T1S YNC Bit)....................47
Module On/Off (TMR1ON Bit).....................................47
Oscillator...............................................................47, 49
Oscillator Enable (T1OSCEN Bit)...............................47
Overflow Enable (TMR1IE Bit)....................................17
Overflow Interrupt ..... ............................. ...............47, 49
Prescaler. See Prescaler, Time r1
Special Event Trigger (ECCP)..............................49, 55
T1CON Regis te r ............... .............................. ........ ....47
TMR1H Register.........................................................47
TMR1L Register..........................................................47
Timer2
Block Diag ram...... ............... ........ ........ ............... ........ 52
Postscaler. See Postscaler, Timer2
PR2 Register........................................................ 51, 56
Prescaler. See Prescaler, Timer2
SSP Cl o ck Sh i f t . ...... .. ...... . ...... .. ...... .. ..... .. ...... .. ..... 51, 5 2
T2CON Register......................................................... 51
TMR2 R e g i s t e r ...... ...... ..... ...... ...... ...... ..... ...... ...... ...... . 51
TMR2 to PR 2 Match En a ble (TMR2 I E Bi t ).. .. ...... .. ..... 17
TMR2 to PR2 Match Interrupt......................... 51, 52, 56
Timing Diagrams
Acknowledge Sequence Timing ................................. 91
Baud Rate Generator with Clock Arbitration............... 85
BRG Reset Due to SDA Collision........ ................. ...... 96
Brown-o u t Re set..... ........ ......... ................................. 159
Bus Collision
Start Condition Timing.......................... ...... ...... .. 95
Bus Collision During a Restart Condition
(Case 1)...... ........ ............... ............................. ........ 97
Bus Collision During a Restart Condition
(Case2)....... ........ ............... ............................. ........ 97
Bus Collision During a Start Condition
(SCL = 0)........ ........ ....................... ......................... 96
Bus Collision During a Stop Condition........................ 98
Bus Collision for Transmit and Acknowledge ............. 94
Capture/Compare/PWM ........................................... 161
CLKOUT and I/O...................................................... 157
Exter n a l C l o ck T iming...... ..... ...... .. ...... ..... .. ...... ...... ... 157
I2C Bus Data........ .. ...... ..... ...... ...... ...... .. ..... ...... ...... ... 177
I2C Master Mode First Start bit timi ng ........................ 85
I2C Master Mode Reception timing............................. 90
I2C Master Mode Transmission timing ....................... 88
Master Mode Transmit Clock Arbitration .................... 93
Power-up Ti mer..... ...... ..... ...... .. ...... ...... ..... .. ...... ...... . 15 9
Repeat Start Condition ............................... .. .... .. .... .. .. 86
Reset........................................................................ 159
Slave Synchronization................................................ 73
Start- u p Timer........... ......... ............................. ........ .. 159
Stop Condition Receive or Transmit........................... 92
Time-out Sequence on Power-up................. .... 125, 126
Timer0 ...................................................................... 160
Timer1 ...................................................................... 160
Wake-up from SLEEP via Interrupt .......................... 131
Watchdog Timer ........................................... .. .... .... .. 159
TMR0.................................................................................. 13
TMR0 Register.................................................................... 11
TMR1H ............................................................................... 13
TMR1H Register................................................................. 11
TMR1L................................................................................ 13
TMR1L Register.................................................................. 11
TMR2.................................................................................. 13
TMR2 Register.................................................................... 11
TRISA Register........................................................... 12, 116
TRISB Register........................................................... 12, 116
TXREG ............................................................................... 13
U
Update Address, UA......... .... .. ......... .... .. .... ......... .. .... .... .. .... 66
USART
Receive Enable (RCIE Bit)................................... 17, 18
PIC16C717/770/771
DS41120C-page 214 1999-2013 Microchip Technology Inc.
W
W Register ..................... ......... .............. ............................128
Wake-up from SLEEP...............................................117, 130
Interrupts...........................................................123, 124
MCLR Reset ................. .............. ......... .....................124
Timing Dia g ram........ ............... ........ ..........................131
WDT Reset .................................................. ........ .....124
Watchdog Timer (WDT)...................... .... ......... .... .. ...117, 129
Block Diag ram............................................ ........ .......129
Enable (WDTE Bit)....... .............................................129
Postscaler. See Postscaler, WDT
Programming Considerations . ........ ......... ........ .........129
RC Oscillator.............................................................129
Time-o ut Period .................... ............... .............. .......129
WDT Reset, Normal Operation.................121, 123, 124
WDT Reset, SLEEP..........................................123, 124
Waveform for General Call Address Seque nce ..................82
WCOL .................. ........ ............... ........ ..67 , 8 5 , 8 7, 89, 91, 92
WCOL Statu s Flag....... .............................. .............. ......... ..85
Write Collision Detect bit, WCOL........................................67
WWW, On-Line Support ........................................................3
1999-2013 Microchip Technology Inc. DS41120C-page 215
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchi p con sul tant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of sem inars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local S ales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is avail able throug h the web si te
at: http://microchip.com/support
DS41120C-page 216 1999-2013 Mic rochip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS41120C
1. What are the best f eatures of thi s document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1999-2013 Microchip Technology Inc. DS41120C-page 217
PIC16C717/770/771
PIC16C717/770/771 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
* JW Devices are UV er asable and can be programm ed to any device configurat ion. JW Devices meet the electr ical requirement of
each oscillator type.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC16C771 : VDD range 4.0V to 5.5V
PIC16C771T : VDD range 4.0V to 5.5V (Tape/Reel)
PIC16LC771 : VDD range 2.5V to 5.5V
PIC16LC771T: VDD range 2.5V to 5.5V (Tape/Reel)
Temper atu re Rang e: -=0C to +70C
I=-40C to +85C
E=-40C to +125C
Package JW = Windowed CERDIP
SO = SOIC
P=PDIP
SS = SSOP
Pattern QTP, SQTP, Code or Special Requirements. Blank for OTP
and Windowed devices.
Examples:
a) PIC16C771/P Commercial Temp.,
PDIP package, normal VDD limits
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
PIC16C717/770/771
DS41120C-page 218 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 219
PIC16C717/770/771
NOTES:
PIC16C717/770/771
DS41120C-page 220 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 221
PIC16C717/770/771
NOTES:
PIC16C717/770/771
DS41120C-page 222 1999-2013 Microchip Technology Inc.
1999-2013 Microchip Technology Inc. DS41120C-page 223
Information contained in this publication regarding device
applications a nd the like is p ro vid ed only f or yo ur c onvenien ce
and may be supers eded by u pdates. I t is y o u r r es ponsibil i ty to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Em bedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Stor age Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In- Circuit Serial
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germ any II Gm bH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1999-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769713
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsP IC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS41120C-page 224 1999-2013 Mic rochip Technology Inc.
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11/29/12
