General Description
The MAX19538 is a 3.3V, 12-bit, 95Msps analog-to-digi-
tal converter (ADC) featuring a fully differential wide-
band track-and-hold (T/H) input amplifier, driving a
low-noise internal quantizer. The analog input accepts
single-ended or differential signals. The MAX19538 is
optimized for low power, small size, and high dynamic
performance. Excellent dynamic performance is main-
tained from baseband to input frequencies of 175MHz
and beyond, making the MAX19538 ideal for intermedi-
ate frequency (IF) sampling applications.
Powered from a single 3.3V supply, the MAX19538 con-
sumes only 492mW while delivering a typical 68.4dB
signal-to-noise ratio (SNR) performance at a 175MHz
input frequency. In addition to low operating power, the
MAX19538 features a 63µW power-down mode to con-
serve power during idle periods.
A flexible reference structure allows the MAX19538 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.10V. The MAX19538 provides a com-
mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX19538 supports either a single-ended or differ-
ential input clock drive. The internal clock duty-cycle
equalizer accepts a wide range of clock duty cycles.
Analog-to-digital conversion results are available
through a 12-bit, parallel, CMOS-compatible output bus.
The digital output format is pin selectable to be either
two’s complement or Gray code. A data-valid indicator
eliminates external components that are normally
required for reliable digital interfacing. A separate digital
power input accepts a wide 1.7V to 3.6V supply allow-
ing the MAX19538 to interface with various logic levels.
The MAX19538 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the Pin-Compatible Versions table for a complete
family of 14-bit and 12-bit high-speed ADCs.
Applications
IF and Baseband Communication Receivers
Cellular, Point-to-Point Microwave, HFC
Medical Imaging Including Positron
Emission Tomography (PET)
Video Imaging
Portable Instrumentation
Low-Power Data Acquisition
Features
♦Direct IF Sampling Up to 400MHz
♦Excellent Dynamic Performance
70.9dB/68.4dB SNR at fIN = 3MHz/175MHz
89.0dBc/76.2dBc SFDR at fIN = 3MHz/175MHz
-71.5dBFS Small-Signal Noise Floor
♦3.3V Low-Power Operation
465mW (Single-Ended Clock Mode)
492mW (Differential Clock Mode)
63µW (Power-Down Mode)
♦Fully Differential or Single-Ended Analog Input
♦Adjustable Full-Scale Analog Input Range: ±0.35V
to ±1.10V
♦Common-Mode Reference
♦CMOS-Compatible Outputs in Two’s Complement
or Gray Code
♦Data-Valid Indicator Simplifies Digital Design
♦Data Out-of-Range Indicator
♦Miniature 6mm x 6mm x 0.8mm 40-Pin Thin QFN
Package with Exposed Paddle
♦Evaluation Kit Available (Order MAX1211EVKIT)
MAX19538
12-Bit, 95Msps, 3.3V ADC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3403; Rev 0; 10/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
+Denotes lead-free package.
*All devices are specified over the -40°C to +85°C operating
range.
EVALUATION KIT
AVAILABLE
PART* PIN-PACKAGE PKG CODE
MAX19538ETL 40 Thin QFN T4066-3
MAX19538ETL+ 40 Thin QFN T4066-3
PART
SAMPLING
RATE
(Msps)
RESOLUTION
(BITS)
TARGET
APPLICATION
MAX12555 95 14 IF/Baseband
MAX12554 80 14 IF/Baseband
MAX12553 65 14 IF/Baseband
MAX19538 95 12 IF/Baseband
MAX1209 80 12 IF
MAX1211 65 12 IF
MAX1208 80 12 Baseband
MAX1207 65 12 Baseband
MAX1206 40 12 Baseband
Pin-Compatible Versions
MAX19538
12-Bit, 95Msps, 3.3V ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND...........................................................-0.3V to +3.6V
OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V
INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN,
COM to GND.....-0.3V to the lower of (VDD + 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G / T, DCE,
PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V
D11–D0, I.C., DAV,
DOR to GND........................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated
26.3mW/°C above +70°C) ......................................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 2)
Resolution 12 Bits
Integral Nonlinearity INL fIN = 3MHz -1.7 ±0.4 +1.4 LSB
Differential Nonlinearity DNL fIN
= 3M H z, no m i ssi ng codes over tem per atur e -0.55 ±0.30 +0.95 LSB
Offset Error VREFIN = 2.048V ±0.10 ±0.58 %FS
Gain Error VREFIN = 2.048V ±0.6 ±4.9 %FS
ANALOG INPUT (INP, INN)
Differential Input Voltage Range VDIFF Differential or single-ended inputs ±1.024 V
Common-Mode Input Voltage VDD / 2 V
CPAR Fixed capacitance to ground 2
Input Capacitance
(Figure 3) CSAMPLE Switched capacitance 4.5 pF
CONVERSION RATE
Maximum Clock Frequency fCLK 95 MHz
Minimum Clock Frequency 5 MHz
Data Latency Figure 6 8.5 Clock
cycles
DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)
Small-Signal Noise Floor SSNF Input at less than -35dBFS -71.5 dBFS
fIN = 3MHz at -0.5dBFS (Note 3) 67.2 70.9
fIN = 70MHz at -0.5dBFS 70.4
Signal-to-Noise Ratio SNR
fIN = 175MHz at -0.5dBFS (Note 3) 65.5 68.4
dB
fIN = 3MHz at -0.5dBFS (Note 3) 66.5 70.8
fIN = 70MHz at -0.5dBFS 70.0
Signal-to-Noise and Distortion SINAD
fIN = 175MHz at -0.5dBFS (Note 3) 63.3 67.5
dB
MAX19538
12-Bit, 95Msps, 3.3V ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 3MHz at -0.5dBFS (Note 3) 73.5 89.0
fIN = 70MHz at -0.5dBFS 83.5
Spurious-Free Dynamic Range SFDR
fIN = 175MHz at -0.5dBFS (Note 3) 67.2 76.2
dBc
fIN = 3MHz at -0.5dBFS (Note 3) -86.3 -72.9
fIN = 70MHz at -0.5dBFS -81.2Total Harmonic Distortion THD
fIN = 175MHz at -0.5dBFS (Note 3) -74.7 -66.2
dBc
fIN = 3MHz at -0.5dBFS -92.4
fIN = 70MHz at -0.5dBFS -91.3
Second Harmonic HD2
fIN = 175MHz at -0.5dBFS -82.3
dBc
fIN = 3MHz at -0.5dBFS -89.6
fIN = 70MHz at -0.5dBFS -83.7Third Harmonic HD3
fIN = 175MHz at -0.5dBFS -76.2
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS -82.5
Intermodulation Distortion IMD
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS -73.6
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS -84.3
Third-Order Intermodulation IM3
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS -76.0
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS 84.7
Two-Tone Spurious Free
Dynamic Range SFDRTT fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS 75.6
dBc
Aperture Delay tAD Figure 4 1.2 ns
Aperture Jitter tAJ Figure 4 <0.2 psRMS
Output Noise nOUT INP = INN = COM 0.36 LSBRMS
Overdrive Recovery Time ±10% beyond full scale 1 Clock
cycles
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)
REFOUT Output Voltage VREFOUT 1.996 2.048 2.063 V
COM Output Voltage VCOM VDD / 2 1.65 V
Differential-Reference Output
Voltage VREF VREF = VREFP - VREFN = VREFIN x 3/4 1.536 V
REFOUT Load Regulation -1.0mA < IREFOUT < 0.1mA 35 mV/mA
REFOUT Temperature Coefficient TCREF +50 ppm/°C
Short to VDD, sinking 0.24
REFOUT Short-Circuit Current Short to GND, sourcing 2.1 mA
MAX19538
12-Bit, 95Msps, 3.3V ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated
internally)
REFIN Input Voltage VREFIN 2.048 V
REFP Output Voltage VREFP (VDD / 2) + (VREFIN x 3/8) 2.418 V
REFN Output Voltage VREFN (VDD / 2) - (VREFIN x 3/8) 0.882 V
COM Output Voltage VCOM VDD / 2 1.60 1.65 1.70 V
Differential-Reference Output
Voltage VREF VREF = VREFP - VREFN = VREFIN x 3/4 1.462 1.536 1.594 V
Differential-Reference
Temperature Coefficient ±25 ppm/°C
REFIN Input Resistance >50 MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally)
COM Input Voltage VCOM VDD / 2 1.65 V
REFP Input Voltage VREFP - VCOM +0.768 V
REFN Input Voltage VREFN - VCOM -0.768 V
D i ffer enti al - Refer ence Inp ut V ol tag eV
REF VREF = VREFP - VREFN = VREFIN x 3/4 1.536 V
REFP Sink Current IREFP VREFP = 2.418V 1.4 mA
REFN Source Current IREFN VREFN = 0.882V 1.0 mA
COM Sink Current ICOM VCOM = 1.65V 1.0 mA
REFP, REFN Capacitance 13 pF
COM Capacitance 6pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended-Input High
Threshold VIH CLKTYP = GND, CLKN = GND 0.8 x
VDD V
Single-Ended-Input Low
Threshold VIL CLKTYP = GND, CLKN = GND 0.2 x
VDD V
Differential Input Voltage Swing CLKTYP = high 1.4 VP-P
Differential Input Common-Mode
Voltage CLKTYP = high VDD / 2 V
Input Resistance RCLK Figure 5 5 kΩ
Input Capacitance CCLK 2pF
DIGITAL INPUTS (CLKTYP, DCE, G / TT
TT , PD)
Input High Threshold VIH 0.8 x
OVDD V
Input Low Threshold VIL 0.2 x
OVDD V
VIH = OVDD ±5
Input Leakage Current VIL = 0 ±5µA
Input Capacitance CDIN 5pF
MAX19538
12-Bit, 95Msps, 3.3V ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUTS (D11–D0, DAV, DOR)
D11–D0, DOR, ISINK = 200µA 0.2
Output-Voltage Low VOL DAV, ISINK = 600µA 0.2 V
D11–D0, DOR, ISOURCE = 200µA OVDD -
0.2
Output-Voltage High VOH
DAV, ISOURCE = 600µA OVDD -
0.2
V
Tri-State Leakage Current ILEAK (Note 4) ±5 µA
D11–D0, DOR Tri-State Output
Capacitance COUT (Note 4) 3 pF
DAV Tri-State Output
Capacitance CDAV (Note 4) 6 pF
POWER REQUIREMENTS
Analog Supply Voltage VDD 3.15 3.30 3.60 V
Digital Output Supply Voltage OVDD 1.7 1.8 VDD +
0.3V V
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = GND,
single-ended clock
141
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = OVDD,
differential clock
149 163
Analog Supply Current IVDD
Power-down mode clock idle PD = OVDD 0.22
mA
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = GND,
single-ended clock
465
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = OVDD,
differential clock
492 538
Analog Power Dissipation PDISS
Power-down mode clock idle PD = OVDD 0.063
mW
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CL ≈ 5pF 9.9 mA
Digital Output Supply Current IOVDD
Power-down mode clock idle PD = OVDD 1.0 µA
MAX19538
12-Bit, 95Msps, 3.3V ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 6)
Clock Pulse-Width High tCH 5.26 ns
Clock Pulse-Width Low tCL 5.26 ns
Data-Valid Delay tDAV CL ≈ 5pF (Note 5) 6.8 ns
Data Setup Time Before Rising
Edge of DAV tSETUP CL ≈ 5pF (Notes 5, 6) 5.7 ns
Data Hold Time After Rising Edge
of DAV tHOLD CL ≈ 5pF (Notes 5, 6) 4.2 ns
Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V 10 ms
Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: See definitions in the Parameter Definitions section at the end of this data sheet.
Note 3: Limit specifications include performance degradations due to production test socket. Performance is improved when the
MAX19538 is soldered directly to the PC board.
Note 4: During power-down, D11–D0, DOR, and DAV are high impedance.
Note 5: Digital outputs settle to VIH or VIL.
Note 6: Guaranteed by design and characterization.
MAX19538
12-Bit, 95Msps, 3.3V ADC
_______________________________________________________________________________________ 7
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX19538 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
HD4
fCLK = 95MHz
fIN = 3.00354004MHz
AIN = -0.519dBFS
SNR = 70.89dB
SINAD = 70.83dB
THD = -89.3dBc
SFDR = 93.6dBc
HD3
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX19538 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
HD2
HD5
fCLK = 95MHz
fIN = 47.30285645MHz
AIN = -0.510dBFS
SNR = 70.80dB
SINAD = 70.41dB
THD = -81.0dBc
SFDR = 83.2dBc
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX19538 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
HD3
HD5
HD2
fCLK = 95MHz
fIN = 69.89318848MHz
AIN = -0.472dBFS
SNR = 70.65dB
SINAD = 70.35dB
THD = -82.1dBc
SFDR = 85.8dBc
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX19538 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
HD3
HD5 HD2
fCLK = 95MHz
fIN = 174.8895264MHz
AIN = -0.521dBFS
SNR = 69.02dB
SINAD = 68.19dB
THD = -75.8dBc
SFDR = 76.8dBc
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX19538 toc05
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
HD3 HD5
HD2
fCLK = 95MHz
fIN = 224.8944092MHz
AIN = -0.531dBFS
SNR = 68.14dB
SINAD = 66.42dB
THD = -71.3dBc
SFDR = 72.4dBc
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
MAX19538 toc06
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
2 × fIN1 + fIN2 fIN1 + fIN2
3 × fIN1 + 2 × fIN2
2 × fIN2 + fIN1
fIN2
fIN1
fCLK = 95MHz
fIN1 = 68.50739MHz
AIN1 = -7.0dBFS
fIN2 = 71.51093MHz
AIN2 = -7.0dBFS
SFDRTT = 84.7dB
IMD = -82.4dBc
IM3 = -84.3dBc
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
MAX19538 toc07
FREQUENCY (MHz)
AMPLITUDE (dBFS)
454030 3510 15 20 255
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0
2 × fIN1 + fIN2
fIN1 + fIN2
fIN2 - fIN1
2 × fIN2 + fIN1
fIN2
fIN1
fCLK = 95MHz
fIN1 = 172.4716MHz
AIN1 = -7.0dBFS
fIN2 = 177.4698MHz
AIN2 = -7.0dBFS
SFDRTT = 75.5dBc
IMD = -73.6dBc
IM3 = -76.0dBc
INTEGRAL NONLINEARITY
MAX19538 toc08
DIGITAL OUTPUT CODE
INL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
DIFFERENTIAL NONLINEARITY
MAX19538 toc09
DIGITAL OUTPUT CODE
DNL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
MAX19538
12-Bit, 95Msps, 3.3V ADC
8 _______________________________________________________________________________________
SNR, SINAD vs. SAMPLING RATE
MAX19538 toc10
fCLK (MHz)
SNR, SINAD (dB)
100755025
63
64
65
66
67
68
69
70
71
72
62
0 125
SNR
SINAD
fIN = 70MHz
SFDR, -THD vs. SAMPLING RATE
MAX19538 toc11
fCLK (MHz)
SFDR, -THD (dBc)
65
70
75
80
90
85
95
100
60
1007550250 125
SFDR
-THD
fIN = 70MHz
POWER DISSIPATION
vs. SAMPLING RATE
MAX19538 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
100755025
350
400
450
500
550
300
0 125
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN = 70MHz
CL ≈ 5pF
SNR, SINAD vs. SAMPLING RATE
MAX19538 toc13
fCLK (MHz)
SNR, SINAD (dB)
100755025
61
62
63
64
65
66
67
68
69
70
60
0 125
SNR
SINAD
fIN = 175MHz
SFDR, -THD
vs. SAMPLING RATE
MAX19538 toc14
fCLK (MHz)
SFDR, -THD (dBc)
65
70
75
80
90
85
95
100
60
1007550250 125
SFDR
-THD
fIN = 175MHz
POWER DISSIPATION
vs. SAMPLING RATE
MAX19538 toc15
fCLK (MHz)
POWER DISSIPATION (mW)
100755025
350
400
450
500
550
600
650
700
300
0 125
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
SNR, SINAD
vs. ANALOG INPUT FREQUENCY
MAX19538 toc16
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD (dB)
350300200 250100 15050
57
59
61
63
65
67
69
71
73
75
55
0 400
SNR
SINAD
fCLK = 95MHz
SFDR, -THD
vs. ANALOG INPUT FREQUENCY
MAX19538 toc17
SFDR, -THD (dBc)
60
65
70
75
80
85
90
95
100
55
ANALOG INPUT FREQUENCY (MHz)
350300200 250100 150500 400
SFDR
-THD
fCLK = 95MHz
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
MAX19538 toc18
ANALOG INPUT FREQUENCY (MHz)
POWER DISSIPATION (mW)
35030025020015010050
450
500
550
600
650
700
400
0 400
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 95MHz
CL ≈ 5pF
MAX19538
12-Bit, 95Msps, 3.3V ADC
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
SNR, SINAD
vs. ANALOG INPUT AMPLITUDE
MAX19538 toc19
ANALOG INPUT AMPLITUDE (dBFS)
SNR, SINAD (dB)
-5-10-20 -15-30 -25-35
30
35
40
45
50
55
60
65
70
75
25
-40 0
SNR
SINAD
fCLK = 95MHz
fIN = 175MHz
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
MAX19538 toc20
ANALOG INPUT AMPLITUDE (dBFS)
SFDR, -THD (dBc)
-5-10-20 -15-30 -25-35
45
50
55
60
65
70
75
80
85
90
40
-40 0
fCLK = 95MHz
fIN = 175MHz
SFDR
-THD
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
MAX19538 toc21
ANALOG INPUT AMPLITUDE (dBFS)
POWER DISSIPATION (mW)
-5-10-15-20-25-30-35
450
500
550
600
650
700
400
-40 0
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 96MHz
fIN = 175MHz
CL ≈ 5pF
SNR, SINAD
vs. ANALOG SUPPLY VOLTAGE
MAX19538 toc22
VDD (V)
SNR, SINAD (dB)
3.43.23.02.8
63
64
65
66
67
68
69
70
71
72
62
2.6 3.6
SNR
SINAD
fCLK = 95MHz
fIN = 175MHz
SFDR, -THD
vs. ANALOG SUPPLY VOLTAGE
MAX19538 toc23
VDD (V)
SFDR, -THD (dBc)
65
70
75
80
90
85
95
100
60
3.43.23.02.82.6 3.6
SFDR
-THD
fCLK = 95MHz
fIN = 175MHz
POWER DISSIPATION
vs. ANALOG SUPPLY VOLTAGE
MAX19538 toc24
VDD (V)
POWER DISSIPATION (mW)
3.43.23.02.8
350
400
450
500
550
600
300
2.6 3.6
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 95MHz
fIN = 175MHz
CL ≈ 5pF
SNR, SINAD
vs. DIGITAL SUPPLY VOLTAGE
MAX19538 toc25
OVDD (V)
3.4
3.02.62.21.81.4 3.8
SNR, SINAD (dB)
63
64
65
66
67
68
69
70
71
72
62
SNR
SINAD
fIN = 174.8953247MHz
fCLK = 95MHz
SFDR, -THD
vs. DIGITAL SUPPLY VOLTAGE
MAX19538 toc26
SFDR, -THD (dBc)
65
70
75
80
85
90
95
100
60
OVDD (V)
3.43.02.62.21.81.4 3.8
SFDR
-THD
fIN = 174.8953247MHz
fCLK = 95MHz
POWER DISSIPATION
vs. DIGITAL SUPPLY VOLTAGE
MAX19538 toc27
OVDD (V)
POWER DISSIPATION (mW)
3.43.02.62.21.8
450
500
550
600
650
700
400
1.4 3.8
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN = 175.8953247MHz
fIN = 95MHz
CL ≈ 5pF
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
MAX19538
12-Bit, 95Msps, 3.3V ADC
10 ______________________________________________________________________________________
SNR, SINAD
vs. TEMPERATURE
MAX19538 toc28
TEMPERATURE (°C)
SNR, SINAD (dB)
603510-15
63
64
65
66
67
68
69
70
71
72
62
-40 85
SNR
SINAD
fCLK = 95MHz
fIN = 175MHz
SFDR, -THD
vs. TEMPERATURE
MAX19538 toc29
TEMPERATURE (°C)
SFDR, -THD (dBc)
6035-15 10
65
70
75
80
90
85
95
100
60
-40 85
SFDR
-THD
fCLK = 95MHz
fIN = 175MHz
POWER DISSIPATION
vs. TEMPERATURE
MAX19538 toc30
TEMPERATURE (°C)
ANALOG POWER DISSIPATION (mW)
603510-15
450
500
550
600
650
700
400
-40 85
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 95MHz
fIN = 175MHz
CL ≈ 5pF
OFFSET ERROR
vs. TEMPERATURE
MAX19538 toc31
TEMPERATURE (°C)
OFFSET ERROR (%FS)
603510-15
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
-40 85
VREFIN = 2.048V
GAIN ERROR
vs. TEMPERATURE
MAX19538 toc32
TEMPERATURE (°C)
GAIN ERROR (%FS)
603510-15
-2.0
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-3.0
-40 85
VREFIN = 2.048V
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 11
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
REFERENCE OUTPUT VOLTAGE
LOAD REGULATION
MAX19538 toc33
IREFOUT SINK CURRENT (mA)
VREFOUT (V)
0-0.5-1.0-1.5
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
2.05
1.95
-2.0 0.5
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCE
MAX19538 toc34
IREFOUT SINK CURRENT (mA)
VREFOUT (V)
0-1.0-2.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
-3.0 1.0
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX19538 toc35
TEMPERATURE (°C)
VREFOUT (V)
603510-15
2.031
2.033
2.035
2.037
2.039
2.029
-40 85
REFP, COM, REFN
LOAD REGULATION
MAX19538 toc36
SINK CURRENT (mA)
VOLTAGE (V)
10-1
0.5
1.0
1.5
2.0
2.5
3.0
0
-2
INTERNAL REFERENCE MODE AND
BUFFERED EXTERNAL REFERENCE MODE.
2
VREFP
VREFN
VCOM
REFP, COM, REFN
SHORT-CIRCUIT PERFORMANCE
MAX19538 toc37
SINK CURRENT (mA)
VOLTAGE (V)
840-4
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
-8 12
INTERNAL REFERENCE MODE
AND BUFFERED EXTERNAL
REFERENCE MODE.
VREFP
VREFN
VCOM
MAX19538
12-Bit, 95Msps, 3.3V ADC
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 REFP
Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFP to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP-to-REFN capacitor as close to the device as possible on the
same side of the PC board.
2 REFN
Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFN to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP-to-REFN capacitor as close to the device as possible on the
same side of the PC board.
3 COM
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM-to-
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the
opposite side of the PC board and connected to the MAX19538 through a via.
4, 7, 16, 35 GND Ground. Connect all ground pins and EP together.
5 INP Positive Analog Input
6 INN Negative Analog Input
8 DCE Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.
9 CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the
differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND),
apply the single-ended clock signal to CLKP and connect CLKN to GND.
10 CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the
differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND),
apply the single-ended clock signal to CLKP and connect CLKN to GND.
11 CLKTYP Clock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input.
Connect CLKTYP to OVDD or VDD to define the differential clock input.
12–15, 36 VDD Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
17, 34 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with
a parallel capacitor combination of ≥2.2µF and 0.1µF.
18 DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the
analog input is within its full-scale range (Figure 6).
19 D11 CMOS Digital Output, Bit 11 (MSB)
20 D10 CMOS Digital Output, Bit 10
21 D9 CMOS Digital Output, Bit 9
22 D8 CMOS Digital Output, Bit 8
23 D7 CMOS Digital Output, Bit 7
24 D6 CMOS Digital Output, Bit 6
25 D5 CMOS Digital Output, Bit 5
26 D4 CMOS Digital Output, Bit 4
27 D3 CMOS Digital Output, Bit 3
28 D2 CMOS Digital Output, Bit 2
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 13
Figure 1. Pipeline Architecture—Stage Blocks
MAX19538 Σ
+
−
DIGITAL ERROR CORRECTION
FLASH
ADC
T/H
DAC
STAGE 2
D11–D0
INP
INN
STAGE 1
T/H STAGE 9 STAGE 10
END OF PIPE
OUTPUT
DRIVERS
D11–D0
Figure 2. Simplified Functional Diagram
MAX19538
INP
INN
12-BIT
PIPELINE
ADC DEC
REFERENCE
SYSTEM
COM
REFOUT
REFN
REFP
OVDD
DAV
OUTPUT
DRIVERS
D11–D0
DOR
REFIN
T/H
POWER CONTROL
AND
BIAS CIRCUITS
CLKP CLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKN
CLKTYP
PD
VDD
GND
DCE
G/T
Pin Description (continued)
PIN NAME FUNCTION
29 D1 CMOS Digital Output, Bit 1
30 D0 CMOS Digital Output, Bit 0 (LSB)
31, 32 I.C. Internally Connected. Leave I.C. unconnected.
33 DAV
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX19538 output data into an
external back-end digital circuit.
37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
38 REFOUT
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to
REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND
with a ≥0.1µF capacitor.
39 REFIN
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes VREFP - VREFN = VREFIN x 3/4. For unbuffered external
reference mode operation, connect REFIN to GND.
40 G/ TOutput-Format-Select Input. Connect G/ T to GND for the two’s-complement digital output format.
Connect G/ T to OVDD or VDD for the Gray-code digital output format.
—EP
Exposed Paddle. The MAX19538 relies on the exposed paddle connection for a low-inductance
ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to
connect the top-side PC board ground plane to the bottom-side PC board ground plane.
Detailed Description
The MAX19538 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every half clock cycle. From input to
output, the total clock-cycle latency is 8.5 clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX19538 functional diagram.
MAX19538
12-Bit, 95Msps, 3.3V ADC
14 ______________________________________________________________________________________
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit. This input T/H circuit
allows for high analog input frequencies of 175MHz
and beyond and supports a VDD / 2 ±0.5V common-
mode input voltage.
The MAX19538 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3), allowing
the analog input signal to be stored as charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and they are open
(hold) when the sampling clock is low (Figure 4). The
analog input signal source must be capable of provid-
ing the dynamic current necessary to charge and dis-
charge the sampling capacitors. To avoid signal degra-
dation, these capacitors must be charged to 1/2 LSB
accuracy within one half of a clock cycle.
The analog input of the MAX19538 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
supply (VDD / 2). The MAX19538 provides the optimum
common-mode voltage of VDD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX19538. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX19538 or when PD transitions from
high to low. REFOUT has approximately 17kΩto GND
when the MAX19538 is in power-down.
The internal bandgap reference and its buffer generate
VREFOUT to be 2.048V. The reference temperature coeffi-
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
REFOUT sources up to 1.0mA and sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
Short-circuit protection limits IREFOUT to a 2.1mA
source current when shorted to GND and a 0.24mA
sink current when shorted to VDD.
Figure 3. Simplified Input Track-and-Hold Circuit
MAX19538
CPAR
2pF
VDD
BOND WIRE
INDUCTANCE
1.5nH
INP
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE
4.5pF
CPAR
2pF
VDD
BOND WIRE
INDUCTANCE
1.5nH
INN
*CSAMPLE
4.5pF
RSAMPLE = 1
fCLK x CSAMPLE
Figure 4. T/H Aperture Timing
tAD
T/H
CLKN
CLKP
tAJ
TRACK HOLDTRACK HOLDTRACK HOLDTRACKHOLD
ANALOG
INPUT
SAMPLED
DATA
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 15
Analog Inputs and Reference
Configurations
The MAX19538 full-scale analog input range is
adjustable from ±0.35V to ±1.10V with a common-
mode input range of VDD / 2 ±0.5V. The MAX19538
provides three modes of reference operation. The volt-
age at REFIN (VREFIN) sets the reference operation
mode (Table 1).
To operate the MAX19538 with the internal reference,
connect REFOUT to REFIN either with a direct short or
through a resistive divider. In this mode, COM, REFP,
and REFN are low-impedance outputs with VCOM =
VDD / 2, VREFP = VDD / 2 + VREFIN x 3/8, and VREFN =
VDD / 2 - VREFIN x 3/8. The REFIN input impedance is
very large (>50MΩ). When driving REFIN through a
resistive divider, use resistances ≥10kΩto avoid load-
ing REFOUT.
Buffered external reference mode is virtually identical to
internal reference mode except that the reference
source is derived from an external reference and not
the MAX19538 REFOUT. In buffered external reference
mode, apply a stable 0.7V to 2.2V source at REFIN. In
this mode, COM, REFP, and REFN are low-impedance
outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN
x 3/8, and VREFN = VDD/2 - VREFIN x 3/8.
To operate the MAX19538 in unbuffered external refer-
ence mode, connect REFIN to GND. Connecting REFIN
to GND deactivates the on-chip reference buffers for
COM, REFP, and REFN. With the respective buffers
deactivated, COM, REFP, and REFN become high-
impedance inputs and must be driven through sepa-
rate, external reference sources. Drive VCOM to VDD / 2
±5%, and drive REFP and REFN such that VCOM =
(VREFP + VREFN) / 2. The full-scale analog input range
is ±(VREFP - VREFN) x 2/3.
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
For detailed circuit suggestions, see Figures 13 and 14.
VREFIN REFERENCE MODE
35% VREFOUT to 100% VREFOUT
Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a
resistive divider.
The full-scale analog input range is ±VREFIN / 2:
VCOM = VDD / 2
VREFP = VDD / 2 + VREFIN x 3/8
VREFN = VDD / 2 - VREFIN x 3/8
0.7V to 2.2V
Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to
REFIN.
The full-scale analog input range is ±VREFIN / 2:
VCOM = VDD / 2
VREFP = VDD / 2 + VREFIN x 3/8
VREFN = VDD / 2 - VREFIN x 3/8
<0.4V
Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference
sources.
The full-scale analog input range is ±(VREFP - VREFN) x 2/3.
Table 1. Reference Modes
MAX19538
12-Bit, 95Msps, 3.3V ADC
16 ______________________________________________________________________________________
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
The MAX19538 accepts both differential and single-
ended clock inputs. For single-ended clock input oper-
ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock input operation, connect CLKTYP
to OVDD or VDD, and drive CLKP and CLKN with the
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
CLKP and CLKN are high impedance when the
MAX19538 is powered down (Figure 5).
Low clock jitter is required for the specified SNR perfor-
mance of the MAX19538. Analog input sampling
occurs on the falling edge of the clock signal, requiring
this edge to have the lowest possible jitter. Jitter limits
the maximum SNR performance of any ADC according
to the following relationship:
where fIN represents the analog input frequency and tJ
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 68.4dB of SNR with an input fre-
quency of 175MHz, the system must have less than
0.35ps of clock jitter. In actuality, there are other noise
sources such as thermal noise and quantization noise
that contribute to the system noise requiring the clock
jitter to be less than 0.23ps to obtain the specified
68.4dB of SNR at 175MHz.
Clock Duty-Cycle Equalizer (DCE)
Connect DCE high to enable the clock duty-cycle equal-
izer (DCE = OVDD or VDD). Connect DCE low to disable
the clock duty-cycle equalizer (DCE = GND). With the
clock duty-cycle equalizer enabled, the MAX19538 is
insensitive to the duty cycle of the signal applied to
CLKP and CLKN. Duty cycles from 35% to 65% are
acceptable with the clock duty-cycle equalizer enabled.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX19538 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Although not recommended, disabling the clock duty-
cycle equalizer reduces the analog supply current by
1.5mA. With the clock duty-cycle equalizer disabled, the
MAX19538’s dynamic performance varies depending on
the duty cycle of the signal applied to CLKP and CLKN.
SNR ft
IN J
=× ×× ×
⎛
⎝
⎜⎞
⎠
⎟
log20 1
2π
Figure 5. Simplified Clock Input Circuit
MAX19538
CLKP
CLKN
VDD
GND
10kΩ
10kΩ
10kΩ
10kΩ
DUTY-CYCLE
EQUALIZER
SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S2_ ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
S1H
S2H
S1L
S2L
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 17
System Timing Requirements
Figure 6 shows the relationship between the clock, ana-
log inputs, DAV indicator, DOR indicator, and the result-
ing output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.5 clock cycles later.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP-CLKN).
Data-Valid Output (DAV)
DAV is a single-ended version of the input clock (CLKP).
Output data changes on the falling edge of DAV, and
DAV rises once output data is valid (Figure 6).
The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle equal-
izer disabled (DCE = low), the DAV signal is the inverse
of the signal at CLKP delayed by 6.8ns. With the duty-
cycle equalizer enabled (DCE = high), the DAV signal
has a fixed pulse width that is independent of CLKP. In
either case, with DCE high or low, output data at D11–D0
and DOR are valid from 5.7ns (tSETUP) before the rising
edge of DAV to 4.2ns (tHOLD) after the rising edge of
DAV, and the rising edge of DAV is synchronized to have
a 6.8ns (tDAV) delay from the falling edge of CLKP.
DAV is high impedance when the MAX19538 is in power-
down (PD = high). DAV is capable of sinking and sourc-
ing 600µA and has three times the drive strength of
D11–D0 and DOR. DAV is typically used to latch the
MAX19538 output data into an external back-end digital
circuit.
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back into
the analog portion of the MAX19538 and degrading its
dynamic performance. An external buffer on DAV isolates
it from heavy capacitive loads. Refer to the MAX1211
evaluation kit schematic for an example of DAV driving
back-end digital circuitry through an external buffer.
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (VREFP - VREFN) x 2/3 to (VREFN - VREFP) x 2/3.
Signals outside this valid differential range cause DOR
to assert high as shown in Table 2 and Figure 6.
DOR is synchronized with DAV and transitions along
with the output data D11–D0. There is an 8.5 clock-
cycle latency in the DOR function, as is with the output
data (Figure 6).
DOR is high impedance when the MAX19538 is in
power-down (PD = high). DOR enters a high-imped-
ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Figure 6. System Timing Diagram
DAV
D0–D11
NN + 1 N + 2
N + 3
N + 4 N + 5
N + 6
N + 7
N + 8
N + 9
tDAV
tSETUP
tAD
N - 1
N - 2
N - 3
tHOLD
tCL tCH
DOR
8.5 CLOCK-CYCLE DATA LATENCY
DIFFERENTIAL ANALOG INPUT (INP–INN)
tSETUP tHOLD
N N + 1 N + 2 N + 3 N + 5 N + 6 N + 7N - 1N - 2N - 3 N + 9N + 4 N + 8
CLKN
CLKP
(VREFP - VREFN) x 2/3
(VREFN - VREFP) x 2/3
MAX19538
12-Bit, 95Msps, 3.3V ADC
18 ______________________________________________________________________________________
Digital Output Data (D11–D0), Output Format (G/ T)
The MAX19538 provides a 12-bit, parallel, tri-state output
bus. D11–D0 and DOR update on the falling edge of
DAV and are valid on the rising edge of DAV.
The MAX19538 output data format is either Gray code
or two’s complement, depending on the logic input G/T.
With G/Thigh, the output data format is Gray code.
With G/Tlow, the output data format is two’s comple-
ment. See Figure 9 for a binary-to-Gray and Gray-to-
binary code conversion example.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
for Gray code (G/T= 1).
for two’s complement (G/T= 0).
where CODE10 is the decimal equivalent of the digital
output code as shown in Table 2.
Digital outputs D11–D0 are high impedance when the
MAX19538 is in power-down (PD = high). D11–D0 transi-
tion high 10ns after the rising edge of PD and become
active 10ns after PD’s falling edge.
Keep the capacitive load on the MAX19538 digital out-
puts D11–D0 as low as possible (<15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX19538 and degrading its dynamic perfor-
mance. The addition of external digital buffers on the
digital outputs isolates the MAX19538 from heavy
capacitive loading. To improve the dynamic perfor-
mance of the MAX19538, add 220Ωresistors in series
with the digital outputs close to the MAX19538. Refer to
the MAX1211 evaluation kit schematic for an example
of the digital outputs driving a digital buffer through
220Ωseries resistors.
VV V V CODE
INP INN REFP REFN
−−=
()
××
4
3 4096
10
VV V V CODE
INP INN REFP REFN
−− −
=
()
××
4
3
2048
4096
10
Figure 7. Two’s-Complement Transfer Function (G/
T
= 0)
DIFFERENTIAL INPUT VOLTAGE (LSB)
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
-2045 +2047+2045-1 0 +1-2047
0x800
0x801
0x802
0x803
0x7FF
0x7FE
0x7FD
0xFFF
0x000
0x001
(VREFP - VREFN) x 2/3 (VREFP - VREFN) x 2/3
Figure 8. Gray-Code Transfer Function (G/
T
= 1)
DIFFERENTIAL INPUT VOLTAGE (LSB)
GRAY OUTPUT CODE (LSB)
+1 +2047+2045-1 0
-2047 -2045
0x000
0x001
0x003
0x002
0x800
0x801
0x803
0x400
0xC00
0xC01
(VREFP - VREFN) x 2/3 (VREFP - VREFN) x 2/3
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 19
Table 2. Output Codes vs. Input Voltage
GRAY-CODE
OUTPUT CODE
(G/TT
TT = 1)
TWO’S-COMPLEMENT
OUTPUT CODE
(G/TT
TT = 0)
BINARY
D11 D0 DOR
HEXADECIMAL
EQUIVALENT
OF
D11 D0
D EC IM A L
EQ U IVA L EN T O F
D11 D0
(CODE10)
BINARY
D11 D0 DOR
H EXA D EC IM A L
EQ U IVA L EN T O F
D11 D0
DECIM AL
EQUIVALENT OF
D11 D0
(CODE10)
VINP - VINN
VREFP = 2.418V
VREFN = 0.882V
1000 0000 0000 10x800 +4095 0111 1111 1111 10x7FF +2047
>+1.0235V
(DATA OUT OF
RANGE)
1000 0000 0000 0 0x800 +4095 0111 1111 1111 0 0x7FF +2047 +1.0235V
1000 0000 0001 0 0x801 +4094 0111 1111 1110 0 0x7FE +2046 +1.0230V
1100 0000 0011 0 0xC03 +2050 0000 0000 0010 0 0x002 +2 +0.0010V
1100 0000 0001 0 0xC01 +2049 0000 0000 0001 0 0x001 +1 +0.0005V
1100 0000 0000 0 0xC00 +2048 0000 0000 0000 0 0x000 0 +0.0000V
0100 0000 0000 0 0x400 +2047 1111 1111 1111 0 0xFFF -1 -0.0005V
0100 0000 0001 0 0x401 +2046 1111 1111 1110 0 0xFFE -2 -0.0010V
0000 0000 0001 0 0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235V
0000 0000 0000 0 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V
0000 0000 0000 10x000 0 1000 0000 0000 10x800 -2048
<-1.0240V
(DATA OUT OF
RANGE)
MAX19538
12-Bit, 95Msps, 3.3V ADC
20 ______________________________________________________________________________________
Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion
BINARY-TO-GRAY-CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
0 1 1 1 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
D11 D7 D3 D0
GRAYX = BINARYX +BINARYX + 1
BIT POSITION
0 1 1 1 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
GRAY10 = BINARY10 BINARY11
GRAY10 = 1 0
GRAY10 = 1
1
3) REPEAT STEP 2 UNTIL COMPLETE:
0 1 1 1 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
GRAY9 = BINARY9BINARY10
GRAY9 = 1 1
GRAY9 = 0
10
4) THE FINAL GRAY-CODE CONVERSION IS:
0 1 1 1 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
1001101 1010
GRAY-TO-BINARY-CODE CONVERSION
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
D11 D7 D3 D0
BINARYX = BINARYX+1
BIT POSITION
BINARY10 = BINARY11 GRAY10
BINARY10 = 0 1
BINARY10 = 1
3) REPEAT STEP 2 UNTIL COMPLETE:
4) THE FINAL BINARY CONVERSION IS:
0100 1110 1010
BINARY
GRAY CODE
D11 D7 D3 D0 BIT POSITION
0 BINARY
GRAY CODE0100 11 011010
BINARY9 = BINARY10 GRAY9
BINARY9 = 1 0
BINARY9 = 1
GRAYX
0 100 1110 1010
BINARY
GRAY CODE
0
D11 D7 D3 D0 BIT POSITION
1
01 00 1110 1010
BINARY
GRAY CODE
0
D11 D7 D3 D0 BIT POSITION
11
0111 0100 1100
AB Y=AB
00
01
10
11
0
1
1
0
EXCLUSIVE OR TRUTH TABLE
WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 21
Power-Down Input (PD)
The MAX19538 has two power modes that are con-
trolled with the power-down digital input (PD). With PD
low, the MAX19538 is in normal operating mode. With
PD high, the MAX19538 is in power-down mode.
The power-down mode allows the MAX19538 to effi-
ciently use power by transitioning to a low-power state
when conversion is not required. Additionally, the
MAX19538 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
In power-down mode, all internal circuits are off, the
analog supply current reduces to 0.02mA, and the digi-
tal supply current reduces to 1µA. The following list
shows the state of the analog inputs and digital outputs
in power-down mode:
• INP, INN analog inputs are disconnected from the
internal input amplifier (Figure 3).
• REFOUT has approximately 17kΩto GND.
• REFP, COM, REFN go high impedance with respect
to VDD and GND, but there is an internal 4kΩresistor
between REFP and COM, as well as an internal 4kΩ
resistor between REFN and COM.
Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
MAX19538
1
2
3
6
5
4
N.C. N.C.
T2
MINI-CIRCUITS
ADT1-1WT
1
2
3
6
5
4
N.C.
VIN
0.1µF
T1
MINI-CIRCUITS
ADT1-1WT
0Ω*
0Ω*
5.6pF**
5.6pF**
2.2µF
INP
COM
INN
110Ω
0.1%
110Ω
0.1%
75Ω
0.5%
75Ω
0.5%
*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE
RESISTORS TO LIMIT THE BANDWIDTH.
**TUNE THESE CAPACITORS FROM 5.6pF TO 18pF IN ORDER TO
OPTIMIZE DYNAMIC PERFORMANCE VARIATIONS DUE TO:
PRINTED CIRCUIT BOARD (PCB) LAYOUT
ANALOG INPUT SIGNAL POWER
ANALOG INPUT CARRIER FREQUENCY
Figure 10. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
MAX19538
1
2
3
6
5
4
N.C.
VIN
0.1µF
T1
MINI-CIRCUITS
TT1-6 OR T1-1T
24.9Ω
24.9Ω
12pF
12pF
2.2µF
INP
COM
INN
Figure 12. Single-Ended, AC-Coupled Input Drive
MAX19538
5.6pF
5.6pF
2.2µF
INP
COM
INN
24.9Ω
24.9Ω
100Ω
100Ω
0.1µF
MAX4108
VIN
MAX19538
12-Bit, 95Msps, 3.3V ADC
22 ______________________________________________________________________________________
Figure 13. External Buffered Reference Driving Multiple ADCs
MAX19538
NOTE: ONE FRONT-END REFERENCE
CIRCUIT IS CAPABLE OF SOURCING 15mA
AND SINKING 30mA OF OUTPUT CURRENT.
*PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
16.2kΩ
0.1µF
0.1µF
1µF
2
5
2.048V
2.048V
+3.3V
1
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10µF
6V
330µF
6V
+3.3V
2.2µF
2.2µF
0.1µF
1µF* 10µF
0.1µF
0.1µF
0.1µF
REFP
REFN
COM
3
2
1
VDD
GND
REFIN
39
REFOUT
38
MAX19538
+3.3V
2.2µF
2.2µF
0.1µF
1µF* 10µF
0.1µF
0.1µF
0.1µF
REFP
REFN
COM
3
2
1
VDD
GND
REFIN
39
REFOUT
38
MAX6029EUK21
MAX4230
• D11–D0, DOR, and DAV go high impedance.
• CLKP, CLKN go high impedance (Figure 5).
The wake-up time from power-down mode is dominat-
ed by the time required to charge the capacitors at
REFP, REFN, and COM. In internal reference mode and
buffered external reference mode the wake-up time is
typically 10ms with the recommended capacitor array
(Figure 13). When operating in unbuffered external ref-
erence mode, the wake-up time is dependent on the
external reference drivers.
Applications Information
Using Transformer Coupling
In general, the MAX19538 provides better SFDR and
THD performance with fully differential input signals as
opposed to single-ended input drive. In differential
input mode, even-order harmonics are lower as both
inputs are balanced, and each of the ADC inputs only
requires half the signal swing compared to single-
ended input mode.
An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX19538
for optimum performance. Connecting the center tap of
the transformer to COM provides a VDD / 2 DC level
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 23
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 10 is good
for frequencies up to Nyquist (fCLK / 2).
The circuit of Figure 11 converts a single-ended input
signal to fully differential just as Figure 10. However
Figure 11 utilizes an additional transformer to improve
the common-mode rejection allowing high-frequency
signals beyond the Nyquist frequency. The two sets of
termination resistors provide an equivalent 50Ωtermi-
nation to the signal source, as the ADT1-1WT trans-
former has a 1:1.5 impedance ratio. The second set of
termination resistors connects to COM, providing the
correct input common-mode voltage. Two 0Ωresistors
in series with the analog inputs allow high IF input fre-
quencies. These 0Ωresistors can be replaced with low-
value resistors to limit the input bandwidth.
Single-Ended AC-Coupled Input Signal
Figure 12 shows an AC-coupled, single-ended input
application. The MAX4108 operational amplifier pro-
vides high speed, high bandwidth, low noise, and low
distortion to maintain the input signal integrity.
Figure 14. External Unbuffered Reference Driving Multiple ADCs
MAX19538
*PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
0.1µF
0.1µF
5
2.413V
+3.3V
1
2
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10µF
6V
330µF
6V
+3.3V
2.2µF
0.1µF
1µF*
10µF
0.1µF
0.1µF
0.1µF
REFOUT
REFN
REFIN 39
1
2
3
VDD
GND
COM
REFP 38
MAX6029EUK30
MAX4230
0.1µF
0.47µF
1.647V
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10µF
6V
330µF
6V
MAX4230
0.1µF
0.880V
2
4
1
3
5
47Ω
1.47kΩ
+3.3V
10µF
6V
330µF
6V
MAX4230
MAX19538
+3.3V
2.2µF
0.1µF
1µF*
10µF
0.1µF
0.1µF
0.1µF
REFOUT
REFN
REFIN 39
1
2
3
VDD
GND
COM
REFP 38
3.000V
20kΩ
1%
20kΩ
1%
52.3kΩ
1%
52.3kΩ
1%
20kΩ
1%
20kΩ
1%
20kΩ
1%
0.1µF
2.2µF
2.2µF
MAX19538
12-Bit, 95Msps, 3.3V ADC
24 ______________________________________________________________________________________
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX19538 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is >50MΩ.
Figure 13 uses the MAX6029EUK21 precision 2.048V
reference as a common reference for multiple convert-
ers. The 2.048V output of the MAX6029 passes through
a one-pole, 10Hz lowpass filter to the MAX4230. The
MAX4230 buffers the 2.048V reference and provides
additional 10Hz lowpass filtering before its output is
applied to the REFIN input of the MAX19538.
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX19538 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
ence, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
Figure 14 uses the MAX6029EUK30 precision 3.000V
reference as a common reference for multiple convert-
ers. A seven-component resistive divider chain fol-
lows the MAX6029 voltage reference. The 0.47µF
capacitor along this chain creates a 10Hz lowpass
filter. Three MAX4230 operational amplifiers buffer taps
along this resistor chain providing 2.413V, 1.647V, and
0.880V to the MAX19538’s REFP, COM, and REFN ref-
erence inputs, respectively. The feedback around the
MAX4230 op amps provides additional 10Hz low-
pass filtering. The 2.413V and 0.880V reference volt-
ages set the full-scale analog input range to
±1.022V = ±(VREFP - VREFN) x 2/3.
A common power source for all active components
removes any concern regarding power-supply
sequencing when powering up or down
Grounding, Bypassing,
and Board Layout
The MAX19538 requires high-speed board layout
design techniques. Refer to the MAX1211 evaluation kit
data sheet for a board layout reference. Locate all
bypass capacitors as close to the device as possible,
preferably on the same side of the board as the ADC,
using surface-mount devices for minimum inductance.
Bypass VDD to GND with a 0.1µF ceramic capacitor in
parallel with a 2.2µF ceramic capacitor. Bypass OVDD
to GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All
MAX19538 GNDs and the exposed backside paddle
must be connected to the same ground plane. The
MAX19538 relies on the exposed backside paddle con-
nection for a low-inductance ground connection. Use
multiple vias to connect the top-side ground to the bot-
tom-side ground. Isolate the ground plane from any
noisy digital system ground planes such as a DSP or
output buffer ground.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90°turns.
Ensure that the differential analog input network layout is
symmetric and that all parasitics are balanced equally.
Refer to the MAX1211 evaluation kit data sheet for an
example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX19538, this straight line is between the end points of
the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every step
of the transfer function and the worst-case deviation is
reported in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. For
the MAX19538, DNL deviations are measured at every
step of the transfer function and the worst-case devia-
tion is reported in the Electrical Characteristics table.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX19538 transition occurs at 0.5 LSB above midscale.
The offset error is the amount of deviation between the
measured midscale transition point and the ideal mid-
scale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. The slope of the actual
transfer function is measured between two data points:
positive full scale and negative full scale. Ideally the
positive full-scale MAX19538 transition occurs at 1.5
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 25
LSB below positive full scale, and the negative full-
scale transition occurs at 0.5 LSB above negative full
scale. The gain error is the difference of the measured
transition points minus the difference of the ideal transi-
tion points.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and dis-
tortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calcu-
lation. For this converter, a small signal is defined as a
single tone with an amplitude less than -35dBFS. This
parameter captures the thermal and quantization noise
characteristics of the converter and can be used to
help calculate the overall noise figure of a receive
channel. Go to www.maxim-ic.com for application
notes on thermal + quantization noise floor.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR[max] = 6.02 ×N + 1.76
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2 to HD7), and
the DC offset:
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first six har-
monics (HD2–HD7), and the DC offset. RMS distortion
includes the first six harmonics (HD2–HD7):
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Single-Tone Spurious-Free
Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS amplitude of the next-largest spurious
component, excluding DC offset.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V1is the fundamental amplitude, and V2through
V7are the amplitudes of the 2nd- through 7th-order
harmonics (HD2–HD7).
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
The fundamental input tone amplitudes (V1and V2) are
at -7dBFS. Fourteen intermodulation products (VIM_)
are used in the MAX19538 IMD calculation. The inter-
modulation products are the amplitudes of the output
spectrum at the following frequencies, where fIN1 and
fIN2 are the fundamental input tone frequencies:
• Second-order intermodulation products:
fIN1 + fIN2, fIN2 - fIN1
• Third-order intermodulation products:
2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
• Fourth-order intermodulation products:
3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1
IMD VV V V
VV
IM IM IM IM
log ...........
=× ++++
+
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20
12
1
222132142
22
THD VVVVVV
V
log=× +++++
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20 223242526272
1
ENOB SINAD
=⎛
⎝
⎜⎞
⎠
⎟
−
.
.
176
602
SINAD SIGNAL
NOISE DISTORTION
RMS
RMS RMS
=×
+
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
log20
22
SNR SIGNAL
NOISE
RMS
RMS
=×
⎛
⎝
⎜⎞
⎠
⎟
log20
MAX19538
12-Bit, 95Msps, 3.3V ADC
26 ______________________________________________________________________________________
• Fifth-order intermodulation products:
3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2,
3 x fIN2 + 2 x fIN1
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones fIN1 and fIN2. The
individual input tone levels are at -7dBFS. The third-
order intermodulation products are 2 ×fIN1 - fIN2, 2 ×
fIN2 - fIN1, 2 ×fIN1 + fIN2, 2 ×fIN2 + fIN1.
Two-Tone Spurious-Free
Dynamic Range (SFDRTT)
SFDRTT represents the ratio, expressed in decibels, of
the RMS amplitude of either input tone to the RMS
amplitude of the next-largest spurious component in the
spectrum, excluding DC offset. This spurious compo-
nent can occur anywhere in the spectrum up to Nyquist
and is usually an intermodulation product or a harmonic.
Aperture Delay
The MAX19538 samples data on the falling edge of its
sampling clock. In actuality, there is a small delay
between the falling edge of the sampling clock and the
actual sampling instant. Aperture delay (tAD) is the time
defined between the falling edge of the sampling clock
and the instant when an actual sample is taken (Figure 4).
Aperture Jitter
Figure 4 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to the ther-
mal + quantization noise parameter and is an indication
of the ADC’s overall noise performance.
No fundamental input tone is used to test for nOUT; INP,
INN, and COM are connected together and 1024k
data points collected. nOUT is computed by taking
the RMS value of the collected data points after the mean
is removed.
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX19538 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%.
REFP 1
REFN 2
COM 3
GND 4
INP 5
INN 6
GND 7
DCE 8
CLKN 9
CLKP 10
D030
D129
D228
D327
D426
D525
D624
D723
D822
D921
40
REFIN
39
REFOUT
38
PD
37
VDD
36
GND
35
OVDD
34
DAV
33
I.C.
32
I.C.
31
CLKTYP
11
VDD
12
VDD
13
VDD
14
VDD
15
GND
16
OVDD
17
DOR
18
D11
19
D10
20
G/T
TOP VIEW
MAX19538
EXPOSED PADDLE (GND)
THIN QFN
6mm x 6mm x 0.8mm
Pin Configuration
MAX19538
12-Bit, 95Msps, 3.3V ADC
______________________________________________________________________________________ 27
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
e e
LL
A1 A2 A
E/2
E
D/2
D
E2/2
E2
(NE-1) X e
(ND-1) X e
e
D2/2
D2
b
k
k
L
C
L
C
L
C
L
C
L
E
1
2
21-0141
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
L1
L
e
MAX19538
12-Bit, 95Msps, 3.3V ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
3. N IS THE TOTAL NUMBER OF TERMINALS.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
E
2
2
21-0141
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
