3
MD1715
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Operating Supply Current
(Over operating conditions unless otherwise specied, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
IAVDDEN AVDD power up current - 2.0 3.0 mA
EN = 1, all inputs low.
IVSSEN VSS power up current - 0.7 1.0 mA
IVDD1EN VDD1 power up current - 10 - µA
IVDD2EN VDD2 power up current - 10 - µA
IAVDDCW AVDD CW 5MHz current - 10 - mA A&B channel on at 5.0MHz no load,
VDD1 = 12V, VDD2 = 5.0V
IVSSCW VSS CW 5MHz current - 5.0 -
IVDD1CW VDD1 CW 5MHz current - 25 - mA A&B channel on at 5.0MHz no load,
VDD1 = 5.0V, VDD2 = 12V
IVDD2CW VDD2 CW 5MHz current - 25 - mA A&B channel on at 5.0MHz no load,
VDD1 = 12V, VDD2 = 5.0V
AC Electrical Characteristics
(Over operating conditions unless otherwise specied, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
tirf Input rise & fall time - - 10 ns Logic input edge speed requirement
trOutput rise time - 6.5 - ns 1nF load, see timing diagram, input
signal rise/fall time 2.0ns
tfOutput fall time - 6.5 - ns ---
tdr Output rise delay - 10 - ns ---
tdf Output fall delay - 10 - ns ---
|tr - tf| Rise and fall time matching - 1.0 - - For each channel
|tdr - tdf| Propagation delay matching - 1.0 - - ---
tdm Delay time matching - ±2.0 - ns Ch to Ch and Device to Device
ΔtjOutput jitter - 20 - ps VDD = 10V
tEN_ON IC enable time - 25 50 μs ---
tEN_OFF IC disable time - 0.5 2.0 μs ---
HD2 2nd harmonic distortion -40 - - dB ---
P-Channel Gate Driver Outputs
Sym Parameter Min Typ Max Units Conditions
RSINK Output sink resistance - 5.0 6.0 ΩISINK = 100mA
RSOURCE Output source resistance - 5.0 6.0 ΩISOURCE = 100mA
ISINK Peak output sink current 1.7 2.0 - A ---
ISOURCE Peak output source current 1.7 2.0 - A ---