Supertex inc. MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Features
Advanced CMOS technology
±4.75 to 12.9V gate drive voltage
2A output source and sink current
6.5ns rise and fall time with 1nF load
10ns propagation delay
±2ns matched delay times
12 matched channels
1.8V to 3.3V CMOS logic interface
Smart logic threshold
Low inductance package
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Metal aw detection
Non-Destructive Testing (NDT)
General Description
The Supertex MD1715, paired with the Supertex TC8020, forms
a two channel, ve level, high voltage, high speed transmit pulser
chip set. The chip set is designed for medical ultrasound imaging
applications, but can also be used for metal aw detection, Non-
Destructive Testing (NDT), and piezoelectric transducer drivers.
The MD1715 is a two channel logic controller circuit with 12 low
impedance MOSFET gate drivers. There are two sets of control
logic inputs, one each for channels A and B. Each channel
consists of three pairs of MOSFET gate drivers. These drivers
are designed to match the drive requirements of the Supertex
TC8020.
The TC8020 is the output stage of the pulser, with six pairs of
MOSFETs. Each pair consists of a P-channel and an N-channel
MOSFET. They are designed to have the same impedance and
can provide typical peak currents of ±3.5 amps at 200V.
Typical Application Circuit
Two Channel, Five Level, High Speed
Ultrasound Driver IC
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
TX(B)
TX(A)
TC8020
MD1715
AVDD
SELA
POSA
NEGA
POSB
NEGB
SELB
OP1A
ON1A
OP2A
ON2A
OP3A
ON3A
OP1B
ON1B
OP2B
ON2B
OP3B
ON3B
GP1
GN1
GP2
GN2
GP3
GN3
GP4
GN4
GP5
GN5
GP6
GN6
AGND
VLL/EN
+12V
GND AVSS(SUB) VSS
1.8 to 3.3V
CMOS
Input Logic
VDD1 VDD2
-12V
+12V +12V
+3.3V
-12V
VPP2
SP2
VPP1
SP1
SP3 SP4
SP5
SP6
SN3 SN2 SN1
VNN1
VNN2
SN5 SN4
SN6
PAD
DP1
DN1
DP2
DN2
DP3
DN3
DP4
DN4
DP5
DN5
DP6
DN6
2
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Ordering Information
Device
Package Option
40-Lead QFN
6.00x6.00mm body
1.0mm height (max)
0.50mm pitch
MD1715 MD1715K6-G
Absolute Maximum Ratings
Parameter Value
GND and AGND, Ground 0V
VLL logic input pin -0.5V to +5.5V
AVDD, VDD1, positive gate drive supply -0.5V to +14.5V
VDD2, positive gate drive supply -0.5V to +14.5V
AVSS, VSS, negative gate drive supply -14.5V to +0.5V
Storage temperature -65°C to 150°C
Power dissipation* 1.3W
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
* 1.0oz 4-layer 3x4” PCB
-G indicates package is RoHS compliant (‘Green’)
Pin Conguration
Package Marking
40-Lead QFN (K6)
(top view)
40-Lead QFN (K6)
Operating Supply Voltages
Sym Parameter Min Typ Max Units Conditions
VLL Logic supply 1.8 3.3 3.6 V ---
AVDD Positive analog supply 8.0 - 12.9 V AVDD ≥ (VDD1 or VDD2)
VDD2, VDD1 Positive gate drive supply 4.75 - 12.9 V ---
AVSS, VSS Negative gate drive supply -12.9 - -4.75 V ---
Operating Supply Current
(Over operating conditions unless otherwise specied, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
IVLL Logic reference current 10 µA VLL = 3.3V
IAVDDQ AVDD power down current - 0.4 - mA
EN = 0, all inputs Low.
IVSSQ VVSS power down current - 0.1 -
IVDD1Q VDD1 power down current - 10 25 µA
IVDD2Q VDD2 power down current - 10 25
Package may or may not include the following marks: Si or
1
40
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
MD1715
LLLLLL
YYWW
AAA CCC
3
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Operating Supply Current
(Over operating conditions unless otherwise specied, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
IAVDDEN AVDD power up current - 2.0 3.0 mA
EN = 1, all inputs low.
IVSSEN VSS power up current - 0.7 1.0 mA
IVDD1EN VDD1 power up current - 10 - µA
IVDD2EN VDD2 power up current - 10 - µA
IAVDDCW AVDD CW 5MHz current - 10 - mA A&B channel on at 5.0MHz no load,
VDD1 = 12V, VDD2 = 5.0V
IVSSCW VSS CW 5MHz current - 5.0 -
IVDD1CW VDD1 CW 5MHz current - 25 - mA A&B channel on at 5.0MHz no load,
VDD1 = 5.0V, VDD2 = 12V
IVDD2CW VDD2 CW 5MHz current - 25 - mA A&B channel on at 5.0MHz no load,
VDD1 = 12V, VDD2 = 5.0V
AC Electrical Characteristics
(Over operating conditions unless otherwise specied, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
tirf Input rise & fall time - - 10 ns Logic input edge speed requirement
trOutput rise time - 6.5 - ns 1nF load, see timing diagram, input
signal rise/fall time 2.0ns
tfOutput fall time - 6.5 - ns ---
tdr Output rise delay - 10 - ns ---
tdf Output fall delay - 10 - ns ---
|tr - tf| Rise and fall time matching - 1.0 - - For each channel
|tdr - tdf| Propagation delay matching - 1.0 - - ---
tdm Delay time matching - ±2.0 - ns Ch to Ch and Device to Device
ΔtjOutput jitter - 20 - ps VDD = 10V
tEN_ON IC enable time - 25 50 μs ---
tEN_OFF IC disable time - 0.5 2.0 μs ---
HD2 2nd harmonic distortion -40 - - dB ---
P-Channel Gate Driver Outputs
Sym Parameter Min Typ Max Units Conditions
RSINK Output sink resistance - 5.0 6.0 ΩISINK = 100mA
RSOURCE Output source resistance - 5.0 6.0 ΩISOURCE = 100mA
ISINK Peak output sink current 1.7 2.0 - A ---
ISOURCE Peak output source current 1.7 2.0 - A ---
4
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
N-Channel Gate Driver Outputs
Sym Parameter Min Typ Max Units Conditions
RSINK Output sink resistance - 5.0 6.0 ΩISINK = 100mA
RSOURCE Output source resistance - 5.0 6.0 ΩISOURCE = 100mA
ISINK Peak output sink current 1.7 2.0 - A ---
ISOURCE Peak output source current 1.7 2.0 - A ---
Logic Inputs
Sym Parameter Min Typ Max Units Conditions
VENL Chip disable low voltage 0 - 0.3 V VLL/EN is a dual function pin
VIH Input logic high voltage 0.8VLL - VLL V ---
VIL Input logic low voltage 0 - 0.2VLL V ---
IIH Input logic high current - - 1.0 µA ---
IIL Input logic low current -1.0 - - µA ---
Truth Table for Channels A and B
EN
Logic Inputs A SP1
to
DP1
SN1
to
DN1
SP2
to
DP2
SN2
to
DN2
SP3
to
DP3
SN3
to
DN3
SELA POSA NEGA
1 0 0 0 OFF OFF OFF OFF ON ON
1 0 0 1 OFF OFF OFF ON OFF OFF
1 0 1 0 OFF OFF ON OFF OFF OFF
1 0 1 1 OFF OFF OFF OFF OFF OFF
1 1 0 0 OFF OFF OFF OFF ON ON
1 1 0 1 OFF ON OFF OFF OFF OFF
1 1 1 0 ON OFF OFF OFF OFF OFF
1 1 1 1 OFF OFF OFF OFF OFF OFF
EN
Logic Inputs B SP4
to
DP4
SN4
to
DN4
SP5
to
DP5
SN5
to
DN5
SP6
to
DP6
SN6
to
DN6
SELB POSB NEGB
1 0 0 0 OFF OFF OFF OFF ON ON
1 0 0 1 OFF OFF OFF ON OFF OFF
1 0 1 0 OFF OFF ON OFF OFF OFF
1 0 1 1 OFF OFF OFF OFF OFF OFF
1 1 0 0 OFF OFF OFF OFF ON ON
1 1 0 1 OFF ON OFF OFF OFF OFF
1 1 1 0 ON OFF OFF OFF OFF OFF
1 1 1 1 OFF OFF OFF OFF OFF OFF
0 X X X OFF OFF OFF OFF ON ON
0→1 0 0 0 EN transitions from low to high or high to low should occur at all logic inputs low.
1→0 0 0 0
5
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Circuit Pin Layout
TC8020
GN1
GN2
NC
GN3
GP3
NC
SN3
SN6
NC
GP6
GN6
NC
GN5
GN4
SP4
GP5
GP4
SP5
NC
NC
NC
VSUB
NC
SN4
NC
NC
SN5
NC
DP4
DN4
DP6
SP6
SP3
DP3
DN2
DP2
DN6
DN3
DP1
DN1
DP5
DN5
GP2
GP1
SP2
NC
NC
NC
NC
SN2
NC
VSUB
NC
SN1
NC
SP1
MD1715
SELA
POSA
NEGA
VLL/EN
AVDD
AGND
AVSS
SELB
POSB
NEGB
VDD2
OP1A
VDD1
GND
OP2A
VDD2
ON1A
GND
VDD1
ON2A
ON3A
GND
GND
OP3A
VSS
GND
OP3B
VSS
ON3B
GND
VDD2
OP1B
VDD1
GND
OP2B
VDD2
ON1B
GND
VDD1
ON2B
TX(A)
TX(B)
Timing Diagram
tdf
50%
10%
50%
Input
Output
0V
tdr
VDD
trtf
90%
6
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Detail Circuit
VDD2
GN2
VSS
VDD1
High Speed
Gate Buffers
SP1
DP1
100Ω
DN1
SP2
SN2
DP2
DN2
DP3
DN3
OP1 GP1
ON1 GN1
Control
Logic
and
Level
Translation
VLL/EN
SEL
POS
NEG
GND
OP2 GP2
ON2
OP3 GP3
GN3
ON3
SN3
SP3
VPP2
VNN2
VNN1
MD1715
1 OF 2-CH TC8020
6 of 12-FETs
VPP1
VDD1 VDD2
-12V
VSSAVSS
-12V
GND
+12V +12V
AVDD
+12V
PAD PAD
VDD2
VDD1
VDD1
High Speed
Gate Buffers
SN1
7
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Pin Descriptions
Pin # Name Description
1 SELA SEL input logic control for channel A. See logic truth table for details.
2 POSA POS input logic control for channel A. See logic truth table for details.
3 NEGA NEG input logic control for channel A. See logic truth table for details.
4 VLL/EN Logic Hi reference voltage and chip enable input.
5 AVDD Positive supply voltage of analog circuitry. AVDD should be same or higher potential than the
highest voltages of VDD1 or VDD2.
6 AGND Digital Ground.
7 AVSS Negative supply voltage of analog circuitry and connection of IC substrate. Should be at the
same potential as VSS.
8 SELB SEL input logic control for channel B. See logic truth table for details.
9 POSB POS input logic control for channel B. See logic truth table for details.
10 NEGB NEG input logic control for channel B. See logic truth table for details.
11 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B chan-
nels. VDD2 can be at a different voltage than VDD1.
12 OP1B First output P-Channel gate drivers for channel B.
13 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and
B channels. VDD1 can be different voltage than VDD2.
14 GND Power Ground.
15 OP2B Second output P-Channel gate drivers for channel B.
16 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B chan-
nels. VDD2 can be at a different voltage than VDD1.
17 ON1B First output N-Channel gate drivers for channel B.
18 GND Power Ground.
19 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and
B channels. VDD1 can be different voltage than VDD2.
20 ON2B Second output N-Channel gate drivers for channel B.
21 GND Power Ground.
22 ON3B Damping output N-Channel gate drivers for channel B.
23 VSS Negative supply voltage for gate drive of OP3. Should be the same voltage as AVSS.
24 OP3B Damping output P-Channel gate drivers for channel B.
25 GND Power Ground.
26 VSS Negative supply voltage for gate drive of OP3. Should be the same voltage as AVSS.
27 OP3A Damping output P-Channel gate drivers for channel A.
28 GND Power Ground.
29 GND Power Ground.
30 ON3A Damping output N-Channel gate drivers for channel A.
31 ON2A Second output N-Channel gate drivers for channel A.
8
MD1715
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Pin Descriptions (cont.)
Pin # Name Description
32 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and
B channels. VDD1 can be different voltage than VDD2.
33 GND Power Ground.
34 ON1A First output N-Channel gate drivers for channel A.
35 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B chan-
nels. VDD2 can be at a different voltage than VDD1.
36 OP2A Second output P-Channel gate drivers for channel A.
37 GND Power Ground.
38 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and
B channels. VDD1 can be different voltage than VDD2.
39 OP1A First output P-Channel gate drivers for channel A.
40 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B chan-
nels. VDD2 can be at a different voltage than VDD1.
Center
Pad Thermal pad IC substrate, must connect to AVSS externally
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
9
MD1715
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-MD1715
B011612
40-Lead QFN Package Outline (K6)
6.00x6.00mm body, 1.00mm height (max), 0.50mm pitch
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Seating
Plane
Top View
Side View
Bottom View
A
A1
D
E
b
E2
A3
L
L1
View B
View B
1
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
40
1
40
e
D2
θ
Symbol A A1 A3 b D D2 E E2 e L L1 θO
Dimension
(mm)
MIN 0.80 0.00
0.20
REF
0.18 5.85* 1.05 5.85* 1.05
0.50
BSC
0.300.00 0
NOM 0.90 0.02 0.25 6.00 - 6.00 - 0.40- -
MAX 1.00 0.05 0.30 6.15* 4.45 6.15* 4.45 0.500.15 14
JEDEC Registration MO-220, Variation VJJD-6, Issue K, June 2006.
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-40QFNK66X6P050, Version C041009.