Supertex inc. MD1715 Two Channel, Five Level, High Speed Ultrasound Driver IC Features General Description Advanced CMOS technology 4.75 to 12.9V gate drive voltage 2A output source and sink current 6.5ns rise and fall time with 1nF load 10ns propagation delay 2ns matched delay times 12 matched channels 1.8V to 3.3V CMOS logic interface Smart logic threshold Low inductance package The Supertex MD1715, paired with the Supertex TC8020, forms a two channel, five level, high voltage, high speed transmit pulser chip set. The chip set is designed for medical ultrasound imaging applications, but can also be used for metal flaw detection, NonDestructive Testing (NDT), and piezoelectric transducer drivers. The MD1715 is a two channel logic controller circuit with 12 low impedance MOSFET gate drivers. There are two sets of control logic inputs, one each for channels A and B. Each channel consists of three pairs of MOSFET gate drivers. These drivers are designed to match the drive requirements of the Supertex TC8020. Applications The TC8020 is the output stage of the pulser, with six pairs of MOSFETs. Each pair consists of a P-channel and an N-channel MOSFET. They are designed to have the same impedance and can provide typical peak currents of 3.5 amps at 200V. Medical ultrasound imaging Piezoelectric transducer drivers Metal flaw detection Non-Destructive Testing (NDT) Typical Application Circuit +3.3V +12V +12V +12V VLL/EN AVDD VDD1 VDD2 OP1A ON1A OP2A 1.8 to 3.3V CMOS Input Logic 10nF 10nF 10nF GP1 OP3A GP3 NEGA ON3A GN3 OP1B GP4 NEGB ON1B SELB OP2B ON2B OP3B ON3B AGND GND AVSS(SUB) VSS -12V -12V Supertex inc. 10nF 10nF 10nF 10nF SP4 SP1 DP1 DN1 DP2 GN2 POSA POSB SP6 SP3 SP5 SP2 GP2 SELA MD1715 VPP1 GN1 ON2A 10nF VPP2 TX(A) DN2 DP3 TC8020 GN4 DN3 DP4 DN4 GP5 DP5 GN5 DN5 GP6 DP6 GN6 DN6 PAD SN6 SN3 SN5 SN2 SN4 SN1 VNN2 VNN1 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com TX(B) MD1715 Ordering Information Package Option 40-Lead QFN Device 6.00x6.00mm body 1.0mm height (max) 0.50mm pitch MD1715 MD1715K6-G -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Pin Configuration Parameter 40 Value GND and AGND, Ground 1 0V VLL logic input pin -0.5V to +5.5V AVDD, VDD1, positive gate drive supply -0.5V to +14.5V VDD2, positive gate drive supply -0.5V to +14.5V AVSS, VSS, negative gate drive supply -14.5V to +0.5V Storage temperature -65C to 150C Power dissipation* 1.3W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 40-Lead QFN (K6) (top view) Package Marking MD1715 LLLLLL YYWW AAA CCC * 1.0oz 4-layer 3x4" PCB L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging Package may or may not include the following marks: Si or 40-Lead QFN (K6) Operating Supply Voltages Sym Parameter Min Typ Max Logic supply 1.8 3.3 3.6 V --- Positive analog supply 8.0 - 12.9 V AVDD (VDD1 or VDD2) VDD2, VDD1 Positive gate drive supply 4.75 - 12.9 V --- AVSS, VSS -12.9 - -4.75 V --- VLL AVDD Negative gate drive supply Units Conditions Operating Supply Current (Over operating conditions unless otherwise specified, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25C) Sym IVLL Parameter Min Logic reference current Typ Max 10 A IAVDDQ AVDD power down current - 0.4 - IVSSQ VVSS power down current - 0.1 - IVDD1Q VDD1 power down current - 10 25 IVDD2Q VDD2 power down current - 10 25 Supertex inc. Units Conditions VLL = 3.3V mA EN = 0, all inputs Low. A 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 MD1715 Operating Supply Current (Over operating conditions unless otherwise specified, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25C) Sym Parameter Min Typ Max IAVDDEN Units Conditions AVDD power up current - 2.0 3.0 mA IVSSEN VSS power up current - 0.7 1.0 mA IVDD1EN VDD1 power up current - 10 - A IVDD2EN VDD2 power up current - 10 - A IAVDDCW AVDD CW 5MHz current - 10 - IVSSCW VSS CW 5MHz current - 5.0 - IVDD1CW VDD1 CW 5MHz current - 25 IVDD2CW VDD2 CW 5MHz current - 25 EN = 1, all inputs low. mA A&B channel on at 5.0MHz no load, VDD1 = 12V, VDD2 = 5.0V - mA A&B channel on at 5.0MHz no load, VDD1 = 5.0V, VDD2 = 12V - mA A&B channel on at 5.0MHz no load, VDD1 = 12V, VDD2 = 5.0V AC Electrical Characteristics (Over operating conditions unless otherwise specified, VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = -12V, TA = 25C) Sym Parameter Min Typ Max Units Conditions tirf Input rise & fall time - - 10 ns Logic input edge speed requirement tr Output rise time - 6.5 - ns 1nF load, see timing diagram, input signal rise/fall time 2.0ns tf Output fall time - 6.5 - ns --- tdr Output rise delay - 10 - ns --- tdf Output fall delay - 10 - ns --- |tr - tf| Rise and fall time matching - 1.0 - - For each channel |tdr - tdf| Propagation delay matching - 1.0 - - --- tdm Delay time matching - 2.0 - ns Ch to Ch and Device to Device tj Output jitter - 20 - ps VDD = 10V tEN_ON IC enable time - 25 50 s --- tEN_OFF IC disable time - 0.5 2.0 s --- HD2 2 harmonic distortion -40 - - dB --- Min Typ Max nd P-Channel Gate Driver Outputs Sym Parameter RSINK Output sink resistance - 5.0 6.0 ISINK = 100mA RSOURCE Output source resistance - 5.0 6.0 ISOURCE = 100mA ISINK Peak output sink current 1.7 2.0 - A --- Peak output source current 1.7 2.0 - A --- ISOURCE Supertex inc. Units Conditions 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 MD1715 N-Channel Gate Driver Outputs Sym Parameter Min Typ Max RSINK Output sink resistance - 5.0 6.0 ISINK = 100mA RSOURCE Output source resistance - 5.0 6.0 ISOURCE = 100mA ISINK Peak output sink current 1.7 2.0 - A --- Peak output source current 1.7 2.0 - A --- Min Typ Max ISOURCE Units Conditions Logic Inputs Sym Parameter Units Conditions VENL Chip disable low voltage 0 - 0.3 V VLL/EN is a dual function pin VIH Input logic high voltage 0.8VLL - VLL V --- VIL Input logic low voltage 0 - 0.2VLL V --- IIH Input logic high current - - 1.0 A --- IIL Input logic low current -1.0 - - A --- Truth Table for Channels A and B Logic Inputs A SELA POSA NEGA SP1 to DP1 1 0 0 0 OFF OFF OFF OFF ON ON 1 0 0 1 OFF OFF OFF ON OFF OFF 1 0 1 0 OFF OFF ON OFF OFF OFF 1 0 1 1 OFF OFF OFF OFF OFF OFF 1 1 0 0 OFF OFF OFF OFF ON ON 1 1 0 1 OFF ON OFF OFF OFF OFF 1 1 1 0 ON OFF OFF OFF OFF OFF 1 1 1 1 OFF OFF OFF OFF OFF OFF SN4 to DN4 SP5 to DP5 SN5 to DN5 SP6 to DP6 SN6 to DN6 EN SN1 to DN1 SP2 to DP2 SN2 to DN2 SP3 to DP3 SN3 to DN3 SELB POSB NEGB SP4 to DP4 1 0 0 0 OFF OFF OFF OFF ON ON 1 0 0 1 OFF OFF OFF ON OFF OFF 1 0 1 0 OFF OFF ON OFF OFF OFF 1 0 1 1 OFF OFF OFF OFF OFF OFF 1 1 0 0 OFF OFF OFF OFF ON ON 1 1 0 1 OFF ON OFF OFF OFF OFF 1 1 1 0 ON OFF OFF OFF OFF OFF 1 1 1 1 OFF OFF OFF OFF OFF OFF 0 X X X OFF OFF OFF OFF ON ON 01 0 0 0 10 0 0 0 EN Logic Inputs B Supertex inc. EN transitions from low to high or high to low should occur at all logic inputs low. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 MD1715 ON2A VDD1 GND ON1A VDD2 OP2A GND VDD1 OP1A VDD2 NC NC NC SP2 SP1 VSUB NC NC SN1 NC SN2 NC GP1 GP2 Circuit Pin Layout GN1 DN1 GN2 DP1 NC DN2 DP2 SELA ON3A POSA GND GN3 NEGA GND GP3 DN3 OP3A NC DP3 VLL/EN MD1715 TC8020 GP6 DP6 POSB ON3B GN6 DN5 NEGB GND NC DP5 SP3 SP6 DN6 NC NC SP5 NC SP4 NC VSUB NC SN4 NC SN5 DP4 NC DN4 GN4 GP4 GN5 GP5 OP1B VDD2 ON2B VSS VDD1 SELB GND NC ON1B OP3B VDD2 AVSS OP2B SN6 GND SN3 GND VDD1 VSS AVDD AGND Timing Diagram Input 50% 50% tdf tdr VDD 90% Output 0V Supertex inc. TX(A) 10% tr tf 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 TX(B) MD1715 Detail Circuit +12V VDD1 +12V AVDD +12V VDD2 VPP1 SP1 VDD2 OP1 GP1 DP1 VDD2 DN1 ON1 GN1 VNN1 SN1 High Speed Gate Buffers VLL/EN VPP2 SP2 VDD1 OP2 SEL POS NEG Control Logic and Level Translation GP2 DP2 VDD1 DN2 ON2 100 GN2 VNN2 SN2 GND High Speed Gate Buffers OP3 SP3 GP3 DP3 VSS VDD1 DN3 ON3 SN3 MD1715 1 OF 2-CH GND AVSS PAD -12V Supertex inc. GN3 VSS -12V TC8020 6 of 12-FETs PAD 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 6 MD1715 Pin Descriptions Pin # Name Description 1 SELA SEL input logic control for channel A. See logic truth table for details. 2 POSA POS input logic control for channel A. See logic truth table for details. 3 NEGA NEG input logic control for channel A. See logic truth table for details. 4 VLL/EN 5 AVDD Positive supply voltage of analog circuitry. AVDD should be same or higher potential than the highest voltages of VDD1 or VDD2. 6 AGND Digital Ground. 7 AVSS Negative supply voltage of analog circuitry and connection of IC substrate. Should be at the same potential as VSS. 8 SELB SEL input logic control for channel B. See logic truth table for details. 9 POSB POS input logic control for channel B. See logic truth table for details. 10 NEGB NEG input logic control for channel B. See logic truth table for details. 11 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B channels. VDD2 can be at a different voltage than VDD1. 12 OP1B First output P-Channel gate drivers for channel B. 13 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and B channels. VDD1 can be different voltage than VDD2. 14 GND Power Ground. 15 OP2B Second output P-Channel gate drivers for channel B. 16 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B channels. VDD2 can be at a different voltage than VDD1. 17 ON1B First output N-Channel gate drivers for channel B. 18 GND Power Ground. 19 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and B channels. VDD1 can be different voltage than VDD2. 20 ON2B Second output N-Channel gate drivers for channel B. 21 GND Power Ground. 22 ON3B Damping output N-Channel gate drivers for channel B. 23 VSS 24 OP3B Damping output P-Channel gate drivers for channel B. 25 GND Power Ground. 26 VSS Negative supply voltage for gate drive of OP3. Should be the same voltage as AVSS. 27 OP3A Damping output P-Channel gate drivers for channel A. 28 GND Power Ground. 29 GND Power Ground. 30 ON3A Damping output N-Channel gate drivers for channel A. 31 ON2A Second output N-Channel gate drivers for channel A. Logic Hi reference voltage and chip enable input. Negative supply voltage for gate drive of OP3. Should be the same voltage as AVSS. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 7 MD1715 Pin Descriptions (cont.) Pin # Name Description 32 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and B channels. VDD1 can be different voltage than VDD2. 33 GND Power Ground. 34 ON1A First output N-Channel gate drivers for channel A. 35 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B channels. VDD2 can be at a different voltage than VDD1. 36 OP2A Second output P-Channel gate drivers for channel A. 37 GND Power Ground. 38 VDD1 Positive supply voltage of the gate drivers for the output stage for OP2, ON2, ON3 in A and B channels. VDD1 can be different voltage than VDD2. 39 OP1A First output P-Channel gate drivers for channel A. 40 VDD2 Positive supply voltage of the gate drivers for the output stage OP1, ON1 in A and B channels. VDD2 can be at a different voltage than VDD1. Center Pad Thermal pad IC substrate, must connect to AVSS externally Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 8 MD1715 40-Lead QFN Package Outline (K6) 6.00x6.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 40 Note 1 (Index Area D/2 x E/2) 40 1 1 e Note 1 (Index Area D/2 x E/2) E2 E b View B Top View Bottom View Note 3 A A3 A1 L Seating Plane L1 Note 2 Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.18 5.85* 1.05 5.85* 1.05 0.25 6.00 - 6.00 - 0.30 6.15* 4.45 6.15* 4.45 0.50 BSC L L1 O 0.30 0.00 0 0.40 - - 0.50 0.15 14 JEDEC Registration MO-220, Variation VJJD-6, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-40QFNK66X6P050, Version C041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. (c)2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-MD1715 B011612 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com