© Semiconductor Components Industries, LLC, 2010
December, 2010 Rev. 13
1Publication Order Number:
NCP1216/D
NCP1216, NCP1216A
PWM Current-Mode
Controller for High-Power
Universal Off-Line Supplies
Housed in a SOIC8 or PDIP7 package, the NCP1216 represents
an enhanced version of NCP1200 based controllers. Due to its high
drive capability, NCP1216 drives large gatecharge MOSFETs, which
together with internal ramp compensation and builtin frequency
jittering, ease the design of modern ACDC adapters.
With an internal structure operating at different fixed frequencies,
the controller supplies itself from the highvoltage rail, avoiding the
need of an auxiliary winding. This feature naturally eases the designer
task in some particular applications, e.g. battery chargers or TV sets.
Currentmode control also provides an excellent input audio
susceptibility and inherent pulsebypulse control. Internal ramp
compensation easily prevents subharmonic oscillations from taking
place in continuous conduction mode designs.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the socalled
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1216 features an efficient protective circuitry, which in
presence of an over current condition disables the output pulses while
the device enters a safe burst mode, trying to restart. Once the default
has gone, the device autorecovers.
Features
No Auxiliary Winding Operation
CurrentMode Control with Adjustable SkipCycle Capability
Internal Ramp Compensation
Limited Duty Cycle to 50% (NCP1216A Only)
Internal 1.0 ms SoftStart (NCP1216A Only)
BuiltIn Frequency Jittering for Better EMI Signature
AutoRecovery Internal Output ShortCircuit Protection
Extremely Low NoLoad Standby Power
500 mA Peak Current Capability
Fixed Frequency Versions at 65 kHz, 100 kHz, 133 kHz
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient and AC Analysis
PintoPin Compatible with NCP1200 Series
These are PbFree and HalideFree Devices
Typical Applications
High Power ACDC Converters for TVs, SetTop Boxes, etc.
Offline Adapters for Notebooks
Telecom DCDC Converters
All Power Supplies
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
PDIP7
P SUFFIX
CASE 626B
P1216XXXX
AWL
YYWWG
1
XXXX = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= PbFree Package
PIN CONNECTIONS
1
Adj 8HV
2
FB
3
CS
4
Gnd
7NC
6VCC
5Drv
See detailed ordering and shipping information in the ordering
information section on page 16 of this data sheet.
ORDERING INFORMATION
See detailed device marking information in the ordering
information section on page 16 of this data sheet.
DEVICE MARKING INFORMATION
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16XXX
ALYW
1
8
1
8
G
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2
Universal Input
Fosc = 35kHz HV
Vcc
Drv
GND
Adj
FB
CS
NCP1216
EMI
Filter
1
2
3
45
6
7
8
Rsense
Rcomp
+
+
+
*See Application Section
Figure 1. Typical Application Example
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Pin Description
1 Adj Adjust the Skipping Peak Current This pin lets you adjust the level at which the cycle skipping process
takes place. Shorting this pin to ground, permanently disables the skip
cycle feature.
2 FB Sets the Peak Current Setpoint By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand.
3 CS Current Sense Input This pin senses the primary current and routes it to the internal com-
parator via an L.E.B. By inserting a resistor in series with the pin, you
control the amount of ramp compensation you need.
4 GND IC Ground
5 Drv Driving Pulses The driver’s output to an external MOSFET.
6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 22 mF.
7 NC This unconnected pin ensures adequate creepage distance.
8 HV Generates the VCC from the Line Connected to the highvoltage rail, this pin injects a constant current
into the VCC bulk capacitor.
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Q
Set
Reset
1 V
HV1
2
3
45
6
7
8
Drv
GND
NC
Current
Sense
Adj
FB
Skip Cycle Comparator
1.1 V
Overload?
Fault Duration
20 k
19 k
Clock Jittering
57 k
25 k
96 k
25 k
5 V
Figure 2. Internal Circuit Architecture
+
+
Pullup Resistor
UVLO High and Low
Internal Regulator
HV Current Source
Q FlipFlop
DCmax = 75%
Reset
65 kHz
100 kHz
133kHz
Ramp
Compensation
+Vref
220 ns
L.E.B
$500 mA
VCC
Internal VCC
1 ms SS*
* Available for ”A” version only.
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage, VCC Pin VCC 16 V
Maximum Voltage on Low Power Pins (except Pin 8 and Pin 6) 0.3 to 10 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF500 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded 450 V
Minimum Operating Voltage on Pin 8 (HV) 28 V
Maximum Current into all Pins except VCC (Pin 6) and HV (Pin 8) when 10 V ESD Di-
odes are Activated
5.0 mA
Thermal Resistance JunctiontoAir, PDIP7 Version
Thermal Resistance JunctiontoAir, SOIC8 Version
RqJA
RqJA
100
178
°C/W
Maximum Junction Temperature TJMAX 150 °C
Temperature Shutdown TSD 155 °C
Hysteresis in Shutdown 30 °C
Storage Temperature Range 60 to +150 °C
ESD Capability, HBM Model (All Pins except VCC and HV) 2.0 kV
ESD Capability, Machine Model 200 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Maximum TJ = 150°C,
VCC = 11 V unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
DYNAMIC SELFSUPPLY
VCC Increasing Level at which the Current Source Turns Off 6 VCCOFF 11.2 12.2 13.4
(Note 1)
V
VCC Decreasing Level at which the Current Source Turns On 6 VCCON 9.2 10.0 11.0
(Note 1)
V
VCC Decreasing Level at which the Latchoff Phase Ends 6 VCClatch 5.6 V
Internal IC Consumption, No Output Load on Pin 5, FSW = 65 kHz 6 ICC1 990 1110
(Note 2)
mA
Internal IC Consumption, No Output Load on Pin 5, FSW = 100 kHz 6 ICC1 1025 1180
(Note 2)
mA
Internal IC Consumption, No Output Load on Pin 5, FSW = 133 kHz 6 ICC1 1060 1200
(Note 2)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 65 kHz 6 ICC2 1.7 2.0
(Note 2)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 100 kHz 6 ICC2 2.1 2.4
(Note 2)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 133 kHz 6 ICC2 2.4 2.9
(Note 2)
mA
Internal IC Consumption, Latchoff Phase, VCC = 6.0 V NCP1216
NCP1216A
6 ICC3 250
320
mA
INTERNAL STARTUP CURRENT SOURCE (TJ > 0°C)
Highvoltage Current Source, VCC = 10 V 8 IC1 4.9
(Note 3)
8.0 11 mA
Highvoltage Current Source, VCC = 0 V 8 IC2 9.0 mA
DRIVE OUTPUT
Output Voltage Risetime @ CL = 1.0 nF, 1090% of a 12 V Output Signal 5 Tr60 ns
Output Voltage Falltime @ CL = 1.0 nF, 1090% of a 12 V Output Signal 5 Tf20 ns
Source Resistance 5 ROH 15 20 35 W
Sink Resistance 5 ROL 5.0 10 18 W
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB 0.02 mA
Maximum Internal Current Setpoint 3 ILimit 0.93 1.08 1.14 V
Default Internal Current Setpoint for Skip Cycle Operation 3 ILskip 330 mV
Propagation Delay from Current Detection to Gate OFF State 3 TDEL 80 130 ns
Leading Edge Blanking Duration 3 TLEB 220 ns
1. VCCOFF and VCCON minmax always ensure an hysteresis of 2.0 V.
2. Maximum value at TJ = 0°C.
3. Minimum value for TJ = 125°C.
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ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Maximum
TJ = 150°C, VCC = 11 V unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Oscillation Frequency, 65 kHz Version fOSC 58.5 65 71.5 kHz
Oscillation Frequency, 100 kHz Version fOSC 90 100 110 kHz
Oscillation Frequency, 133 kHz Version fOSC 120 133 146 kHz
Builtin Frequency Jittering in Percentage of fOSC fjitter ±4.0 %
Maximum DutyCycle NCP1216
NCP1216A
Dmax 69
42
75
46.5
81
50
%
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Internal Pullup Resistor 2 Rup 20 kW
Pin 2 (FB) to Internal Current Setpoint Division Ratio Iratio 3.3
SKIP CYCLE GENERATION
Default Skip Mode Level 1 Vskip 0.9 1.1 1.26 V
Pin 1 Internal Output Impedance 1 Zout 25 kW
INTERNAL RAMP COMPENSATION
Internal Ramp Level @ 25°C (Note 4) 3 Vramp 2.6 2.9 3.2 V
Internal Ramp Resistance to CS Pin 3 Rramp 19 kW
4. A 1.0 MW resistor is connected to the ground for the measurement.
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TEMPERATURE (°C)
Figure 3. High Voltage Pin Leakage Current vs.
Temperature
0
10
20
30
40
50
25 0 25 50 75 100 125
HV PIN LEAKAGE CURRENT @ 500 V
(mA)
Figure 4. VCCOFF vs. Temperature
11.0
11.5
12.0
12.5
13.0
13.5
14.0
25 0 25 50 75 100 12
5
TEMPERATURE (°C)
VCCOFF (V)
Figure 5. VCCON vs. Temperature
9.0
9.5
10.0
10.5
11.0
11.5
12.0
25 0 25 50 75 100 125
VCCON (V)
TEMPERATURE (°C)
500
600
700
800
900
1000
1100
1200
1300
1400
25 0 25 50 75 100 12
5
TEMPERATURE (°C)
ICC1 (mA)
Figure 6. ICC1 (@ VCC = 11 V) vs. Temperature
65 kHz
133 kHz
100 kHz
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
25 0 25 50 75 100 125
TEMPERATURE (°C)
ICC2 (mA)
133 kHz
100 kHz
65 kHz
Figure 7. ICC2 vs. Temperature
50
70
90
110
130
150
25 0 25 50 75 100 125
133 kHz
100 kHz
65 kHz
FOSC (kHz)
TEMPERATURE (°C)
Figure 8. Switching Frequency vs.
Temperature
TYPICAL CHARACTERISTICS
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5.30
5.40
5.50
5.60
5.70
5.80
5.90
25 0 25 50 75 100 125
TEMPERATURE (°C)
VCClatch (V)
Figure 9. VCClatch vs. Temperature Figure 10. ICC3 vs. Temperature
0
100
200
300
400
25 0 25 50 75 100 125
TEMPERATURE (°C)
ICC3 (mA)
0
5
10
15
20
25
30
25 0 25 50 75 100 125
DRIVER RESISTANCE (W)
TEMPERATURE (°C)
Figure 11. Drive Sink and Source Resistance
vs. Temperature
Source
Sink
0.93
0.98
1.03
1.08
1.13
25 0 25 50 75 100 125
TEMPERATURE (°C)
CURRENT SENSE LIMIT (V)
Figure 12. Current Sense Limit vs. Temperature
25 0 25 50 75 100 125
1.00
1.05
1.10
1.15
1.20
TEMPERATURE (°C)
Vskip (V)
Figure 13. Vskip vs. Temperature
72.0
72.5
73.0
73.5
74.0
74.5
75.0
25 0 25 50 75 100 12
5
TEMPERATURE (°C)
DUTY CYCLE (%)
Figure 14. NCP1216 Max DutyCycle vs.
Temperature
50
150
250
350
NCP1216A
NCP1216
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2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
25 0 25 50 75 100 125
TEMPERATURE (°C)
Vramp (V)
Figure 15. NCP1216A Max DutyCycle vs.
Temperature
2
4
6
8
10
12
14
25 0 25 50 75 100 125
IC1 (mA)
TEMPERATURE (°C)
Figure 16. Vramp vs. Temperature
Figure 17. High Voltage Current Source
(@ VCC = 10 V) vs. Temperature
45.0
45.5
46.0
46.5
47.0
48.5
49.0
25 0 25 50 75 100 125
TEMPERATURE (°C)
DUTY CYCLE (%)
47.5
48.0
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APPLICATION INFORMATION
Introduction
The NCP1216 implements a standard current mode
architecture where the switchoff event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part count is the key parameter,
particularly in lowcost ACDC adapters, TV power
supplies etc. Due to its highperformance HighVoltage
technology, the NCP1216 incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, lowpass filter and
selfsupply. This later point emphasizes the fact that ON
Semiconductor’s NCP1216 does NOT need an auxiliary
winding to operate: the product is naturally supplied from
the highvoltage rail and delivers a VCC to the IC. This
system is called the Dynamic SelfSupply (DSS):
Dynamic SelfSupply (DSS): Due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductors NCP1216 allows for a direct pin
connection to the highvoltage DC rail. A dynamic current
source charges up a capacitor and thus provides a fully
independent VCC level to the NCP1216. As a result, there is
no need for an auxiliary winding whose management is
always a problem in variable output voltage designs (e.g.
battery chargers).
Adjustable Skip Cycle Level: By offering the ability to tailor
the level at which the skip cycle takes place, the designer can
make sure that the skip operation only occurs at low peak
current. This point guarantees a noisefree operation with
cheap transformers. Skip cycle offers a proven mean to
reduce the standby power in no or light loads situations.
Internal Frequency Dithering for Improved EMI
Signature: By modulating the internal switching frequency
with the DSS VCC ripple, natural energy spread appears and
softens the controller’s EMI signature.
Wide Switching Frequency Offered with Different
Options (65 kHz 100 kHz 133 kHz): Depending on the
application, the designer can pick up the right device to help
reducing magnetics or improve the EMI signature before
reaching the 150 kHz starting point.
Ramp Compensation: By inserting a resistor between the
Current Sense (CS) pin and the actual sense resistor, it
becomes possible to inject a given amount of ramp
compensation since the internal sawtooth clock is routed to
the CS pin. Subharmonic oscillations in Continuous
Conduction Mode (CCM) can thus be compensated via a
single resistor.
Over Current Protection (OCP): By continuously
monitoring the FB line activity, NCP1216 enters burst mode
as soon as the power supply undergoes an overload. The
device enters a safe low power operation, which prevents
from any lethal thermal runaway. As soon as the default
disappears, the power supply resumes operation. Unlike
other controllers, overload detection is performed
independently of any auxiliary winding level. In presence of
a bad coupling between both power and auxiliary windings,
the short circuit detection can be severely affected. The DSS
naturally shields you against these troubles.
Wide DutyCycle Operation: Wide mains operation requires
a large dutycycle excursion. The NCP1216 can go up to 75%
typically. For Continuous Conduction Mode (CCM)
applications, the internal ramp compensation lets you fight
against subharmonic oscillations.
Low Standby Power: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less efficient
when the output power demand diminishes. By skipping
unnecessary switching cycles, the NCP1216 drastically
reduces the power wasted during light load conditions. In
noload conditions, the NPC1216 allows the total standby
power to easily reach next International Energy Agency
(IEA) recommendations.
No Acoustic Noise While Operating: Instead of skipping
cycles at high peak currents, the NCP1216 waits until the
peak current demand falls below a useradjustable 1/3 of the
maximum limit. As a result, cycle skipping can take place
without having a singing transformer, one can thus select
cheap magnetic components free of noise problems.
External MOSFET Connection: By leaving the external
MOSFET external to the IC, you can select avalanche proof
devices, which in certain cases (e.g. low output powers), let
you work without an active clamping network. Also, by
controlling the MOSFET gate signal flow; you have an
option to slow down the device commutation, therefore
reducing the amount of ElectroMagnetic Interference
(EMI).
SPICE Model: A dedicated model to run transient
cyclebycycle simulations is available but also an
averaged version to help you closing the loop.
Readytouse templates can be downloaded in OrCAD’s
PSpice and INTUSOFT’s IsSpice from ON Semiconductor
web site, in the NCP1216 related section.
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Dynamic SelfSupply
The DSS principle is based on the charge/discharge of the
VCC bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation with a bunch
of simple logical equations:
POWERON: If VCC < VCCOFF then the Current Source
is ON, no output pulses
If VCC decreasing > VCCON then the Current Source is
OFF, output is pulsing
If VCC increasing < VCCOFF then the Current Source is
ON, output is pulsing
Typical values are: VCCOFF = 12.2 V, VCCON = 10 V
To better understand the operational principle, Figure 18
offers the necessary light:
10 30 50 70 90
Figure 18. The Charge/Discharge Cycle Over a
10 mF VCC Capacitor
VCCOFF = 12.2 V
VCCON = 10 V
Vripple = 2.2 V
ON, I = 8 mA OFF, I = 0 mA
Output Pulse
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a 600 V 10 A MOSFET featuring a 30 nC Qg, then we
can compute the resulting average consumption supported
by the DSS which is:
Itotal [Fsw Qg)ICC1.(eq. 1)
The total IC heat dissipation incurred by the DSS only is
given by:
Itotal Vpin8.(eq. 2)
Suppose that we select the NCP1216P065 with the above
MOSFET, the total current is
(30 n 65 k) )900 m+2.9 mA. (eq. 3)
Supplied from a 350 VDC rail (250 VAC), the heat
dissipated by the circuit would then be:
350 V 2.9 mA +1W (eq. 4)
As you can see, it exists a tradeoff where the dissipation
capability of the NCP1216 fixes the maximum Qg that the
circuit can drive, keeping its dissipation below a given
target. Please see the “Power Dissipation” section for a
complete design example and discover how a resistor can
help to heal the NCP1216 heat equation.
Application note AND8069/D details tricks to widen the
NCP1216 driving implementation, in particular for large Qg
MOSFETs. This document can be downloaded at
www.onsemi.com/pub/Collateral/AND8069D.PDF.
Ramp Compensation
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a dutycycle
greater than 50%. To lower the current loop gain, one usually
injects between 50% and 100% of the inductor downslope.
Figure 19 depicts how internally the ramp is generated:
CS
L.E.B
19 k
2.9V
0V
Figure 19. Inserting a Resistor in Series with the
Current Sense Information brings Ramp
Compensation
+
From Setpoint
Rsense
Rcomp
DCmax = 75°C
In the NCP1216, the ramp features a swing of 2.9 V with
a Duty cycle max at 75%. Over a 65 kHz frequency, it
corresponds to a
2.9
0.75 65 kHz +251 mVńms ramp. (eq. 5)
In our FLYBACK design, let’s suppose that our primary
inductance Lp is 350 mH, delivering 12 V with a Np : Ns
ratio of 1:0.1. The OFF time primary current slope is thus
given by:
Vout )Vf
Lp Np
Ns+371 mAńmsor37mVńms(eq. 6)
when projected over an Rsense of 0.1 W, for instance. If we
select 75% of the downslope as the required amount of
ramp compensation, then we shall inject 27 mV/ms. Our
internal compensation being of 251 mV/ms, the divider ratio
(divratio) between Rcomp and the 19 kW is 0.107. A few lines
of algebra to determine Rcomp:
19 k divratio
1*divratio +2.37 kW(eq. 7)
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. NCP1216 offers a $4% deviation of
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the nominal switching frequency whose sweep is
synchronized with the VCC ripple. For instance, with a 2.2 V
peaktopeak ripple, the NCP1216P065 frequency will
equal 65 kHz in the middle of the ripple and will increase as
VCC rises or decrease as VCC ramps down. Figure 20
portrays the behavior we have adopted:
Figure 20. VCC Ripple is Used to Introduce a
Frequency Jittering on the Internal Oscillator
Sawtooth
65 kHz
68 kHz
VCCOFF
VCC Ripple
VCCON
62 kHz
Skipping Cycle Mode
The NCP1216 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the socalled skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 22).
Suppose we have the following component values:
Lp, primary inductance = 350 mH
Fsw, switching frequency = 65 kHz
Ip skip = 600 mA (or 333 mV / Rsense)
The theoretical power transfer is therefore:
1
2 Lp Ip2 Fsw +4W. (eq. 8)
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power
transfer is:
4 0.1 +400 mW. (eq. 9)
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
Figure 21.
4.2 V, FB Pin Open
3.2 V, Upper
Dynamic Range
Normal Current Mode Operation
Skip Cycle Operation
IpMIN = 333 mV / Rsense
FB
1 V
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/Rsense. When
the IC enters the skip cycle mode, the peak current cannot go
below Vpin1 / 3.3. The user still has the flexibility to alter this
1.0 V by either shunting pin 1 to ground through a resistor
or raising it through a resistor up to the desired level.
Grounding pin 1 permanently invalidates the skip cycle
operation.
Figure 22. Output Pulses at Various Power Levels
(X = 5 ms/div) P1 < P2 < P3
Power P1
Power
P2
Power
P3
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315.4U 882.7U 1.450M 2.017M 2.585M
300
200
100
0
Figure 23. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise Free Operation
Skip Cycle
Current Limit
Max Peak
Current
NonLatching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 24 depicts the application example:
Figure 24. Another Way of Shutting Down the IC
without a Definitive Latchoff State
8
7
6
5
1
2
3
4
Q1
ON/OFF
A full latching shutdown, including overtemperature
protection, is described in application note AND8069/D.
Power Dissipation
The NCP1216 is directly supplied from the DC rail
through the internal DSS circuitry. The current flowing
through the DSS is therefore the direct image of the
NCP1216 current consumption. The total power dissipation
can be evaluated using:
(VHVDC *11 V) ICC2 (eq. 10)
which is, as we saw, directly related to the MOSFET Qg. If
we operate the device on a 90250 VAC rail, the maximum
rectified voltage can go up to 350 VDC. However, as the
characterization curves show, the current consumption
drops at a higher junction temperature, which quickly occurs
due to the DSS operation. In our example, at
Tambient = 50°C, ICC2 is measured to be 2.9 mA with a
10 A / 600 V MOSFET. As a result, the NCP1216 will
dissipate from a 250 VAC network,
350 V 2.9 mA@TA+50 C +1W (eq. 11)
°
The PDIP7 package offers a junctiontoambient thermal
resistance RqJA of 100°C/W. Adding some copper area
around the PCB footprint will help decreasing this number:
12 mm x 12 mm to drop RqJA down to 75°C/W with 35 m
copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m
copper thickness (2 oz.). For a SOIC8, the original
178°C/W will drop to 100°C/W with the same amount of
copper. With this later PDIP7 number, we can compute the
maximum power dissipation that the package accepts at an
ambient of 50°C:
Pmax +TJmax *TAmax
RqJ*A+1W (eq. 12)
which barely matches our previous budget. Several
solutions exist to help improving the situation:
1. Insert a Resistor in Series with Pin 8: This resistor will
take a part of the heat normally dissipated by the NCP1216.
Calculations of this resistor imply that Vpin8 does not drop
below 30 V in the lowest mains conditions. Therefore, Rdrop
can be selected with:
Rdrop vVbulkmin *50 V
8mA (eq. 13)
In our case, Vbulk minimum is 120 VDC, which leads to a
dropping resistor of 8.7 kW. With the above example in
mind, the DSS will exhibit a dutycycle of:
2.9 mAń8mA+36% (eq. 14)
By inserting the 8.7 kW resistor, we drop
8.7 kW*8mA+69.6 V (eq. 15)
during the DSS activation. The power dissipated by the
NCP1216 is therefore:
Pinstant *DSS
duty *cycle +
(eq. 16)
(350 *69) * 8 m * 0.36 +800 mW
We can pass the limit and the resistor will dissipate
(eq. 17)
1W*800 mW +200 mW
or
(eq. 18)
pdrop +692
8.7 k *0.36
2. Select a MOSFET with a Lower Qg: Certain MOSFETs
exhibit different total gate charges depending on the
technology they use. Careful selection of this component
can help to significantly decrease the dissipated heat.
NCP1216, NCP1216A
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13
3. Implement Figure 3, from AN8069/D, Solution: This is
another possible option to keep the DSS functionality (good
shortcircuit protection and EMI jittering) while driving any
types of MOSFETs. This solution is recommended when the
designer plans to use SOIC8 controllers.
4. Connect an Auxiliary Winding: If the mains conditions
are such that you simply can’t match the maximum power
dissipation, then you need to connect an auxiliary winding
to permanently disconnect the startup source.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true shortcircuit protection. A
shortcircuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation, NCP1216
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low dutycycle. The system autorecovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The timeout used by this IC
works with the VCC decoupling capacitor: as soon as the
VCC decreases from the VCCOFF level (typically 12.2 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCCON level is
reached, the controller stops the driving pulses, prevents the
selfsupply current source to restart and puts all the circuitry
in standby, consuming as little as 350 mA typical (ICC3
parameter). As a result, the VCC level slowly discharges
toward 0 V. When this level crosses 5.6 V typical, the
controller enters a new startup phase by turning the current
source on: VCC rises toward 12.2 V and again delivers
output pulses at the VCCOFF crossing point. If the fault
condition has been removed before VCCON approaches,
then the IC continues its normal operation. Otherwise, a new
fault cycle takes place. Figure 25 shows the evolution of the
signals in presence of a fault.
Figure 25.
Latchoff
Phase
Time
Time
Time
Fault is
Relaxed
Regulation
Occurs Here
VCC
12.2 V
10 V
5.6 V
Fault Occurs Here
Startup Phase
Internal
Fault Flag
Driver
Pulses
Drv
Driver
Pulses
VCCOFF = 12.2 V
VCCON = 10 V
VCClatch = 5.6 V
If the fault is relaxed during the VCC natural fall down
sequence, the IC automatically resumes.
If the fault still persists when VCC reached VCCON, then the
controller cuts everything off until recovery.
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12.2 V to 10 V. The required time
NCP1216, NCP1216A
http://onsemi.com
14
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12.2 V
to 10 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a VCC fall time of 10 ms could be well
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 2.9 mA, we can calculate
the required capacitor using the following formula:
Dt+DV·C
i(eq. 19)
with DV = 2.2 V. Then for a wanted Dt of 30 ms, C equals
39.5 mF or a 68 mF for a standard value (including ±20%
dispersions). When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
350 mA typical. This happens at VCC = 10 V and it remains
stuck until VCC reaches 5.6 V: we are in latchoff phase.
Again, using the selected 68 mF and 350 mA current
consumption, this latchoff phase lasts: 780 ms.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designers duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between VCC and GND. If the current sense pin is
often the seat of such spurious signals, the highvoltage pin
can also be the source of problems in certain circumstances.
During the turnoff sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its VCC capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
coefficient Q of the resonating network formed by Lp and
Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge, (Q = I * t),
immediately latches the controller that brutally discharges
its VCC capacitor. If this VCC capacitor is of sufficient value,
its stored energy damages the controller. Figure 26 depicts
a typical negative shot occurring on the HV pin where the
brutal VCC discharge testifies for latchup.
Figure 26. A Negative Spike Takes Place on the Bulk Capacitor at the Switchoff Sequence
VCC
5 V/DIV
10 ms/DIV Vlatch
1 V/DIV
0
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the highvoltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 27). Please note that the negative
spike is clamped to (2 * Vf) due to the diode bridge. Also,
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
Another option (Figure 28) consists in wiring a diode
from VCC to the bulk capacitor to force VCC to reach
VCCON sooner and thus stops the switching activity before
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
NCP1216, NCP1216A
http://onsemi.com
15
Figure 27. Figure 28.
A simple resistor in series avoids any latchup in the controller
or one diode forces VCC to reach VCCON sooner.
D3
1N4007
1
2
45
8
6
7
3
+
+CVCC
Cbulk
1
2
45
8
6
7
3
+
+CVCC
Cbulk
Rbulk
> 4.7 k
SoftStart NCP1216A only
The NCP1216A features an internal 1.0 ms softstart
activated during the power on sequence (PON). As soon as
VCC reaches VCCOFF, the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). This situation lasts during 1ms and further
to that time period, the peak current limit is blocked to
1.0 V until the supply enters regulation. The softstart is also
activated during the over current burst (OCP) sequence.
Every restart attempt is followed by a softstart activation.
Generally speaking, the softstart will be activated when
VCC ramps up either from zero (fresh poweron sequence)
or 5.6 V, the latchoff voltage occurring during OCP.
Figure 29 portrays the softstart behavior. The time scales
are purposely shifted to offer a better zoom portion.
Figure 29. Softstart is activated during a startup sequence or an OCP condition
NCP1216, NCP1216A
http://onsemi.com
16
ORDERING INFORMATION
Device Version Marking Package Shipping
NCP1216D65R2G 65 kHz 16D06 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1216D100R2G 100 kHz 16D10 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1216D133R2G 133 kHz 16D13 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1216P65G 65 kHz P1216P065 PDIP7
(PbFree)
50 Units / Rail
NCP1216P100G 100 kHz P1216P100 PDIP7
(PbFree)
50 Units / Rail
NCP1216P133G 133 kHz P1216P133 PDIP7
(PbFree)
50 Units/ Rail
NCP1216AD65R2G 65 kHz 16A06 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1216AD100R2G 100 kHz 16A10 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1216AD133R2G 133 kHz 16A13 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1216AP65G 65 kHz P1216AP06 PDIP7
(PbFree)
50 Units / Rail
NCP1216AP100G 100 kHz P1216AP10 PDIP7
(PbFree)
50 Units / Rail
NCP1216AP133G 133 kHz P1216AP13 PDIP7
(PbFree)
50 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1216, NCP1216A
http://onsemi.com
17
PACKAGE DIMENSIONS
SOIC8 NB
CASE 75107
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCP1216, NCP1216A
http://onsemi.com
18
PACKAGE DIMENSIONS
PDIP7
P SUFFIX
CASE 626B01
ISSUE A
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION L TO CENTER OF LEAD
WHEN FORMED PARALLEL.
4. PACKAGE CONTOUR OPTIONAL
(ROUND OR SQUARE CORNERS).
5. DIMENSIONS A AND B ARE DATUMS.
14
58
F
NOTE 2
T
SEATING
PLANE
H
J
G
DK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX
MILLIMETERS
A9.40 10.16
B6.10 6.60
C3.94 4.45
D0.38 0.51
F1.02 1.78
G2.54 BSC
H0.76 1.27
J0.20 0.30
K2.92 3.43
L7.62 BSC
M−−− 10
N0.76 1.01
°
A
B
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NCP1216/D
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