DATASHEET HIP4081A FN3659 Rev.9.00 Feb12, 2020 80V/2.5A Peak, High Frequency Full Bridge FET Driver The HIP4081A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081A can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081A can switch at frequencies up to 1MHz and is well suited to driving Voice Coil Motors, high-frequency switching power amplifiers, and power supplies. For example, the HIP4081A can drive medium voltage brush motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum "on-time" can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate "hysteresis mode" switching. The Application Note for the HIP4081A is the AN9405. Ordering Information Features * Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations * Bootstrap Supply Max Voltage to 95VDC * Drives 1000pF Load at 1MHz in Free Air at 50C with Rise and Fall Times of Typically 10ns * User-Programmable Dead Time * On-Chip Charge-Pump and Bootstrap Upper Bias Supplies * DIS (Disable) Overrides Input Control * Input Logic Thresholds Compatible with 5V to 15V Logic Levels * Very Low Power Consumption * Undervoltage Protection * Pb-free RoHS Compliant Applications * Medium/Large Voice Coil Motors * Full Bridge Power Supplies TEMP RANGE PACKAGE PKG. (C) (RoHS Compliant) DWG. # * Switching Power Amplifiers HIP4081AIPZ (Note) -40 to 85 20 Ld PDIP E20.3 * Noise Cancellation Systems HIP4081AIBZ (Note) -40 to 85 20 Ld SOIC (W) M20.3 HIP4081AIBZT (Note) -40 to 85 20 Ld SOIC (W) M20.3 PART NUMBER NOTE: Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. FN3659 Rev.9.00 Feb12, 2020 * High Performance Motor Controls * Battery Powered Vehicles * Peripherals * U.P.S. Pinout HIP4081A (PDIP, SOIC) TOP VIEW BHB 1 BHI 2 19 BHS DIS 3 18 BLO VSS 4 17 BLS BLI 5 16 VDD ALI 6 15 VCC AHI 7 14 ALS HDEL 8 13 ALO LDEL 9 12 AHS AHB 10 11 AHO 20 BHO Page 1 of 18 HIP4081A Application Block Diagram 80V 12V BHO BHS BHI LOAD BLO BLI HIP4081A ALI ALO AHS AHI AHO GND Functional Block Diagram GND (1/2 HIP4081A) HIGH VOLTAGE BUS 80VDC AHB 10 UNDERVOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 11 7 DIS 3 CBS AHS VDD 16 AHI AHO 12 TURN-ON DELAY DBS 15 DRIVER ALI 6 TURN-ON DELAY TO VDD (PIN 16) VCC ALO 13 ALS CBF +12VDC BIAS SUPPLY 14 HDEL 8 LDEL 9 VSS 4 FN3659 Rev.9.00 Feb12, 2020 Page 2 of 18 HIP4081A Typical Application (PWM Mode Switching) 80V BHO 20 2 BHI BHS 19 DIS 3 DIS 4 VSS PWM INPUT 5 BLI 6 ALI 7 AHI HIP4081/HIP4081A 1 BHB 12V 8 HDEL LOAD BLO 18 BLS 17 VDD 16 VCC 15 12V ALS 14 ALO 13 9 LDEL AHS 12 10 AHB AHO 11 GND - TO OPTIONAL CURRENT CONTROLLER + 6V GND FN3659 Rev.9.00 Feb12, 2020 Page 3 of 18 HIP4081A Absolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25C to 125C) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55C to 125C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All Voltages relative to VSS, unless otherwise specified. Thermal Resistance (Typical, Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65C to 150C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . . 125C Lead Temperature (Soldering 10s)) . . . . . . . . . . . . . . . . . . . . . 300C (For SOIC - Lead Tips Only Operating Conditions Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . -500A to -50A Operating Ambient Temperature Range . . . . . . . . . . .-40C to 85C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified TJS = -40C TO 125C TJ = 25C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS All inputs = 0V 8.5 10.5 14.5 7.5 14.5 mA Outputs switching f = 500kHz SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current IDD VDD Operating Current IDDO VCC Quiescent Current ICC VCC Operating Current ICCO AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage 9.5 12.5 15.5 8.5 15.5 mA All Inputs = 0V, IALO = IBLO = 0 - 0.1 10 - 20 A f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V -50 -30 -11 -60 -10 A IAHBO, IBHBO f = 500kHz, No Load 0.6 1.2 1.5 0.5 1.9 mA IHLK VBHS = VAHS = 80V, VAHB = VBHB = 93V - 0.02 1.0 - 10 A IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V IAHB, IBHB VAHB-VAHS VBHB-VBHS INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V - 35 - - - mV Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 A High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V Input Voltage Hysteresis TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL, VLDEL GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V High Level Output Voltage VCC-VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A Peak Pullup Current FN3659 Rev.9.00 Feb12, 2020 IO + Page 4 of 18 HIP4081A Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified (Continued) TJS = -40C TO 125C TJ = 25C PARAMETER SYMBOL Peak Pulldown Current IO - MIN TEST CONDITIONS MAX MIN MAX UNITS 1.7 2.4 3.3 1.3 3.6 A Undervoltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V Undervoltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V Undervoltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V Switching Specifications VO UT = 12V TYP VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF. TJS = -40C TO 125C TJ = 25C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) TLPHL - 30 60 - 80 ns Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) THPHL - 35 70 - 90 ns Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) TLPLH RHDEL = RLDEL = 10K - 45 70 - 90 ns Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) THPLH RHDEL = RLDEL = 10K - 60 90 - 110 ns Rise Time TR - 10 25 - 35 ns Fall Time TF - 10 25 - 35 ns TPWIN-ON RHDEL = RLDEL = 10K 50 - - 50 - ns Turn-off Input Pulse Width TPWIN-OFF RHDEL = RLDEL = 10K 40 - - 40 - ns Turn-on Output Pulse Width TPWOUT-ON RHDEL = RLDEL = 10K 40 - - 40 - ns Turn-off Output Pulse Width TPWOUT-OFF RHDEL = RLDEL = 10K 30 - - 30 - ns Turn-on Input Pulse Width Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW - 45 75 - 95 ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 55 85 - 105 ns Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) TDLPLH - 40 70 - 90 ns Refresh Pulse Width (ALO and BLO) TREF-PW 240 410 550 200 600 ns TUEN - 450 620 - 690 ns Disable to Upper Enable (DIS - AHO and BHO) TRUTH TABLE INPUT NOTE: OUTPUT ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO X X X 1 0 0 1 X 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 X X 1 X 0 0 X signifies that input can be either a "1" or "0". FN3659 Rev.9.00 Feb12, 2020 Page 5 of 18 HIP4081A Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 4 VSS Chip negative supply, generally will be ground. 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN3659 Rev.9.00 Feb12, 2020 Page 6 of 18 HIP4081A Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL THPHL U/V = DIS = 0 XLI XHI XLO XHO THPLH TLPLH TR (10% - 90%) TF (10% - 90%) (10% - 90%) (10% - 90%) FIGURE 1. INDEPENDENT MODE U/V = DIS = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO FIGURE 2. BISTATE MODE TDLPLH TDIS U/V OR DIS TREF-PW XLI XHI XLO XHO TUEN FIGURE 3. DISABLE FUNCTION FN3659 Rev.9.00 Feb12, 2020 Page 7 of 18 HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified 11.0 14.0 IDD SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 10.5 12.0 10.0 8.0 6.0 4.0 9.5 9.0 8.5 8.0 2.0 6 8 10 12 VDD SUPPLY VOLTAGE (V) 0 14 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) 5.0 30.0 125C 25.0 ICC SUPPLY CURRENT (mA) FLOATING SUPPLY BIAS CURRENT (mA) 10.0 20.0 15.0 10.0 5.0 0.0 0 100 200 300 400 500 600 700 800 0C 3.0 -40C 2.0 1.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE -90 LOW LEVEL INPUT CURRENT (A) 2.5 FLOATING SUPPLY BIAS CURRENT (mA) 25C 0.0 900 1000 SWITCHING FREQUENCY (kHz) 2 1.5 1 0.5 0 75C 4.0 200 600 800 400 SWITCHING FREQUENCY (kHz) 1000 FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FN3659 Rev.9.00 Feb12, 2020 -100 -110 -120 -50 -25 0 25 50 75 JUNCTION TEMPERATURE (C) 100 125 FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE Page 8 of 18 HIP4081A VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25C, Unless Otherwise Specified 80 15.0 14.0 PROPAGATION DELAY (ns) NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) Typical Performance Curves 13.0 12.0 11.0 10.0 -40 -20 0 20 40 60 80 100 70 60 50 40 30 -40 120 -20 0 JUNCTION TEMPERATURE (C) FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE 60 80 100 120 80 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 40 FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE 525 500 475 450 425 -50 20 JUNCTION TEMPERATURE (C) -25 0 25 50 75 100 70 60 50 40 30 125 150 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) FIGURE 12. DISABLE TO UPPER ENABLE, TUEN, PROPAGATION DELAY vs TEMPERATURE FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE 80 450 PROPAGATION DELAY (ns) REFRESH PULSE WIDTH (ns) 70 425 400 375 350 -50 -25 0 25 50 75 100 JUNCTION TEMPERATURE (C) FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE FN3659 Rev.9.00 Feb12, 2020 125 150 60 50 40 30 20 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE Page 9 of 18 HIP4081A VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25C, Unless Otherwise Specified (Continued) 80 80 70 70 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) Typical Performance Curves 60 50 40 30 50 40 30 20 -40 -20 0 20 40 60 80 100 20 -40 120 JUNCTION TEMPERATURE (C) -20 20 40 60 80 100 120 FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE 80 70 70 PROPAGATION DELAY (ns) 80 60 50 40 60 50 40 30 30 20 20 -40 -20 0 20 40 60 80 100 -40 120 -20 FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE 12.5 12.5 TURN-ON RISE TIME (ns) 13.5 11.5 10.5 9.5 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FN3659 Rev.9.00 Feb12, 2020 20 40 60 80 100 120 FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE 13.5 8.5 -40 0 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) GATE DRIVE FALL TIME (ns) 0 JUNCTION TEMPERATURE (C) FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE PROPAGATION DELAY (ns) 60 11.5 10.5 9.5 8.5 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE Page 10 of 18 HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified 1500 1250 5.5 VCC - VOH (mV) HDEL, LDEL INPUT VOLTAGE (V) 6.0 5.0 -40C 0C 500 25C 250 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 75C 125C 0 10 120 FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE 12 BIAS SUPPLY VOLTAGE (V) 14 FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA 3.5 1500 GATE DRIVE SINK CURRENT (A) 1250 1000 VOL (mV) 750 4.5 4.0 -40 750 -40C 500 0C 25C 250 75C 3.0 2.5 2.0 1.5 1.0 0.5 125C 0 10 0.0 6 12 14 BIAS SUPPLY VOLTAGE (V) 7 8 9 10 11 12 13 VDD , VCC, VAHB , VBHB (V) 14 15 16 FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA 3.5 500 LOW VOLTAGE BIAS CURRENT (mA) GATE DRIVE SINK CURRENT (A) 1000 3.0 2.5 2.0 1.5 1.0 0.5 0.0 6 7 8 9 10 11 12 13 14 15 VDD, VCC, VAHB, VBHB (V) FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE FN3659 Rev.9.00 Feb12, 2020 16 10,000pF 200 100 3,000pF 50 1,000pF 20 100pF 10 5 2 1 0.5 0.2 0.1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE Page 11 of 18 HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified (Continued) 1000 LEVEL-SHIFT CURRENT (A) 500 200 100 50 20 10 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE 150 UV+ 120 8.8 DEAD-TIME (ns) BIAS SUPPLY VOLTAGE, VDD (V) 9.0 8.6 UV- 90 60 8.4 30 8.2 50 25 0 25 50 75 100 125 150 TEMPERATURE (C) FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE FN3659 Rev.9.00 Feb12, 2020 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (k) 250 FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE Page 12 of 18 IN1 POWER SECTION +12V B+ Q1 CONTROL LOGIC SECTION 1 JMPR1 2 U2 + C6 JMPR5 R29 JMPR2 12 U2 IN+/ALI JMPR3 HEN/BHI 6 U2 CD4069UB 11 10 U2 R34 R33 JMPR4 CW CD4069UB 1 6 IN+/ALI 7 IN-/AHI VCC 15 ALS 14 8 HDEL 9 LDEL ALO 13 AHS 12 DD R22 3 L1 Q2 +12V R23 CW 1 AO 2 L2 C1 1 Q4 R24 AHO 11 BO C2 3 2 1 3 CR1 2 2 BLS 17 16 V 2 1 3 3 IN-/AHI 4 V SS 5 OUT/BLI 10 AHB Q3 3 U1 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 OUT/BLI CD4069UB 5 CR2 C8 1 HIP4080A/81A CD4069UB 13 R21 DRIVER SECTION 2 C3 CX CY R30 R31 C5 ENABLE IN I R32 3 U2 4 COM O ALS BLS NOTES: CD4069UB 1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V. 9 U2 8 CD4069UB O 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4. FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC HIP4081A FN3659 Rev.9.00 Feb12, 2020 IN2 Page 13 of 18 HIP4081A FN3659 Rev.9.00 Feb12, 2020 C1 R26 COM C8 C6 R28 R27 B+ + CR2 R32 + JMPR5 +12V C7 R29 GND AO Q1 C4 BHO U1 Q3 1 R22 1 JMPR1 JMPR2 JMPR3 JMPR4 I O IN2 ALS ALO C2 Q2 R23 Q4 1 1 R21 CY CX FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN R31 R34 R30 CR1 R33 BLS C3 C5 ALS AHO LDEL HDEL O L2 BLO BLS L1 IN1 HIP4080/81 R24 DIS U2 BO Page 14 of 18 HIP4081A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE Feb 12, 2020 FN3659.9 Removed retired parts. Removed About Intersil section. Updated disclaimer. Sep15, 2015 FN3659.8 Updated Ordering Information Table on page 1. Added Revision History and About Intersil sections. Updated POD M20.3 from rev 1 to rev 3. Changes since rev 1: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern FN3659 Rev.9.00 Feb12, 2020 Page 15 of 18 HIP4081A Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN A - 0.210 - MAX NOTES 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 C D 0.980 1.060 24.89 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.355 - 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. L 0.115 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.204 0.430 0.150 20 2.54 BSC 7.62 BSC - 6 10.92 7 3.81 4 2.93 20 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3659 Rev.9.00 Feb12, 2020 Page 16 of 18 HIP4081A Package Outline Drawing M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 7.60 7.40 1 2 10.65 10.00 0.25 (0.10) M B M 3 3 TOP VIEW 13.00 12.60 SEATING PLANE 2 2.65 2.35 5 0.75 1.27 BSC 0.49 0.35 7 0.25 (0.10) M 0.25 0.30 MAX C A M B S 1.27 0.40 x 45 8 MAX 0.10 (0.004) SIDE VIEW 0.32 0.23 DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 20 (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 TYPICAL RECOMMENDED LAND PATTERN FN3659 Rev.9.00 Feb12, 2020 9. Dimensions in ( ) for reference only. 10. JEDEC reference drawing number: MS-013-AC. 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