TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 D D D D D (TOP VIEW) GND TRIG OUT RESET 1 8 2 7 3 6 4 5 VDD DISCH THRES CONT FK PACKAGE (TOP VIEW) NC TRIG NC OUT NC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 description NC DISCH NC THRES NC CONT NC D D, DB, JG, P, OR PW PACKAGE NC GND NC VDD NC D D Very Low Power Consumption 1 mW Typ at VDD = 5 V Capable of Operation in Astable Mode CMOS Output Capable of Swinging Rail to Rail High Output-Current Capability Sink 100 mA Typ Source 10 mA Typ Output Fully Compatible With CMOS, TTL, and MOS Low Supply Current Reduces Spikes During Output Transitions Single-Supply Operation From 2 V to 15 V Functionally Interchangeable With the NE555; Has Same Pinout ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015.2 NC RESET NC D The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The NC - No internal connection timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555. The TLC555C is characterized for operation from 0C to 70C. The TLC555I is characterized for operation from - 40C to 85C. The TLC555M is characterized for operation over the full military temperature range of - 55C to 125C. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 AVAILABLE OPTIONS PACKAGED DEVICES TA VDD RANGE SMALL OUTLINE (D) SSOP (DB) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) 0C to 70C 2 V to 15 V TLC555CD TLC555CDBLE -- -- TLC555CP TLC555CPWLE - 40C to 85C 3 V to 15 V TLC555ID -- -- -- TLC555IP -- - 55C to 125C 5 V to 15 V TLC555MD -- TLC555MFK TLC555MJG TLC555MP -- TSSOP (PW) CHIP FORM (Y) TLC555Y The D package is available taped and reeled. Add the R suffix to device type (e.g., TLC555CDR). The DB and PW packages are only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC555CDBLE). Chips are tested at 25C. FUNCTION TABLE RESET VOLTAGE TRIGGER VOLTAGE THRESHOLD VOLTAGE OUTPUT DISCHARGE SWITCH <MIN Irrelevant Irrelevant L On >MAX <MIN Irrelevant H Off >MAX >MAX >MAX L On >MAX >MAX <MIN As previously established For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics. functional block diagram CONT 5 VDD 8 RESET 4 R THRES R1 6 3 R OUT 1 S R TRIG 2 R 7 1 GND Pin numbers are for all packages except the FK package. RESET can override TRIG, which can override THRES. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 DISCH TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 TLC555Y chip information This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CONT VDD (5) (8) THRES (6) R RESET (4) R1 R (3) 1 OUT S 50 R TRIG (2) R (7) DISCH (1) GND 64 RESET can override TRIG, which can override THRES. CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 x 4 MINIMUM TJmax = 150C TOLERANCES ARE 10%. ALL DIMENSIONS ARE IN MILS. PIN (1) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 DISCH GND RESET TRIG Template Release Date: 7-11-94 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OUT TLC555, TLC555Y LinCMOS TIMERS COMPONENT COUNT Transistors Resistors 39 5 V DD CONT SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 4 equivalent schematic (each channel) THRES TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD Sink current, discharge or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Source current, output, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, DB, P, or PW package . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE D DB FK JG P PW TA 25C POWER RATING 725 mW 525 mW 1375 mW 1050 mW 1000 mW 525 mW DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING 5.8 mW/C 4.2 mW/C 11.0 mW/C 8.4 mW/C 8.0 mW/C 4.2 mW/C 464 mW 336 mW 880 mW 672 mW 640 mW 336 mW 377 mW 273 mW 715 mW 546 mW 520 mW 273 mW 145 mW 105 mW 275 mW 210 mW 200 mW 105 mW recommended operating conditions Supply voltage, VDD TLC555C Operating free-air temperature range, TA MIN MAX 2 15 0 70 TLC555I - 40 85 TLC555M - 55 125 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT V C 5 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 electrical characteristics at specified free-air temperature, VDD = 2 V for TLC555C, VDD = 3 V for TLC555I PARAMETER VIT Threshold voltage IIT Threshold current VI(TRIG) Trigger voltage II(TRIG) Trigger current VI(RESET) Reset voltage II(RESET) Reset current TEST TA CONDITIONS IOL = 1 mA MAX MIN 25C 0.95 1.33 1.65 1.6 2.4 Full range 0.85 1.75 1.5 2.5 High level output voltage High-level IOH = - 300 A VOL Low level output voltage Low-level IOL = 1 mA IDD Supply current See Note 2 TYP 25C 10 10 MAX 75 150 25C 0.4 Full range 0.3 0.67 0.95 0.71 1.05 0.61 1 10 10 MAX 75 150 0.4 Full range 0.3 1.1 1.5 0.4 2 0.3 1.1 10 10 MAX 75 150 MAX 66.7% 66.7% 25C 0.03 0.2 0.03 0.25 0.1 0.1 MAX 0.5 120 25C 1.5 Full range 1.5 25C 1.9 1.29 1.5 1.5 0.3 0.2 V V nA 1.9 0.07 V pA V 2.5 0.07 V pA 0.375 25C UNIT pA 1.8 25C Full range MAX 1.39 25C 25C Discharge g switch off-stage g current VOH TLC555I TYP Control voltage (open circuit) as a percentage of supply voltage Discharge g switch on-stage g voltage TLC555C MIN 0.3 Full range 0.35 0.4 25C 250 250 Full range 400 500 V A Full range is 0C to 70C for the TLC555C and - 40C to 85C for the TLC555I. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 electrical characteristics at specified free-air temperature, VDD = 5 V PARAMETER VIT Threshold voltage IIT Threshold current VI(TRIG) Trigger voltage II(TRIG) Trigger current VI(RESET) Reset voltage II(RESET) Reset current TEST CONDITIONS Control voltage (open circuit) as a percentage of supply voltage Discharge g switch on-state voltage IOL = 10 mA Discharge g switch off-state current VOH High-level output g voltage IOH = - 1 mA IOL = 8 mA VOL Low-level output voltage IOL = 5 mA IOL = 3 3.2 2 mA IDD Supply current See Note 2 TA TLC555C TLC555I TLC555M MIN TYP MAX MIN TYP MAX MIN TYP MAX 25C 2.8 3.3 3.8 2.8 3.3 3.8 2.8 3.3 3.8 Full range 2.7 3.9 2.7 3.9 2.7 10 10 10 MAX 75 150 5000 25C 1.36 1.26 1.66 1.96 1.36 2.06 1.26 1.66 1.96 1.36 2.06 1.26 1.66 10 10 10 MAX 75 150 5000 25C 0.4 0.3 1.1 1.5 0.4 1.8 0.3 1.1 1.5 0.4 1.8 0.3 1.1 10 10 10 MAX 75 150 5000 MAX 66.7% 66.7% 66.7% 25C 0.14 0.5 0.14 0.6 0.5 0.14 0.6 0.1 0.1 0.1 MAX 0.5 120 120 25C 4.1 4.1 25C 4.8 0.21 0.13 25C 0.21 4.1 0.3 0.08 0.3 0.13 350 500 0.4 0.21 V pA 0.5 V nA V 0.3 0.08 0.3 0.13 350 600 0.3 V 0.45 0.08 0.3 170 350 0.35 170 0.4 0.6 0.4 0.35 170 1.5 4.8 0.5 0.4 Full range Full range 0.4 pA 4.1 0.5 Full range 25C 4.8 4.1 Full range 25C 4.1 V 0.6 25C Full range 1.96 1.8 25C Full range pA 2.06 25C Full range V 3.9 25C Full range UNIT 0.4 700 A Full range is 0C to 70C the for TLC555C, - 40C to 85C for the TLC555I, and - 55C to 125C for the TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 electrical characteristics at specified free-air temperature, VDD = 15 V PARAMETER VIT Threshold voltage IIT Threshold current VI(TRIG) Trigger voltage II(TRIG) Trigger current VI(RESET) Reset voltage II(RESET) Reset current TEST CONDITIONS Control voltage (open circuit) as a percentage of supply voltage Discharge g switch on-state voltage IOL = 100 mA Discharge g switch off-state current IOH = - 10 mA VOH High-level g output voltage IOH = - 5 mA IOH = - 1 mA IOL = 100 mA VOL Low-level output voltage IOL = 50 mA IOL = 10 mA IDD Supply current See Note 2 TA TLC555C TLC555I TLC555M UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 25C 9.45 10 10.55 9.45 10 10.55 9.45 10 10.55 Full range 9.35 10.65 9.35 10.65 9.35 25C 10 10 10 MAX 75 150 5000 25C 4.65 Full range 4.55 5 5.35 4.65 5.45 4.55 5 5.35 4.65 5.45 4.55 5 10 10 10 MAX 75 150 5000 25C 0.4 0.3 1.1 1.5 0.4 1.8 0.3 1.1 1.5 0.4 1.8 0.3 1.1 10 10 10 MAX 75 150 5000 MAX 66.7% 66.7% 66.7% 25C 0.77 1.7 0.77 1.8 1.7 0.77 1.8 0.1 0.1 0.1 MAX 0.5 120 120 25C 12.5 12.5 25C 13.5 Full range 13.5 25C 14.2 Full range 14.2 25C 14.2 14.6 Full range 13.5 14.9 14.2 1.28 3.2 14.6 1 13.5 14.9 0.3 1.28 600 800 pA 1.7 V nA 14.2 14.6 14.2 V 14.9 3.2 1.28 3.7 0.63 1 0.12 0.3 600 900 1 V 1.5 0.12 0.4 360 3.2 3.8 0.63 1.4 0.4 360 V 14.2 1.3 0.12 1.5 13.5 3.6 0.63 pA 12.5 14.2 Full range 25C 12.5 13.5 Full range 25C 14.2 12.5 Full range 25C 12.5 V 1.8 25C Full range 5.35 1.8 25C Full range pA 5.45 25C Full range V 10.65 0.3 0.45 360 600 1000 A Full range is 0C to 70C for TLC555C, - 40C to 85C for TLC555I, and - 55C to 125C for TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 operating characteristics, VDD = 5 V, TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS Initial error of timing interval Supply voltage sensistivity of timing interval tr tf Output pulse rise time fmax Maximum frequency in astable mode Output pulse fall time VDD = 5 V to 15 V,, CT = 0.1 F, MIN RA = RB = 1 k to 100 k,, See Note 3 RL = 10 M, M CL = 10 pF RA = 470 , CT = 200 pF, RB = 200 , See Note 3 1.2 TYP MAX 1% 3% 0.1 0.5 20 75 15 60 2.1 UNIT %/ V ns MHz Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. NOTE 3: RA, RB, and CT are as defined in Figure 1. electrical characteristics at VDD = 5 V, TA = 25C PARAMETER VIT IIT Threshold voltage VI(TRIG) Trigger voltage II(TRIG) Trigger current VI(RESET) II(RESET) Reset voltage TEST CONDITIONS MIN TYP MAX 2.8 3.3 3.8 Threshold current 10 1.36 1.66 0.4 1.1 1.96 Discharge switch on-state voltage 1.5 V pA 66.7% IOL = 10 mA 0.14 Discharge switch off-state current VOH High-level output voltage IOH = - 1 mA IOL = 8 mA VOL Low-level output voltage IOL = 5 mA IOL = 3.2 mA 4.1 0.5 * DALLAS, TEXAS 75265 V 0.1 nA 4.8 V 0.21 0.4 0.13 0.3 0.08 0.3 IDD Supply current See Note 2 170 350 NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. POST OFFICE BOX 655303 V pA 10 Control voltage (open circuit) as a percentage of supply voltage V pA 10 Reset current UNIT V A 9 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIMES TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER vs SUPPLY VOLTAGE DISCHARGE SWITCH ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE 600 Discharge Switch On-State Resistance - 70 VDD = 2 V, IO = 1 mA 40 VDD = 5 V, IO = 10 mA 20 VDD = 15 V, IO = 100 mA 10 7 4 2 1 -75 - 50 t PHL , t PLH - Propagation Delay Times - ns 100 IO(on) 1 mA CL 0 TA = 25C 500 400 300 tPHL 200 tPLH 100 0 - 25 0 25 50 75 100 125 0 2 TA - Free-Air Temperature - C 4 6 8 10 12 14 16 18 20 VDD - Supply Voltage - V The effects of the load resistance on these values must be taken into account separately. Figure 1 10 Figure 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 APPLICATION INFORMATION 0.1 F RA tc(H) VDD 0.1 F 4 7 5 8 CONT VDD RESET TLC555 DISCH OUT 6 RB tPHL RL 3 CT 2/3 VDD Output THRES 2 tc(L) CL 1/3 VDD TRIG GND 1 GND tPLH Pin numbers shown are for all packages except the FK package. CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, RB, and CT as shown in the equations below. [ CT (RA ) RB) In 2 (In 2 + 0.693) [ CT RB In 2 + tc(H) ) tc(L) [ CT (RA ) 2RB) In 2 t R c(L) B Output driver duty cycle + [ 1 - t ) tc(L) R ) 2R c(H) A B t c(H) t c(L) Period Output waveform duty cycle +t t c(H) c(H) t ) c(L) [ R )RB2R A B The 0.1-F capacitor at CONT in Figure 3 decreases the period by about 10%. The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of timing error in the calculation when RB is very low or ron is very high. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 APPLICATION INFORMATION The equations below provide better agreement with measured values. t t c(H) + CT (RA ) RB) In + CT (RB ) ron) In c(L) 3 - exp 3 - exp -t C T (R B -t C T (R ) ron) PLH ) RB) PHL A ) tPHL ) tPLH These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted t t c(H) with good results. Duty cycles less than 50% require that c(H) < 1 and possibly RA ron. These t t t c(H) c(L) c(L) conditions can be difficult to obtain. ) In monostable applications, the trip point on TRIG can be set by a voltage applied to CONT. An input voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-A bias provides good results. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN PINS ** 0.050 (1,27) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (4,00) 0.150 (3,81) 1 Gage Plane 7 A 0.010 (0,25) 0- 8 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 MECHANICAL INFORMATION DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 28 PIN SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,15 NOM 5,60 5,00 8,20 7,40 Gage Plane 1 14 0,25 A 0- 8 1,03 0,63 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 30 38 A MAX 3,30 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 2,70 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 / C 10/95 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 MECHANICAL INFORMATION FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 MECHANICAL INFORMATION JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE 0.400 (10,20) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.063 (1,60) 0.015 (0,38) 0.100 (2,54) 0-15 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0- 15 0.010 (0,25) M 0.010 (0,25) NOM 4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TLC555, TLC555Y LinCMOS TIMERS SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 18 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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