5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Freescale AISG Applications, East Kilbride
A
X2
X3
X4
Revision Information
Designer CommentsRev Date
GPIO - Calypso GPIO pins 1 of 2
Clocks
Sheet 8
Sheet 2
Sheet 3
Sheet 4
Sheet 5
Sheet 6
Sheet 7
GPIO - Calypso GPIO pins 2 of 2
Table Of Contents:
Calypso Customer EVB 176QFP Daughter Card (X-MPC574XG-176DS)
X1
Power - Calypso power pins footprint
Power - Calypso Decoupling Capacitors
Daughtercard Connectors
Bus Termination
11 Mar 2013 Alasdair Robertson
These schematics are provided for reference purposes only. As such,
Freescale does not make any warranty, implied or otherwise, as to the
suitability of circuit design or component selection (type or value) used in
these schematics for hardware design using the Freescale Calypso family
of Microprocessors. Customers using any part of these schematics as a
basis for hardware design, do so at their own risk and Freescale does not
assume any liability for such a hardware design.
User notes are given throughtout the schematics.
Specific PCB LAYOUT notes are detailed in ITALICS
Caution:
Notes:
- All components and board processes are to be ROHS compliant
- All small capacitors are 0402 unless otherwise stated
- All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603
- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2.
2 Pin jumpers generally have the "source" on pin 1.
- All switches are denoted SWx
- All test points are denoted TPx
- Test point Vias are denoted TPVx
Initial release sent for review based on X-MPC574XG-324DS X2
13 Mar 2013 Alasdair Robertson
15 Mar 2013 Component consolodation, Added MCU GND tab. Sent to LayoutAlasdair Robertson
Version sent to Pre Layout, incorporating fixes from review
Changes made during layout to Daughtercard Connectors29 Mar 2013 Alasdair Robertson
Alasdair Robertson Post Layout (Back Annotated). Matches PCB RevA
X5 LAY RefDes Re-Sequence & SCH Back-Annotate15 Apr 2013 Alasdair Robertson
15 Apr 2013
22 Jul 2013B Alasdair Robertson Update to accomodate extra socket pins on MCU
19 Nov 2013C Jesus Sanchez The socket was updated, exposed center PAD is grounded.
Changes on MCU Power to validate Calypso 3MJesus Sanchez19 Dec 2013D
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Automotive Microcontroller Applications
East Kilbride, Scotland
This document contains information proprietary to Freescale and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of Freescale
SCH-27898 PDF: SPF-27898 D
Calypso 176 QFP Daughter Card
B
Friday, December 20, 2013
Index and Title Page
A. Robertson
A. Robertson
A. Robertson
1 8
Freescale General Business Use
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Automotive Microcontroller Applications
East Kilbride, Scotland
This document contains information proprietary to Freescale and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of Freescale
SCH-27898 PDF: SPF-27898 D
Calypso 176 QFP Daughter Card
B
Friday, December 20, 2013
Index and Title Page
A. Robertson
A. Robertson
A. Robertson
1 8
Freescale General Business Use
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Automotive Microcontroller Applications
East Kilbride, Scotland
This document contains information proprietary to Freescale and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of Freescale
SCH-27898 PDF: SPF-27898 D
Calypso 176 QFP Daughter Card
B
Friday, December 20, 2013
Index and Title Page
A. Robertson
A. Robertson
A. Robertson
1 8
Freescale General Business Use