Note: For higher EFT performance, a minimum 1nF, 1000V capacitor can be added from nodes fIN1–fIN8 to earth or ground. For
additional methods to improve EFT robustness, please check the Maxim website regularly for upcoming application notes currently
being developed.
Applications Information
EMC Standards Compliance
The external components shown in Figure 3 allow the
device to operate in harsh industrial environments.
Components were chosen to assist in suppression of
voltage burst and surge transients, allowing the system
to meet or exceed international EMC requirements.
Table 2 lists an example device for each component
in Figure 3. The system shown in Figure 3, using the
components shown in Table 2, is designed to be robust
against IEC Fast Transient Burst, surge, conducted RFI
specifications, and ESD specifications (IEC 61000-4-2,
-4, -5, and -6).
Serial-Port Operation
Serial output of the device functions in one of two modes,
depending on the MODESEL setting (Table 3).
With MODESEL = 0, the device output includes a 5-bit
CRC, an undervoltage alarm, and an overtemperature
alarm. See the Detailed Description for CRC, undervolt-
age, and overtemperature functional descriptions.
With MODESEL = 1, the device outputs only the state
of the IN1–IN8 inputs and omits the CRC, undervoltage
alarm, and overtemperature alarm.
Daisy-Chain Operation
For systems with more than eight sensor inputs, multiple
devices can be daisy-chained to allow access to all data
inputs through a single serial port. When using a daisy-
chain configuration, connect SOUT of one of the devices
to the SIN input of another upstream device. CS and SCK
of all devices in the chain should be connected together
in parallel (see Figure 4).
In a daisy-chain configuration, external components
used to enhance EMC robustness do not need to be
duplicated for each device of a circuit board. Figure 5
illustrates a 16-input application.
SPI Waveforms
The serial output of the device adheres to the SPI proto-
col, running with CPHA = 0 and CPOL = 0. Input states
on IN1–IN8 are latched in on the falling edge of CS. The
transfer of data out of the slave output, SOUT, starts
immediately when CS is asserted (i.e., MSB is output
onto SOUT independent of CLK). The remaining data bits
are shifted out on the falling edge of CLK. The data bits
are written to the output SOUT with MSB first. When CS
is high, SOUT is high impedance. The resultant timing is
shown in Figure 6. Note that all bits after IN1 are invalid
if 8-bit operation mode is selected with the MODESEL
input. Figure 7, Figure 8, Figure 9, and Figure 10 illustrate
SPI timing specifications.
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12
MAX31910 Ultra-Low Power Industrial, Octal, Digital Input
Translator/Serializer
COMPONENT DESCRIPTION REQUIRED/RECOMMENDED/OPTIONAL
C0 4.7nF, 2kV polypropylene capacitor Recommended
C1 10FF, 60V ceramic capacitor Required
C3 100nF, 10V ceramic capacitor Recommended
C4 4.7µF, 10V low ESR ceramic capacitor Required
C5 100nF, 100V ceramic capacitor Recommended
D0 36V fast zener diode (ZSMB36) Recommended
D1 General-purpose rectifier (IN4007) Optional: For reverse-polarity protection.
R1 150I, 1/3W MELF resistor Recommended
RINX 2.2kI, 1/4W MELF resistor Required
RREF 15kI, 1/8W resistor Required
Table 2. Recommended Circuit Components