TVP9900
VSB/QAM Receiver
Data Manual
Literature Number: SLEA064March 2007
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Contents
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
1 Introduction ......................................................................................................................... 71.1 Features ....................................................................................................................... 71.2 Ordering Information ........................................................................................................ 72 Block Diagram ..................................................................................................................... 83 Terminal Assignments .......................................................................................................... 93.1 Pinout .......................................................................................................................... 93.2 Terminal Functions ......................................................................................................... 104 Functional Description ........................................................................................................ 124.1 Analog Front End ........................................................................................................... 124.2 VSB/QAM Demodulator ................................................................................................... 124.3 Forward Error Correction .................................................................................................. 124.4 Output Formatter ........................................................................................................... 134.5 I
2
C Host Interface .......................................................................................................... 144.5.1 I
2
C Write Operation ............................................................................................. 154.5.2 I
2
C Read Operation ............................................................................................. 164.6 Tuner Control Interface .................................................................................................... 174.6.1 Tuner Write Operation .......................................................................................... 184.6.2 Tuner Read Operation .......................................................................................... 184.7 Antenna Control Interface ................................................................................................. 194.7.1 Antenna Interrogation/Initialization ............................................................................ 204.7.2 Transmit Data to Antenna Operation ......................................................................... 214.7.3 Receive Data from Antenna Operation ....................................................................... 214.8 General-Purpose IO (GPIO) .............................................................................................. 214.9 Clock Circuits ............................................................................................................... 224.10 Power-Up Sequence ....................................................................................................... 224.11 Reset ......................................................................................................................... 224.12 Power Down ................................................................................................................ 234.13 Power-Supply Voltage Requirements ................................................................................... 235 High-K PCB Design Recommendations ................................................................................. 246 Host Processor I
2
C Register Summary .................................................................................. 256.1 Overview ..................................................................................................................... 256.2 I
2
C Register Definitions .................................................................................................... 276.2.1 Receiver Control Register 1 / Soft Reset ..................................................................... 276.2.2 Receiver Control Register 2 .................................................................................... 286.2.3 VSB Control Register ........................................................................................... 286.2.4 AGC Control Register ........................................................................................... 296.2.5 VSB FEC Time Counter Register 1 ........................................................................... 296.2.6 VSB FEC Time Counter Register 2 ........................................................................... 306.2.7 VSB FEC Time Counter Register 3 ........................................................................... 306.2.8 QAM FEC Time Counter Register 1 .......................................................................... 316.2.9 QAM FEC Time Counter Register 2 .......................................................................... 316.2.10 QAM FEC Time Counter Register 3 .......................................................................... 316.2.11 VSB FEC Segment Error Count Threshold Register 1 ..................................................... 326.2.12 VSB FEC Segment Error Count Threshold Register 2 ..................................................... 326.2.13 Update Status Control Register ............................................................................... 326.2.14 Receiver Status Register ....................................................................................... 336.2.15 AGC Status Register 1 .......................................................................................... 336.2.16 AGC Status Register 2 .......................................................................................... 336.2.17 AGC Status Register 3 .......................................................................................... 346.2.18 NTSC Rejection Filter Status Register ....................................................................... 34
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TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
6.2.19 Timing Recovery Status Register 1 ........................................................................... 346.2.20 Timing Recovery Status Register 2 ........................................................................... 346.2.21 Timing Recovery Status Register 3 ........................................................................... 356.2.22 Timing Recovery Status Register 4 ........................................................................... 356.2.23 Timing Recovery Status Register 5 ........................................................................... 356.2.24 Timing Recovery Status Register 6 ........................................................................... 356.2.25 Pilot Tracking Status Register 1 ............................................................................... 366.2.26 Pilot Tracking Status Register 2 ............................................................................... 366.2.27 Pilot Tracking Status Register 3 ............................................................................... 366.2.28 Carrier Recovery Status Register 1 ........................................................................... 366.2.29 Carrier Recovery Status Register 2 ........................................................................... 376.2.30 Carrier Recovery Status Register 3 ........................................................................... 376.2.31 Carrier Recovery Status Register 4 ........................................................................... 376.2.32 Carrier Recovery Status Register 5 ........................................................................... 376.2.33 Carrier Recovery Status Register 6 ........................................................................... 386.2.34 FEC Status Register 1 .......................................................................................... 386.2.35 FEC Status Register 2 .......................................................................................... 396.2.36 FEC Status Register 3 .......................................................................................... 396.2.37 FEC Status Register 4 .......................................................................................... 396.2.38 GPIO Alternate Function Select Register .................................................................... 406.2.39 GPIO Output Data Register .................................................................................... 406.2.40 GPIO Output Enable Register ................................................................................. 416.2.41 GPIO Input Data Register ...................................................................................... 416.2.42 MPEG Interface Output Enable Register 1 .................................................................. 426.2.43 MPEG Interface Output Enable Register 2 .................................................................. 436.2.44 Tuner Control Interface – I
2
C Slave Device Address Register ............................................ 436.2.45 Tuner Control Interface – Data Register 1 Through 8 ...................................................... 436.2.46 Tuner Control Interface – Control and Status Register ..................................................... 446.2.47 Antenna Control Interface – Control and Status Register .................................................. 446.2.48 Antenna Control Interface – Transmit Data Register 1 ..................................................... 456.2.49 Antenna Control Interface – Transmit Data Register 2 ..................................................... 456.2.50 Antenna Control Interface – Receive Data Register 1 ...................................................... 456.2.51 Antenna Control Interface – Receive Data Register 2 ...................................................... 466.2.52 Firmware ID – ROM Version Register ........................................................................ 466.2.53 Firmware ID – RAM Major Version Register ................................................................. 466.2.54 Firmware ID – RAM Minor Version Register ................................................................. 466.2.55 Device ID LSB Register ........................................................................................ 476.2.56 Device ID MSB Register ........................................................................................ 476.2.57 Miscellaneous Control Register ................................................................................ 476.2.58 Software Interrupt Raw Status Register ...................................................................... 486.2.59 Software Interrupt Status Register ............................................................................ 486.2.60 Software Interrupt Mask Register ............................................................................. 496.2.61 Software Interrupt Clear Register ............................................................................. 507 Electrical Specifications ...................................................................................................... 517.1 Absolute Maximum Ratings ............................................................................................... 517.2 Recommended Operating Conditions ................................................................................... 527.3 DC Electrical Characteristics ............................................................................................. 527.4 Analog Input Characteristics .............................................................................................. 537.5 Timing Characteristics ..................................................................................................... 547.5.1 Crystal and Input Clock ......................................................................................... 547.5.2 Device Reset ..................................................................................................... 547.5.3 MPEG Interface .................................................................................................. 557.5.3.1 Parallel Mode (Data Only) ...................................................................................... 55
Contents 3
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TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
7.5.3.2 Serial Mode (Data Only) ........................................................................................ 567.5.3.3 Parallel Mode (Data With Redundancy) ...................................................................... 577.5.3.4 Serial Mode (Data With Redundancy) ........................................................................ 587.5.4 Host and Tuner I
2
C Interface .................................................................................. 598 Application Circuit .............................................................................................................. 60
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TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
List of Figures
2-1 TVP9900 Block Diagram .......................................................................................................... 8
4-1 Parallel Transport Stream Timing Diagram (Data Only) ..................................................................... 13
4-2 Serial Transport Stream Timing Diagram (Data Only) ....................................................................... 13
4-3 Parallel Transport Stream Timing Diagram (Data + Redundancy) ......................................................... 14
4-4 Serial Transport Stream Timing Diagram (Data + Redundancy) ........................................................... 14
4-5 Tuner Control Interface System ................................................................................................. 17
4-6 Antenna Control Interface System .............................................................................................. 19
4-7 25-MHz Crystal Oscillation ....................................................................................................... 22
4-8 4-MHz Clock Input ................................................................................................................ 22
5-1 Thermal Land Size and Via Array ............................................................................................... 24
7-1 Crystal or Clock Timing Waveform ............................................................................................. 54
7-2 Device Reset Signal Timing Waveforms ....................................................................................... 54
7-3 MPEG Interface – Parallel Mode (Data Only) Timing Waveforms .......................................................... 55
7-4 MPEG Interface – Serial Mode (Data Only) Timing Waveforms ............................................................ 56
7-5 MPEG Interface – Parallel Mode (Data With Redundancy) Timing Waveforms .......................................... 57
7-6 MPEG Interface – Serial Mode (Data with Redundancy) Timing Waveforms ............................................. 58
7-7 I
2
C SCL and SDA Timing Waveforms .......................................................................................... 59
7-8 I
2
C Start and Stop Conditions Timing Waveforms ............................................................................ 59
List of Figures 5
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TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
List of Tables
3-1 Terminal Functions ................................................................................................................ 10
4-1 MPEG-2 Transport Stream Interface ........................................................................................... 13
4-2 MPEG-2 Transport Stream Output Clock Frequency ........................................................................ 14
4-3 I
2
C Terminal Description ......................................................................................................... 15
4-4 I
2
C Host Interface Device Write Addresses .................................................................................... 15
4-5 I
2
C Host Interface Device Read Address ...................................................................................... 16
4-6 Tuner Control Interface Registers ............................................................................................... 17
4-7 Antenna Control Interface Registers ............................................................................................ 19
4-8 Antenna Control Interface Pins .................................................................................................. 20
6-1 I
2
C Host Interface Registers ..................................................................................................... 25
7-1 Crystal and Input Clock Timing .................................................................................................. 54
7-2 Device Reset Timing .............................................................................................................. 54
7-3 Parallel Mode (Data Only) Timing .............................................................................................. 55
7-4 Serial Mode (Data Only) Timing ................................................................................................. 56
7-5 Parallel Mode (Data With Redundancy) Timing ............................................................................... 57
7-6 Serial Mode (Data With Redundancy) Timing ................................................................................. 58
7-7 Host and Tuner I
2
C Interface Timing .......................................................................................... 59
6List of Tables Submit Documentation Feedback
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1 Introduction
1.1 Features
1.2 Ordering Information
(1)
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The TVP9900 is a cost-effective digital TV (DTV) front-end IC targeted for low-cost high-volume DTVreceivers. The TVP9900 is a system-on-chip (SoC) device that integrates the main functions of a DTVfront-end system, including programmable gain amplifier (PGA), A/D converter, VSB demodulator, ATSCforward error correction (FEC), QAM demodulator, and ITU-T Annex B FEC. It provides rich peripheralsupport including AGC control, tuner control, CEA-909 antenna control, and host I
2
C interface. TheTVP9900 supports processing of ATSC VSB or ITU-T Annex B QAM IF inputs.
•Host Interrupt for Remote Monitoring of Signal•ATSC 8-VSB Demodulation and FEC
Quality•ITU-J.83B Compliant 64/256 QAM
•SNR MonitorDemodulation and FEC
•BER Monitor•Direct 44-MHz IF Sampling Eliminates Need forExternal Downconverter
•Integrated De-Interleaver RAM•Integrated IF PGA
•Parallel/Serial MPEG Output Interface WithError Packet Indicator•Integrated High-Speed 10-bit A/D Converter
•Direct Tuner Control Interface•Integrated Digital Filter Relaxes External TunerFilters
•EIA/CEA-909 Antenna Control Interface•Sigma-Delta DAC for AGC Control
•Option for 4-MHz Clock Input Driven by MOPIC in Tuner, So No Quartz Crystal Required for•Adjacent Channel Filter
Demodulator•NTSC Co-Channel Rejection Filter
•External DAC and VCXO for Clock Recovery•All Digital Timing Recovery
Not Required•Pilot Tracking Loop With Lock Status Indicator
•Equalizer Covers Echo Profile Required bySignal
ATSC A.74 Guideline•Decision-Directed Carrier Phase Tracking
•Superior Multipath Performance DemodulatingLoop
for Brazil Ensembles A Through E•Field and Segment Synchronization With Sync
•Power-Down ModeStatus Indicator Signal
•80-Pin TQFP Package
PACKAGED DEVICEST
A
PACKAGE OPTION80-Pin TQFP-PowerPAD
TVP9900PFP Tray0°C to 70 °C
TVP9900PFPR Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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2 Block Diagram
VSB/QAM
Demodulator
ITU-T J.83
Annex B FEC
ATSC FEC
I2CSDA
I2CSCL
TUNSDA
TUNSCL
AIFIN_P
AIFIN_N
Tuner
Interface
AGCOUT
GPIO [7:0]
Output
Formatter
CEA-909
Interface
GPIO
Interface
ANTCNTLIO
VBUS
ROM RAM
MCU
Host
Interface
Interrupt Ctrl
JTAG
DCLK
BYTE_START
PACCLK
DATAOUT[7:0]
DERROR
PLL
INTREQ
PWRDOWN
AFE VSB/QAM
Demodulator
ITU-T J.83
Annex B FEC
ATSC FEC
AIFIN_P
AIFIN_N
Tuner
Interface
AGCOUT
GPIO [7:0]
XTALIN
XTALOUT
CLKIN
CLKSEL
CLKOUT
Output
Formatter
CEA-909
Interface
GPIO
Interface
VBUS
ROM RAM
Host
Interface
Interrupt Ctrl
JTAG
DCLK
BYTE_START
PACCLK
DATAOUT[7:0]
DERROR
PLL
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Figure 2-1. TVP9900 Block Diagram
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3 Terminal Assignments
3.1 Pinout
TVP9900
80-PinTQFP
(TopView)
1
AGND 2
AVDD_3_3 3
AIFIN_P 4
AIFIN_N 5
AVDD_3_3 6
AGND 7
AVDD_1_5 8
AGND 9
AGND_PLL 10
AVDD_PLL_1_5 11
XTALOUT 12
XTALREF 13
XTALIN 14
CLKIN 15
DIVINSEL 16
CLKOUT 17
DGND 18
DVDD_1_5 19
IOGND 20
IOVDD_3_3
21
RESETZ 22
TMSEL0 23
TMSEL1 24
DGND 25
DVDD_1_5 26
TMSEL2 27
TMSEL3 28
AGCOUT 29
ANTCNTLIO 30
TUNSDA 31
TUNSCL 32
IOGND 33
IOVDD_3_3 34
I2CSDA 35
I2CSCL 36
DGND 37
DVDD_1_5 38
I2CA0 39
PWRDWN 40
DERROR
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DATAOUT0
DATAOUT1
DVDD_1_5
DGND
DATAOUT2
DATAOUT3
DATAOUT4
IOVDD_3_3
IOGND
DATAOUT5
DATAOUT6
DATAOUT7/SERDATA0
DVDD_1_5
DGND
PACCLK
BYTESTART
IOVDD_3_3
IOGND
DCLK
DGND
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
NSUB
BGREFCAP
BIASRES
AVDD_REF_3_3
AGND_REF
AGND
DGND
DVDD_1_5
GPIO0/ANTCNTLIN
GPIO1
GPIO2
DGND
DVDD_1_5
GPIO3
GPIO4
GPIO5/SYNCOUT
IOVDD_3_3
IOGND
GPIO6
GPIO7/INTREQ
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
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3.2 Terminal Functions
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Table 3-1. Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
IF INTERFACE
AIFIN_P 3 I Analog positive differential IF inputAIFIN_N 4 I Analog negative differential IF input
TRANSPORT STREAM INTERFACE
DCLK 42 O MPEG-2 data clock outputMPEG-2 Byte Start signal. An active high output signal that indicates the first byte of aBYTE_START 45 O
transport stream data packet.MPEG-2 interface packet framing signal. An active high output signal that remains highPACCLK 46 O
for the entire length of the valid data packet.MPEG-2 interface data error. An active high output signal that indicates an error in theDERROR 40 O data output packet. Indicates an error in the input data. This pin should be tied low if notin use.
1. MPEG-2 parallel data output. Bit 7 is the first bit of the transport stream.DATAOUT7/SERDATA0 49 O
2. MPEG-2 serial data output50, 51,54, 55,DATAOUT[6:0] O MPEG-2 parallel data output bits 6-0.56, 59,
60
CLOCK SIGNALS
Crystal input. Input to the on-chip oscillator from an external crystal. The required crystalfrequency is 25 MHz. This input can also be driven by an external clock source instead ofXTALIN 13 I a crystal. When using an external clock source, a 4 MHz or 25 MHz clock must be used.NOTE: If an external clock source is used, the input can only be used with 1.5-V signallevels.XTALOUT 11 O Crystal output. Output from the on-chip oscillator to an external crystal.External crystal reference. This pin is used for the external crystal capacitor groundXTALREF 12 I
reference.CLKIN 14 I Test clock input. For normal operation, this input should be tied low.PLL VCO divider default input select. This input is used to select the default VCO dividervalue for the PLL. If a 25-MHz crystal or clock is used for XTALIN, then DIVINSEL shouldDIVINSEL 15 I
be driven low. If a 4-MHz crystal or clock is used for XTALIN, then DIVINSEL should bedriven high.CLKOUT 16 O Test clock output. For normal operation, this output is not used.
MISCELLANEOUS SIGNALS
AGCOUT 28 O AGC control Delta-Sigma DAC output.ANTCNTLIO 29 I/O Smart antenna control interface input/output.TUNSDA 30 I/O Tuner I
2
C serial data input/output. NOTE: The output functions as an open-drain.TUNSCL 31 I/O Tuner I
2
C serial clock. NOTE: The output functions as an open-drain.1. General purpose I/OGPIO7/INTREQ 61 I/O
2. Interrupt request output1. General purpose I/OGPIO6 62 I/O
2. Reserved
1. General purpose I/OGPIO5/SYNCOUT 65 I/O
2. Sync output66, 67,GPIO[4:2] I/O General purpose I/O70
Dedicated to Smart Antenna support. Outputs direction of signal on pin 29 in SmartAntenna 1-pin mode.GPIO1 71 O
0 = Signal input from antenna to TVP9900, pin 291 = Signal output from TVP9900 pin 29 to antenna
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TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Table 3-1. Terminal Functions (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
1. General purpose I/OGPIO0/ANTCNTLIN 72 I/O
2. Antenna Control InputSystem reset. An active-low asynchronous input that initializes the device to the defaultRESETZ 21 I
state.PWRDOWN 39 I Power down terminal. An active high signal puts the device in a low power state.22, 23,TMSEL[3:0] I Test mode select. Tie low for normal operation.26, 27
HOST INTERFACE
I2CSDA 34 I/O Host I
2
C serial data input/output. NOTE: The pin functions as an open-drain output.I
2
CSCL 35 I/O Host I
2
C serial clock. NOTE: The pin functions as an open-drain output.Host I
2
C device address select. Determines address for I
2
C (sampled during reset). Apullup or pulldown 10-k Ωresistor is needed to program the terminal to the desiredI
2
CA0 38 I address.
0 = Address is 0xB8h1 = Address is 0xBAh
POWER SUPPLIES
18, 25,37, 48,DVDD_1_5 P Digital power supply. Connect to 1.5-V digital supply.58, 68,
7317, 24,36, 41,DGND P Digital power supply return. Connect to digital ground.47, 57,69, 7420, 33,IOVDD_3_3 44, 53, P IO power supply. Connect to 3.3-V digital supply.6419, 32,IOGND 43, 52, P IO power supply return. Connect to digital ground.63AVDD_3_3 2, 5 P Analog power supply. Connect to 3.3-V analog supply.AVDD_1_5 7 P Analog power supply. Connect to 1.5-V analog supply.1, 6, 8,AGND P Analog power supply return. Connect to analog ground.75AVDD_PLL_1_5 10 P PLL power supply. Connect to 1.5-V analog supply.AGND_PLL 9 P PLL power supply return. Connect to analog ground.NSUB 80 P Die substrate. Connect to PCB ground.AVDD_REF_3_3 77 P Analog reference power supply. Connect to 3.3-V analog supply.AGND_REF 76 P Analog reference ground. Connect to analog ground.BGREFCAP 79 O Band-gap reference capacitor connectionBIASRES 78 O Analog bias register. Connect through a 24-k Ωresistor to PCB ground.
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4 Functional Description
4.1 Analog Front End
4.2 VSB/QAM Demodulator
4.3 Forward Error Correction
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The TVP9900 receiver has an analog input channel that accepts one differential or single-ended 44-MHzcenter frequency IF input, which are ac-coupled. The receiver supports a maximum input differentialvoltage range of 1 Vpp with PGA setting at unity gain. The programmable gain amplifier (PGA) and theAGC circuit work together and ensure that the input signal is amplified sufficiently to ensure the properinput range for the ADC. The ADC has 10 bits of resolution. The clock input for the ADC comes from thePLL. An external downconverter is not required to use this IF direct sampling method. The analog frontend and adjacent digital filter can potentially relax the requirement for external analog filters, and only oneexternal SAW filter is required.
The VSB/QAM demodulator is designed for 8-VSB demodulation compliant with ATSC, and 64/256 QAMdemodulation compliant with ITU-T J83 Annex B. The VSB/QAM demodulator in the TVP9900 iscomposed of the following blocks:•Automatic gain control•Adjacent channel filter•NTSC rejection filter•Timing recovery•Pilot tracking•Matched filter•Decision feedback equalizer•Carrier recovery
The all-digital demodulator architecture does not require an external downconverter, AGC control DAC,clock recovery VCXO, or carrier recovery VCXO. This architecture makes a low-cost systemimplementation possible.
Forward Error Correction (FEC) in the TVP9000 includes the following blocks:•QAM FEC– Trellis decoder– Synchronizer
– De-randomizer
– De-interleaver
– Reed Solomon decoder– MPEG deframer•VSB FEC– Trellis decoder– Synchronizer
– De-interleaver
– Reed Solomon decoder– De-randomizer
The Trellis decoder is designed for help protect against short-burst interference. The VSB synchronizerperforms segment and frame synchronization and outputs the synchronization signal with data. An internalRAM is shared by both VSB and QAM modes, and additional external RAM is not required.
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4.4 Output Formatter
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
Data 188 bytes
7 6 5 4 3 2 1 0 7 6 1 0
1st byte
7 6 5 4 3 2 1 0 7 6
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
7 6 5 4 3 2 1 0 7 6 1 0
1st byte
7 6 5 4 3 2 1 0 7 6
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The TVP9900 transport stream interfaces directly to the back-end IC, which provides transport streamcompliance with ISO/IEC 13818-1 in parallel or serial modes. The details of the transport stream interfaceare shown in Table 4-1 . In serial mode, DATAOUT[7] is used as the serial data output, with the MSBoutput first. The maximum output rate is 42.1 Mbit/s in serial mode. The polarity of DCLK, BYTE_START,DERROR, and PACCLK is programmable.
Table 4-1. MPEG-2 Transport Stream Interface
TERMINAL TYPE DESCRIPTION
DCLK O Parallel/serial clock outputParallel/serial data outputDATAOUT[7:0] O DATAOUT7 is the first bit of the transport stream in parallel mode.DATAOUT7 is the serial data output in serial mode.BYTE_START O Packet sync, indicates the start byte of a transport packetPACCLK O Packet enable, indicates the valid packet data
Figure 4-1 and Figure 4-2 show the parallel and serial transport stream timing diagrams in data-onlymode. In data-only mode, 188 bytes of data is transferred from the transport stream interfacecontinuously. PACCLK is always kept high.
Figure 4-1. Parallel Transport Stream Timing Diagram (Data Only)
Figure 4-2. Serial Transport Stream Timing Diagram (Data Only)
Figure 4-3 and Figure 4-4 show the parallel and serial transport stream timing diagrams in data andredundancy mode. In data and redundancy mode, 188 bytes of data is transferred from the transportstream interface with redundant data bytes. PACCLK only becomes high when the data is valid.Redundancy data is 20 bytes in the ATSC standard and 16 bytes in ITU-T J.83 Annex B.
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Parity 16 or 20 bytesData 188 bytes
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Parity 16 or 20 bytesData 188 bytes
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes Parity 16 or 20 bytes
7 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 5
1st byte
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes Parity 16 or 20 bytes
7 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 5
1st byte
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
4.5 I
2
C Host Interface
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Figure 4-3. Parallel Transport Stream Timing Diagram (Data + Redundancy)
Figure 4-4. Serial Transport Stream Timing Diagram (Data + Redundancy)
Table 4-2 shows the transport stream clock frequency in each mode.
Table 4-2. MPEG-2 Transport Stream Output Clock Frequency
DATA ONLY DATA + REDUNDANCYBIT RATEMODE
SERIAL CLOCK PARALLEL CLOCK SERIAL CLOCK PARALLEL CLOCK(Mbps)
(MHz) (MHz) (MHz) (MHz)
8VSB 19.39266 19.39266 2.42408 21.45571 2.6819664QAM 26.97035 26.97035 3.37129 29.26570 3.65821256QAM 38.81070 38.81070 4.85133 42.11374 5.26422
Communication with the TVP9900 receiver is via an I
2
C host interface. The I
2
C standard consists of twosignals, the serial input/output data (I2CSDA) line and the input/output clock line (I2CSCL), which carryinformation between the devices connected to the bus. A 1-bit control signal (I2CA0) is used for slaveaddress selection. Although an I
2
C system can be multi-mastered, the TVP9900 can function as a slavedevice only. Since I2CSDA and I2CSCL are kept open-drain at logic high output level or when the bus isnot driven, the user should connect I2CSDA and I2CSCL to IOVDD_3.3 via a pullup resistor on the board.At the trailing edge of reset, the status of the I2CA0 line is sampled to determine the device address used.Table 4-3 summarizes the terminal functions of the I
2
C-mode host interface. Table 4-4 and Table 4-5show the device address selection options.
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4.5.1 I
2
C Write Operation
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Table 4-3. I
2
C Terminal Description
SIGNAL TYPE DESCRIPTION
I2CA0 I Slave address selectionI2CSCL I/O (open drain) Input/output clock lineI2CSDA I/O (open drain) Input/output data line
Table 4-4. I
2
C Host Interface Device Write Addresses
I2CA0 WRITE ADDRESS
0 B8h1 BAh
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus isdependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during thehigh period of the SCL, except for start and stop conditions. The high or low state of the data line can onlychange with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while theSCL is high indicates an I
2
C start condition. A low-to-high transition on the SDA line while the SCL is highindicates an I
2
C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes that can be transferred isunrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse isgenerated by the I
2
C master.
Data transfers occur utilizing the following illustrated formats. An I
2
C master initiates a write operation tothe TVP9900 receiver by generating a start condition (S), followed by the TVP9900 I
2
C address (as shownbelow), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledgefrom the TVP9900 receiver, the master presents the sub-address of the register or the first of a block ofregisters it wants to write, followed by one or more bytes of data, MSB first. The TVP9900 receiveracknowledges each byte after completion of each transfer. The I
2
C master terminates the write operationby generating a stop condition (P).
Step 1 0
SI
2
C Start (master)
Step 2 7 6 5 4 3 2 1 0
1 0 1 1 1 0 X 0I
2
C General address (master)
Step 3 9
AI
2
C Acknowledge (slave)
Step 4 7 6 5 4 3 2 1 0
Addr Addr Addr Addr Addr Addr Addr AddrI
2
C Write register address (master)
Step 5 9
AI
2
C Acknowledge (slave)
Step 6 7 6 5 4 3 2 1 0
Data Data Data Data Data Data Data DataI
2
C Write data (master)
9Step 7
(1)
AI
2
C Acknowledge (slave)
Step 8 0
PI
2
C Stop (master)
(1) Repeat steps 6 and 7 until all data have been written.
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4.5.2 I
2
C Read Operation
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The read operation consists of two phases. The first phase is the address phase. In this phase, an I
2
Cmaster initiates a write operation to the TVP9900 receiver by generating a start condition (S) followed bythe TVP9900 I
2
C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receivingacknowledges from the TVP9900 receiver, the master presents the sub-address of the register or the firstof a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycleimmediately by generating a stop condition (P).
Table 4-5. I
2
C Host Interface Device Read Address
I2CA0 READ ADDRESS
0 B8h1 BAh
The second phase is the data phase. In this phase, an I
2
C master initiates a read operation to theTVP9900 receiver by generating a start condition, followed by the TVP9900 I
2
C address (as shown belowfor a read operation), in MSB-first bit order, followed by a 1 to indicate a read cycle. After an acknowledgefrom the TVP9900 receiver, the I
2
C master receives one or more bytes of data from the TVP9900receiver. The I
2
C master acknowledges the transfer at the end of each byte. After the last data bytedesired has been transferred from the TVP9900 receiver to the master, the master generates a notacknowledge, followed by a stop.Read Phase 1
Step 1 0
SI
2
C Start (master)
Step 2 7 6 5 4 3 2 1 0
1 0 1 1 1 0 X 0I
2
C General address (master)
Step 3 9
AI
2
C Acknowledge (slave)
Step 4 7 6 5 4 3 2 1 0
Addr Addr Addr Addr Addr Addr Addr AddrI
2
C Write register address (master)
Step 5 9
AI
2
C Acknowledge (slave)
Step 6 0
PI
2
C Stop (master)
Read Phase 2
Step 7 0
SI
2
C Start (master)
Step 8 7 6 5 4 3 2 1 0
1 0 1 1 1 0 X 0I
2
C General address (master)
Step 9 9
AI
2
C Acknowledge (slave)
Step 10 7 6 5 4 3 2 1 0
Data Data Data Data Data Data Data DataI
2
C Read data (slave)
9Step 11
(1)
AI
2
C Not Acknowledge (master)
Step 12 0
PI
2
C Stop (master)
(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
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4.6 Tuner Control Interface
Tuner
Control
Interface
Host
I2C
Interface
MCU
From
Host
Processor
SDA
SCL
TUNSDA
TUNSCL
To
Tuner
Tuner
Control
Interface
Host
I2C
Interface
From
Host
Processor
SDA
SCL
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The TVP9900 has an I
2
C-compatible two-wire serial interface that can be used by the host processor fortuner control. This dedicated tuner interface can be used by the host processor to transfer data to/from thetuner in order to isolate the tuner from the main system I
2
C bus. As a result, noise coupling to the tunerfrom host processor I
2
C bus transfers should be minimized.
The TVP9900 tuner control interface operates as an I
2
C bus master and supports both 100-kbps and400-kbps data transfer rates. The mode and transfer rate is set in the Tuner Control Interface – Controland Status Register (5Eh), bit 0. The device does not support a multi-master bus environment (busarbitration is not supported).
To transfer data to/from the tuner, the host processor first writes the transaction to a set of registers in theTVP9900 via the host processor I
2
C interface. Then the TVP9900 internal MCU transfers the data to/fromthe tuner via the tuner control interface.
TUNSCL and TUNSDA need to be pulled up to the 3.3-V supply (IOVDD) and not to a 5-V supply.
Figure 4-5 shows the block diagram of the tuner control interface system.
Figure 4-5. Tuner Control Interface System
Table 4-6 lists the I
2
C registers and their functions used to control the tuner interface.
Table 4-6. Tuner Control Interface Registers
REGISTER FUNCTION
55h Tuner I
2
C slave address and R/W control56h to 5Dh Data registers 1 through 85Eh Byte Count, Transaction Start, and I
2
C ModeSoftware Interrupt Raw Status, Status, Mask, and Clear – Transaction ErrorF9, FB, FD, FFh
and Done Status
When the TVP9900 tuner I
2
C interface is used, rather than controlling the tuner over the host processorI
2
C bus interface, two status bits are provided in the TVP9900 to indicate a transaction error or thecompletion of a successful transaction. The TCIERROR bit in the TVP9900 Software Interrupt StatusRegister (FBh) gets set as a result of a transaction error. The TCIDONE bit in the same register gets setat the end of a normal transaction; it does not get set for an abnormal transaction. The TVP9900 can beconfigured so that setting the TCIERROR or TCODONE status bits can assert the INTREQ output of theTVP9900; this requires the mask bits to be configured correctly in the TVP9900 Software Interrupt MaskRegister (FDh).
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4.6.1 Tuner Write Operation
4.6.2 Tuner Read Operation
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
If the host INTREQ is not used, the TCIDONE and TCIERROR interrupts should be masked and the hostshould poll the TCIDONE status bit to determine when the transaction is complete, and the host shouldpoll the TCIERROR status bit to determine when an error has occurred.
Tuner data transfers occur utilizing the following illustrated formats.
The following steps are required to initiate a write operation to the tuner. The host processor first writesthe required transaction data to a set of registers in the TVP9900 via the host processor I
2
C interface.
Step 1
Register 55h
Set tuner I
2
C slave address (bits 7:1) and read/write control (bit 0 = 0)
Step 2
Registers 56h to 5Dh Write data bytes to be sent to tuner; 56h is first byte sent
Step 3
Set byte count (bits 7:5) and I
2
C mode (bit 0)Register 5Eh
Set bit 2 to 1 to start transaction to tuner
Step 4
Register FBh Check state of bits 1:0 or INTREQ pin to verify successful transaction
After the transaction has been initiated, the TVP9900 internal MCU transfers the data to the tuner via thetuner control interface. Acting as the I
2
C master, the TVP9900 initiates a write operation to the tuner (asshown below), by generating a start condition, followed by the tuner I
2
C address, in MSB-first bit order,followed by a 0 to indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900presents the sub-address of the register, if needed, followed by one or more bytes of data, MSB first. Thetuner acknowledges each byte after completion of each transfer. The TVP9900 terminates the writeoperation by generating a stop condition.
TVP9900/Tuner Write Operation
Device BaseSDA Start W Ack Ack Data 1 Ack ... Data N Ack StopAddress Address
The following steps are required to initiate a read operation from the tuner. The host processor first writesthe required transaction data to a set of registers in the TVP9900 via the host processor I
2
C interface,then reads the data bytes received from the tuner stored in TVP9900 registers.
Step 1
Register 55h
Set tuner I
2
C slave address (bits 7:1) and read/write control (bit 0 = 1)
Step 2
Set byte count (bits 7:5) and I
2
C mode (bit 0)Register 5Eh
Set bit 2 to 1 to start transaction to tuner
Step 3
Register FBh Check state of bits 1:0 or INTREQ pin to verify successful transaction
Step 4
Registers 56h to 5Dh Read data bytes from tuner; 56h is first byte received
After the transaction has been initiated, the TVP9900 internal MCU transfers the data from the tuner viathe tuner control interface. The read operation consists of two phases, as shown below. The first phase isthe address phase. In this phase, the TVP9900 I
2
C master initiates a write operation to the tuner bygenerating a start condition, followed by the tuner I
2
C address, in MSB-first bit order, followed by a 0 toindicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900 presents thesub-address of the register, if needed. After the cycle is acknowledged, the master terminates the cycleimmediately by generating a stop condition.
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4.7 Antenna Control Interface
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The second phase is the data phase. In this phase, the TVP9900 I
2
C master initiates a read operation tothe tuner by generating a start condition, followed by the tuner I
2
C address, in MSB-first bit order, followedby a 1 to indicate a read cycle. After an acknowledge from the tuner, the TVP9900 receives one or morebytes of data from the tuner. The TVP9900 acknowledges the transfer at the end of each byte. After thelast data byte desired has been transferred from the tuner to the TVP9900, the TVP9900 generates a notacknowledge, followed by a stop.
TVP9900/Tuner Set Start Address, Then Read Operation
Device BaseSDA Start W Ack Ack StopAddress Address
DeviceSDA Start R Ack Data 1 Ack ... Data N Ack StopAddress
The TVP9900 has an antenna control interface compliant with EIA/CEA-909. The TVP9900 receives theantenna parameters from the host processor via I
2
C, and sends a modulated PWM signal to the antenna.The antenna parameters include antenna direction, antenna polarization, preamplifier gain and channelnumber. This interface can be used to automatically optimize the signal by adjusting the antennaconfiguration for the best possible reception.
Figure 4-6 shows the block diagram of the antenna control interface system.
Figure 4-6. Antenna Control Interface System
Table 4-7 lists the I
2
C registers and their functions used with the antenna control interface.
Table 4-7. Antenna Control Interface Registers
REGISTER FUNCTION
4Fh GPIO Alternate Function Select5Fh Antenna Control Interface – Control and Status60h to 61h Antenna Control Interface – Transmit Data62h to 63h Antenna Control Interface – Receive DataSoftware Interrupt Raw Status, Status, Mask, and Clear – TransactionF9, FB, FD, FFh
Complete and Timeout Status
The TVP9900 supports two modes of antenna control: Mode A for basic control (transmit transaction only)and Mode B for advanced control (transmit and receive transactions) as defined in the CEA-909 standard.For Mode B operation, the TVP9900 supports both 1-pin and 2-pin operation. In 1-pin mode, the datainput and output are muxed into one pin (pin 29), and in 2-pin mode the input and output use separatepins (pin 29 for output, pin 72 for input.) The desired pin mode is selected by setting register 5Fh, bit 0.
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4.7.1 Antenna Interrogation/Initialization
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Table 4-8 lists the TVP9900 pins and their functions used with the antenna control interface.
Table 4-8. Antenna Control Interface Pins
PIN NAME FUNCTION
29 ANTCNTLIO Antenna control interface input/output71 GPIO1 Signal direction of pin 29 in 1-pin mode72 GPIO0/ANTCNTLIN Antenna control input for 2-pin mode
The GPIO1 pin provides dedicated smart antenna control support, and in 1-pin mode this pin outputs thedirection of the signal on pin 29:GPIO1 = 0 indicates signal input from antenna to TVP9900 pin 29GPIO1 = 1 indicates signal output from TVP9900 pin 29 to antenna
Four status bit are provided in the TVP9900 to indicate the completion of a successful receive or transmittransaction, or if a transaction timeout has occurred.•The ACIRXCT bit in the TVP9900 Software Interrupt Status Register (FBh) gets set when the receivetransaction from a Mode B antenna is complete.•The ACITXCT bit in the same register gets set when the transmit transaction to the antenna iscomplete.
•The ACIRXTO bit in the same register gets set when an interface timeout has occurred due to no replyform the antenna following a transmit transaction, or an incomplete receive transaction from theantenna.
•The RXERR bit in the Antenna Control Interface Control and Status Register (5Fh) is set if anincomplete receive transaction occurs.
The TVP9900 can be configured so that setting the ACIRXCT, ACITXCT, or ACIRXTO status bits canassert the INTREQ output of the TVP9900; this requires the mask bits to be configured correctly in theTVP9900 Software Interrupt Mask Register (FDh).
If the host INTREQ is not used, the ACIRXCT, ACITXCT, and ACIRXTO interrupts should be masked andthe host should poll the ACIRXCT and ACITXCT status bits to determine when the transactions arecomplete, and the host should poll the ACIRXTO and RXERR status bits to determine when a receivetimeout or error has occurred.
Antenna control data transfers occur utilizing the following illustrated formats.
The following steps are required to interrogate and initialize a smart antenna. The host processor firstwrites the required transaction data to a set of registers in the TVP9900 via the host processor I
2
Cinterface.
1. The system host processor transmits to the antenna a basic Mode A 14-bit serial data stream with anRF channel number of zero.2. The system tri-states the line and waits 100 ms for a reply message from the antenna controller. If noresponse is received, a timeout occurs, and the antenna controller is assumed to be a Mode A system.The system uses only transmit operations for antenna control.3. If the antenna responds with a 10-bit program identifier, the antenna controller is assumed to be aMode B system, and the system uses transmit and receive operations for antenna control.
This initialization is optional. If the system has only Mode A enabled, with no Mode B support, then thisinitialization step may be omitted.
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4.7.2 Transmit Data to Antenna Operation
4.7.3 Receive Data from Antenna Operation
4.8 General-Purpose IO (GPIO)
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The following steps are required to transmit data to the antenna. The host processor writes the requiredtransaction data to a set of registers in the TVP9900, as described below, via the host processor I
2
Cinterface.
Step 1
Set TXRXSEL (bit 2 = 1) to select a transmit data transaction, and set MODE (bit 4 = 1) to enable auto receiveRegister 5Fh
mode
Step 2
Registers 60h to 61h Load 14-bit data value to be transmitted to antenna
Step 3
Register 5Fh Set TXSTART (bit 3) to 1 to start transmit transaction to tuner
Step 4
Register FBh Check state of bit 4 or INTREQ pin to verify successful transaction
After an antenna transmit transaction is executed, a Mode B antenna should respond with a 10-bit datavalue within 100 ms. If the receive data is not received within 100 ms, then a receive timeout occurs. Thefollowing steps are required to receive data from the antenna. The host processor first writes the requiredtransaction data to a set of registers in the TVP9900, as described below, via the host processor I
2
Cinterface, then reads the data bytes received from the antenna stored in TVP9900 registers.
Step 1
Set TXRXSEL (bit 2 = 0) to select a receive data transaction, and set MODE (bit 4 = 1) to enable auto receiveRegister 5Fh
mode
Step 2
Register FBh Check state of bit 5 or INTREQ pin to verify successful transaction, or wait for timeout interrupt (bit 3) to occur
Step 3
Registers 62h to 63h Read 10-bit data value received from antenna
Step 4
Register 5Fh Read RXERR value (bit 5)
The RXERR bit is set to 1 to indicate an error occurred when receiving data from a Mode B antenna. If anon-zero data value was received from the antenna and no error occurred, then the data is valid and theantenna is a Mode B antenna. If the data value is zero and no error occurred, then a receive transactiondid not occur and it is assumed that the antenna is a Mode A antenna.
The TVP9900 has eight general-purpose IO pins, GPIO0–GPIO7. GPIO1 is a dedicated pin for SmartAntenna support. GPIO0, GPIO5, GPIO6, and GPIO7 are shared pins and can be programmed as thefollowing dedicated functions. See register 4Fh description for details about selecting these alternatefunctions. All pins are configured as inputs at device power-up.•GPIO0 – Antenna control input•GPIO5 – Sync output•GPIO6 – Reserved•GPIO7 – Interrupt request output
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4.9 Clock Circuits
TVP9900
XTALIN
XTALOUT
25 MHz
Crystal
TVP9900
XTALREF
TVP9900
4 MHz
Clock
TVP9900
XTALIN
XTALOUT
4.10 Power-Up Sequence
4.11 Reset
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
An internal PLL generates all clocks required in the chip. A 25-MHz clock is required to derive the PLL.Most tuner devices have a 4-MHz crystal oscillator that can be output to the demodulator as a clocksource. In the TVP9900, a 4-MHz clock input also can be used as the clock source. A 4-MHz clock isinput to the TVP9900 receiver on terminal 13 (XTALIN), or a crystal of 25-MHz fundamental resonantfrequency may be connected across terminals 13 (XTALIN) and 11 (XTALOUT). Figure 4-7 shows thereference clock configuration of 25-MHz crystal oscillation. NOTE: The oscillator input, XTALIN, is not3.3-V tolerant and only works at 1.5-V signal levels.
Figure 4-7. 25-MHz Crystal Oscillation
Figure 4-8 shows the reference clock configuration of 4-MHz clock input.
Figure 4-8. 4-MHz Clock Input
No specific power-supply sequence is required, as long as all power supplies are ramped to validoperating levels within 500 ms of one another. Output or bidirectional buffers power-up with the outputbuffers in tri-state mode.
The reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device atpower-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of1 ms after all power-supply voltages are stable at the recommended operating voltage. Internal circuitssynchronize the power-on reset with internal clocks; therefore, the RESETZ signal must remain active lowfor a minimum of 1 µs after the crystal oscillator and clocks are stable.
Reset may be asserted any time after power up and stable crystal oscillation and must remain asserted forat least 1 µs. A minimum of 200 µs must be allowed after reset before commencing I
2
C operations.
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4.12 Power Down
4.13 Power-Supply Voltage Requirements
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
There is no required power-down sequence for the TVP9900.
The digital core uses a 1.5-V power supply. The digital IO cells use a 3.3-V power supply. Note that theexception is for the oscillator input, XTALIN, which is not 3.3-V tolerant and only works at 1.5-V signallevels. The analog circuitry uses both a 1.5-V and a 3.3-V power supply.
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5 High-K PCB Design Recommendations
1.4 mm 0.33 mm
10-mm × 10-mm thermal land size
6 × 6 array of vias
1.4-mm via spacing
0.33-mm via diameter
10 mm
10 mm
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
In order to effectively transfer heat out of the package and to keep the die junction temperature below105 °C, the TVP9900 is packaged in the thermal PowerPAD™ package, which has an exposed metal padon the bottom of the device. To effectively use this package, the following PCB design requirements mustbe followed.
•An array of thermal vias should be placed in the board at the placement location of the TVP9900, asshown in Figure 5-1.•The ideal thermal land size is 10 mm ×10 mm, and the ideal thermal via pattern is a 6 ×6 array.•The vias should be connected to the PCB ground plane.•The exposed metal pad of the TVP9900 should be soldered to these vias.•The copper trace thickness should be 0.071 mm (2 oz), if possible.
Figure 5-1. Thermal Land Size and Via Array
Each of these recommendations is important to maximize the heat-sinking characteristics of the PCB.Refer to the Texas Instruments application report, PowerPAD™ Thermally Enhanced Package (literaturenumber SLMA002 ), for more detailed information.
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6 Host Processor I
2
C Register Summary
6.1 Overview
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The TVP9900 IC is controlled by a host processor by using a set of control and status registers. Access tothese registers by the host processor is via an I
2
C serial interface. A summary of the I
2
C host interfaceregisters is given in Table 6-1 .
Table 6-1. I
2
C Host Interface Registers
ADDRESS REGISTER NAME DEFAULT R/W
00h Receiver Control Register 1 / Soft Reset 20h R/W01h Receiver Control Register 2 11h R/W02h Reserved03h VSB Control Register 02h R/W04h AGC Control Register 07h R/W05h–1Ah Reserved1Bh VSB FEC Time Counter Control Register 1 BCh R/W1Ch VSB FEC Time Counter Control Register 2 64h R/W1Dh VSB FEC Time Counter Control Register 3 00h R/W1Eh QAM FEC Time Counter Control Register 1 00h R/W1Fh QAM FEC Time Counter Control Register 2 08h R/W20h QAM FEC Time Counter Control Register 3 00h R/W21h VSB FEC Segment Error Count Threshold 1 05h R/W22h VSB FEC Segment Error Count Threshold 2 00h R/W23h–24h Reserved25h Update Status Control Register N/A R/W26h Receiver Status Register N/A R27h AGC Status Register 1 – AGC LF Accumulator Output (7:0) N/A R28h AGC Status Register 2 – AGC LF Accumulator Output (15:8) N/A R29h AGC Status Register 3 – AGC LF Accumulator Output (19:16) N/A R2Ah NTSC Rejection Filter Status Register N/A R2Bh Timing Recovery Status Register 1 – DTR LF Accumulator Output (7:0) N/A R2Ch Timing Recovery Status Register 2 – DTR LF Accumulator Output (15:8) N/A R2Dh Timing Recovery Status Register 3 – DTR LF Accumulator Output (23:16) N/A R2Eh Timing Recovery Status Register 4 – DTR LF Accumulator Output (31:24) N/A R2Fh Timing Recovery Status Register 5 – DTR LF Accumulator Output (39:32) N/A R30h Timing Recovery Status Register 6 – DTR LF Accumulator Output (43:40) N/A R31h–33h Reserved34h Pilot Tracking Status Register 1 – DPT LF Accumulator Output (7:0) N/A R35h Pilot Tracking Status Register 2 – DPT LF Accumulator Output (15:8) N/A R36h Pilot Tracking Status Register 3 – DPT LF Accumulator Output (19:16) N/A R37h–38h Reserved39h Carrier Recovery Status Register 1 – DCL Average Error (7:0) N/A R3Ah Carrier Recovery Status Register 2 – DCL Average Error (15:8) N/A R3Bh Carrier Recovery Status Register 3 – DCL Average Error (19:16) N/A R3Ch Carrier Recovery Status Register 4 – QAM DCL LF Accumulator Output (7:0) N/A R3Dh Carrier Recovery Status Register 5 – QAM DCL LF Accumulator Output (15:8) N/A R3Eh Carrier Recovery Status Register 6 – QAM DCL LF Accumulator Output (19:16) N/A R3Fh–40h Reserved
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2
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TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Table 6-1. I
2
C Host Interface Registers (continued)
ADDRESS REGISTER NAME DEFAULT R/W
41h Forward Error Correction Status Register 1 N/A R42h Reserved43h Forward Error Correction Status Register 2 – FEC Segment Error Count (7:0) N/A R44h Forward Error Correction Status Register 3 – FEC Segment Error Count (11:8) N/A R45h Forward Error Correction Status Register 4 N/A R46h–4Eh Reserved4Fh GPIO Alternate Function Select Register 00h R/W50h GPIO Output Data Register 00h R/W51h GPIO Output Enable Register FFh R/W52h GPIO Input Data Register 00h R53h MPEG Interface Output Enable Register 1 00h R/W54h MPEG Interface Output Enable Register 2 00h R/W55h Tuner Control Interface – I
2
C Slave Device Address 00h R/W56h Tuner Control Interface – Data Register 1 00h R/W57h Tuner Control Interface – Data Register 2 00h R/W58h Tuner Control Interface – Data Register 3 00h R/W59h Tuner Control Interface – Data Register 4 00h R/W5Ah Tuner Control Interface – Data Register 5 00h R/W5Bh Tuner Control Interface – Data Register 6 00h R/W5Ch Tuner Control Interface – Data Register 7 00h R/W5Dh Tuner Control Interface – Data Register 8 00h R/W5Eh Tuner Control Interface – Control and Status Register 00h R/W5Fh Antenna Control Interface – Control and Status Register 00h R/W60h Antenna Control Interface – Transmit Data Register 1 00h R/W61h Antenna Control Interface – Transmit Data Register 2 00h R/W62h Antenna Control Interface – Receive Data Register 1 00h R/W63h Antenna Control Interface – Receive Data Register 2 00h R/W64h–6Fh Reserved70h Firmware ID – ROM Version 02h R71h Firmware ID – RAM Major Version 00h R72h Firmware ID – RAM Minor Version 00h R73h–7Fh Reserved80h Device ID LSB 00h R81h Device ID MSB 99h R82h–EDh ReservedEEh Miscellaneous Control Register 00h R/WEFh–F8h ReservedF9h Software Interrupt Raw Status Register 00h RFAh ReservedFBh Software Interrupt Status Register 00h RFCh ReservedFDh Software Interrupt Mask Register 00h R/WFEh ReservedFFh Software Interrupt Clear Register 00h W
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6.2 I
2
C Register Definitions
6.2.1 Receiver Control Register 1 / Soft Reset
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Any write to this register causes a soft reset, which puts the receiver back into signal acquisition, andenables any changes made to registers 01h to 22h. Recommend performing soft reset after channelchange.
Address 00h
Default 20h
Bit 76543210
Mnemonic RDNSEL MPEGSEL DCLKPS BYSTPS DERRPS PCLKPS DMDSEL
Type R/W R/W R/W R/W R/W R/W R/W
Default 001000 00
BIT MNEMONIC NAME DESCRIPTION
The MPEG interface redundancy select is used by the host processor to selectMPEG interface the data with redundancy output mode.7 RDNSEL
redundancy select 0 = No redundancy (data only mode) selected (default)1 = Data with redundancy mode selectedThe MPEG interface serial output select is used by the host processor toMPEG interface serial select the serial versus parallel output mode for the MPEG interface.6 MPEGSEL
output select 0 = 8-bit parallel data output mode selected (default)1 = Serial data output mode selectedThe MPEG interface data clock output polarity select is used by the hostprocessor to select the polarity of the DCLK output pin.MPEG interface data 0 = All MPEG interface output signals transition with respect to the rising edge5 DCLKPS
clock output polarity select of DCLK
1 = All MPEG interface output signals transition with respect to the falling edgeof DCLK (default)The MPEG interface byte start output polarity select is used by the hostMPEG interface byte start processor to select the polarity of the BYTESTART output pin.4 BYSTPS
output polarity select 0 = BYTESTART is active high (default)1 = BYTESTART is active lowThe MPEG interface data error output polarity select is used by the hostMPEG interface data error processor to select the polarity of the DERROR output pin.3 DERRPS
output polarity select 0 = DERROR is active high (default)1 = DERROR is active lowThe MPEG interface packet clock output polarity select is used by the hostMPEG interface packet processor to select the polarity of the PACCLK output pin.2 PCLKPS
clock output polarity select 0 = PACCLK is active high (default)1 = PACCLK is active lowThe VSB or QAM mode select bits are used by the host processor to selectthe demodulation type to be used by the TVP9900 receiver device.VSB or QAM 00 = 8 VSB mode selected (default)1:0 DMDSEL
demodulation mode select 01 = Reserved
10 = 64 QAM mode selected11 = 256 QAM mode selected
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6.2.2 Receiver Control Register 2
6.2.3 VSB Control Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 01h
Default 11h
Bit 76543210
Mnemonic Reserved Reserved IQSWAP Reserved DNFCTRL DAFBYP Reserved
Type R R R R/W R/W R/W R/W
Default 0 0 0 1 00 0 1
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useTiming recovery spectral shift5 IQSWAP IQ swap 0 = Shift spectrum positive frequency (default)1 = Shift spectrum negative frequency. For QAM mode, this bit swaps I and Q.4 — Reserved Reserved for future use. Always set to 1.NTSC detection circuit control for VSB (always bypassed for QAM)00 = Use detection circuit (default)NTSC detection circuit3:2 DNFCTRL 01 = Force bypass of NTSC filtercontrol
10 = Force insertion of NTSC filter11 = Reserved
Adjacent channel filter bypass for VSB (always bypassed for QAM)Adjacent channel filter1 DAFBYP 0 = Enable the adjacent channel filter (default)bypass
1 = Bypass the adjacent channel filter0 — Reserved Reserved for future use. Always set to 1.
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 03h
Default 02h
Bit 76543210
Mnemonic Reserved Reserved Reserved RSTDIS Reserved Reserved Reserved Reserved
Type R R R R/W R R R R
Default 00000010
BIT MNEMONIC NAME DESCRIPTION
7:5 — Reserved Reserved for future useDisable VSB automatic soft reset mode.0 = Firmware automatically restarts acquisition when there are too many4 RSTDIS Auto restart disable
segment errors (default)1 = Disable automatic restarts3:0 — Reserved Reserved for future use. Always set to 2h.
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6.2.4 AGC Control Register
6.2.5 VSB FEC Time Counter Register 1
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 04h
Default 07h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved Reserved DAGINV Reserved
Type R R R R R R/W R
Default 000001 11
BIT MNEMONIC NAME DESCRIPTION
7:3 — Reserved Reserved for future useThe Automatic Gain Control output signal (AGCOUT) invert select bit is usedAGC output signal invert by the host processor to change the polarity of the output signal.2 DAGINV
select 0 = AGCOUT is non-inverted1 = AGCOUT is inverted (default)1:0 — Reserved Reserved for future use. Always set to 3h.
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 1Bh
Default BCh
Bit 76543210
Mnemonic FCSFRSTIMECOUNT1
Type R/W
Default 0xBC
BIT MNEMONIC NAME DESCRIPTION
VSB update interval Update interval count value (RS blocks) for segment error count; bits (7:0)7:0 FCSFRSTIMECOUNT1
count, bits (7:0) of 24-bit value. The remaining bits are stored in registers 1Ch and 1Dh.
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6.2.6 VSB FEC Time Counter Register 2
6.2.7 VSB FEC Time Counter Register 3
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 1Ch
Default 64h
Bit 76543210
Mnemonic FCSFRSTIMECOUNT2
Type R/W
Default 0x64
BIT MNEMONIC NAME DESCRIPTION
VSB update interval Update interval count value (RS blocks) for segment error count; bits (15:8)7:0 FCSFRSTIMECOUNT2
count, bits (15:8) of 24-bit value
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 1Dh
Default 00h
Bit 76543210
Mnemonic FCSFRSTIMECOUNT3
Type R/W
Default 0x00
BIT MNEMONIC NAME DESCRIPTION
VSB update interval Update interval count value (RS blocks) for segment error count; bits7:0 FCSFRSTIMECOUNT3
count, bits (23:16) (23:16) of 24-bit value
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6.2.8 QAM FEC Time Counter Register 1
6.2.9 QAM FEC Time Counter Register 2
6.2.10 QAM FEC Time Counter Register 3
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 1Eh
Default 00h
Bit 76543210
Mnemonic JCSJRSTIMECOUNT1
Type R/W
Default 0x08
BIT MNEMONIC NAME DESCRIPTION
QAM Update interval Update interval count value (RS blocks) for segment error count; bits (7:0) of7:0 JCSJRSTIMECOUNT1
count, bits (7:0) 24-bit value. The remaining bits are stored in registers 1Fh and 20h.
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 1Fh
Default 08h
Bit 76543210
Mnemonic JCSJRSTIMECOUNT2
Type R/W
Default 0x08
BIT MNEMONIC NAME DESCRIPTION
QAM Update interval Update interval count value (RS blocks) for segment error count; bits (15:8) of7:0 JCSJRSTIMECOUNT2
count, bits (15:8) 24-bit value
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 20h
Default 00h
Bit 76543210
Mnemonic JCSJRSTIMECOUNT3
Type R/W
Default 0x00
BIT MNEMONIC NAME DESCRIPTION
QAM Update interval Update interval count value (RS blocks) for segment error count; bits (23:16)7:0 JCSJRSTIMECOUNT3
count, bits (23:16) of 24-bit value
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6.2.11 VSB FEC Segment Error Count Threshold Register 1
6.2.12 VSB FEC Segment Error Count Threshold Register 2
6.2.13 Update Status Control Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 21h
Default 05h
Bit 76543210
Mnemonic UNCORRINT1
Type R/W
Default 0x05
BIT MNEMONIC NAME DESCRIPTION
Segment Error Count Segment error count threshold; bits (7:0) of a 12-bit value. The remaining bits7:0 UNCORRINT1
threshold, bits (7:0) are stored in register 22h.
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing toregister 00h.
Address 22h
Default 00h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved UNCORRINT2
Type R R R R R/W
Default 0 0 0 0 0h
BIT MNEMONIC NAME DESCRIPTION
7:4 Reserved Reserved Reserved for future useSegment error count3:0 UNCORRINT2 Segment error count threshold; bits (11:8) of a 12-bit valuethreshold, bits (11:8)
Address 25h
Default 00h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved Reserved UPDATE
Type RRRRRRRR/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:1 — Reserved Reserved for future useUpdate all status registers (26h to 45h)Host writes a 1 to this bit to update all the status registers. Host should then0 UPDATE Update status registers
read this bit until it reads 0; the status update is then complete, and it is safe toread any/all of the status registers.
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6.2.14 Receiver Status Register
6.2.15 AGC Status Register 1
6.2.16 AGC Status Register 2
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 26h
Bit 76543210
Mnemonic Reserved Reserved Reserved ERRCNT Reserved SLCERR FLDSYNC
Type R R RRRRR
Default 0 N/A N/A N/A N/A N/A N/A
BIT MNEMONIC NAME DESCRIPTION
7:4 — Reserved Reserved for future useImmediate RS segment error count threshold status bitReed Solomon segment3 ERRCNT 0 = RS segment error count is below thresholderror count status
1 = RS segment error count is above threshold2 — Reserved Reserved for future useImmediate slicer error threshold status bit1 SLCERR Slicer error status 0 = Slicer error is below threshold1 = Slicer error is above thresholdImmediate field sync lock status bit0 FLDSYNC Field sync lock status 0 = Field sync is lost1 = Field sync is locked (not lost)
Address 27h
Bit 76543210
Mnemonic DAGLFACC1STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Bits (7:0) of the 20-bit AGC loop filter accumulator output. The remaining bitsAGC accumulator output,7:0 DAGLFACC1STAT are stored in registers 28h and 29h. These register values are updated bybits (7:0)
writing a 1 to register 25h, bit 0.
Address 28h
Bit 76543210
Mnemonic DAGLFACC2STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
AGC accumulator output,7:0 DAGLFACC2STAT Bits (15:8) of the 20-bit AGC loop filter accumulator outputbits (15:8)
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6.2.17 AGC Status Register 3
6.2.18 NTSC Rejection Filter Status Register
6.2.19 Timing Recovery Status Register 1
6.2.20 Timing Recovery Status Register 2
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 29h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved DAGLFACC3STAT
Type RRRR R
Default 0 0 0 0 N/A
BIT MNEMONIC NAME DESCRIPTION
7:4 — Reserved Reserved for future useAGC accumulator output,3:0 DAGLFACC3STAT Bits (19:16) of the 20-bit AGC loop filter accumulator outputbits (19:16)
Address 2Ah
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved Reserved DNFDETECT
Type RRRRRRRR
Default 0000000N/A
BIT MNEMONIC NAME DESCRIPTION
7:1 — Reserved Reserved for future useNTSC detection circuit statusNTSC detection circuit0 DNFDETECT 0 = NTSC is NOT detectedstatus
1 = NTSC is detected
Address 2Bh
Bit 76543210
Mnemonic DTRLFACC1STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Timing recovery Bits (7:0) of the 44-bit timing recovery loop filter accumulator output. The7:0 DTRLFACC1STAT accumulator output, remaining bits are stored in registers 2Ch to 30h. These register values arebits (7:0) updated by writing a 1 to register 25h, bit 0.
Address 2Ch
Bit 76543210
Mnemonic DTRLFACC2STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Timing recovery7:0 DTRLFACC2STAT accumulator output, Bits (15:8) of the 44-bit timing recovery loop filter accumulator outputbits (15:8)
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6.2.21 Timing Recovery Status Register 3
6.2.22 Timing Recovery Status Register 4
6.2.23 Timing Recovery Status Register 5
6.2.24 Timing Recovery Status Register 6
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 2Dh
Bit 76543210
Mnemonic DTRLFACC3STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Timing recovery7:0 DTRLFACC3STAT accumulator output, Bits (23:16) of the 44-bit timing recovery loop filter accumulator outputbits (23:16)
Address 2Eh
Bit 76543210
Mnemonic DTRLFACC4STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Timing recovery7:0 DTRLFACC4STAT accumulator output, Bits (31:24) of the 44-bit timing recovery loop filter accumulator outputbits (31:24)
Address 2Fh
Bit 76543210
Mnemonic DTRLFACC5STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Timing recovery7:0 DTRLFACC5STAT accumulator output, Bits (39:32) of the 44-bit timing recovery loop filter accumulator outputbits (39:32)
Address 30h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved DTRLFACC6STAT
Type RRRR R
Default 0 0 0 0 N/A
BIT MNEMONIC NAME DESCRIPTION
7:4 — Reserved Reserved for future useTiming recovery3:0 DTRLFACC6STAT accumulator output, Bits (43:40) of the 44-bit timing recovery loop filter accumulator outputbits (43:40)
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6.2.25 Pilot Tracking Status Register 1
6.2.26 Pilot Tracking Status Register 2
6.2.27 Pilot Tracking Status Register 3
6.2.28 Carrier Recovery Status Register 1
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 34h
Bit 76543210
Mnemonic DPTLFACC1STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Bits (7:0) of the 20-bit pilot tracking loop filter accumulator output. ThePilot tracking accumulator7:0 DPTLFACC1STAT remaining bits are stored in registers 35h and 36h. These register values areoutput, bits (7:0)
updated by writing a 1 to register 25h, bit 0.
Address 35h
Bit 76543210
Mnemonic DPTLFACC2STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Pilot tracking accumulator7:0 DPTLFACC2STAT Bits (15:8) of the 20-bit pilot tracking loop filter accumulator outputoutput, bits (15:8)
Address 36h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved DPTLFACC3STAT
Type RRRR R
Default 0 0 0 0 N/A
BIT MNEMONIC NAME DESCRIPTION
7:4 — Reserved Reserved for future usePilot tracking accumulator3:0 DPTLFACC3STAT Bits (19:16) of the 20-bit pilot tracking loop filter accumulator outputoutput, bits (19:16)
Address 39h
Bit 76543210
Mnemonic DCLAVGERR1STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Bits (7:0) of the 20-bit DCL average error (derotator SNR) value. TheDCLAVGERR1ST DCL average error, bits7:0 remaining bits are stored in registers 3Ah and 3Bh. These register values areAT (7:0)
updated by writing a 1 to register 25h, bit 0.
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6.2.29 Carrier Recovery Status Register 2
6.2.30 Carrier Recovery Status Register 3
6.2.31 Carrier Recovery Status Register 4
6.2.32 Carrier Recovery Status Register 5
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 3Ah
Bit 76543210
Mnemonic DCLAVGERR2STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
DCLAVGERR2ST DCL average error,7:0 Bits (15:8) of the 20-bit DCL average error (derotator SNR) valueAT bits (15:8)
Address 3Bh
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved DCLAVGERR3STAT
Type RRRR R
Default 0 0 0 0 N/A
BIT MNEMONIC NAME DESCRIPTION
7:4 — Reserved Reserved for future useDCLAVGERR3ST DCL average error,3:0 Bits (19:16) of the 20-bit DCL average error (derotator SNR) valueAT bits (19:16)
Address 3Ch
Bit 76543210
Mnemonic DCLLFACC1STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Bits (7:0) of the 20-bit DCL loop filter accumulator output for QAM. TheQAM DCL loop filter7:0 DCLLFACC1STAT remaining bits are stored in registers 3Dh and 3Eh. These register valuesaccumulator output, bits (7:0)
are updated by writing a 1 to register 25h, bit 0.
Address 3Dh
Bit 76543210
Mnemonic DCLLFACC2STAT
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
QAM DCL loop filter7:0 DCLLFACC2STAT Bits (15:8) of the 20-bit DCL loop filter accumulator output for QAM.accumulator output, bits (15:8)
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6.2.33 Carrier Recovery Status Register 6
6.2.34 FEC Status Register 1
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 3Eh
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved DCLLFACC3STAT
Type RRRR R
Default 0 0 0 0 N/A
BIT MNEMONIC NAME DESCRIPTION
7:4 — Reserved Reserved for future useQAM DCL loop filter3:0 DCLLFACC3STAT accumulator output, Bits (19:16) of the 20-bit DCL loop filter accumulator output for QAM.bits (19:16)
6.2.34.1 VSB ModeAddress 41h
Bit 76543210
Mnemonic FECSADDR1
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
7:2 Reserved Reserved for future useFEC synchronizer status bits00 = Searching for sync (data not valid)FECSADDR1
1:0 FEC synchronizer status 01 = Locked sync (data valid)10 = Reserved
11 = Sync lost (data not valid)
6.2.34.2 QAM ModeAddress 41h
Bit 76543210
Mnemonic FECSADDR1
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Trellis sync status bits00 = Sync locked, error under threshold7:6 Trellis sync status 01 = Reserved
10 = Sync locked, error above threshold11 = Hunting for syncCurrent deinterleaver control5:2 FECSADDR1 Current deinterleaver control work valuework value
FEC synchronizer status bits00 = Searching for sync (data not valid)1:0 FEC synchronizer status 01 = Locked sync (data valid)10 = Reserved
11 = Sync lost (data not valid)
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6.2.35 FEC Status Register 2
6.2.36 FEC Status Register 3
6.2.37 FEC Status Register 4
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 43h
Bit 76543210
Mnemonic FECSADDR2
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
Bits (7:0) of the 12-bit FEC segment error count value. Bits (11:8) are stored inFEC segment error count,7:0 FECSADDR2 register 44h, bits (7:4). These register values are updated by writing a 1 tobits (7:0)
register 25h, bit 0.
Address 44h
Bit 76543210
Mnemonic FECSADDR3
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
FEC segment error count,7:4 Bits (11:8) of the 12-bit FEC segment error count valuebits (11:8)FECSADDR3
3:0 Reserved Reserved for future use
6.2.37.1 VSB ModeAddress 45h
Bit 76543210
Mnemonic FECSADDR4
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
7:0 FECSADDR4 Reserved Reserved for future use
6.2.37.2 QAM ModeAddress 45h
Bit 76543210
Mnemonic FECSADDR4
Type R
Default N/A
BIT MNEMONIC NAME DESCRIPTION
7:5 Reserved Reserved for future useDeframer synchronization4 FECSADDR4 Deframer synchronization 0 = Sync not locked1 = Sync locked3:0 Frame error maximum Maximum number of frame errors encountered
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6.2.38 GPIO Alternate Function Select Register
6.2.39 GPIO Output Data Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 4Fh
Default 00h
Bit 76543210
Mnemonic GPIO7FS GPIO6FS Reserved Reserved Reserved Reserved Reserved Reserved
Type R/W R/W R R R R R R
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
The GPIO bit 7 function select bit is used by the host processor to select thealternate function of the GPIO7 device pin.7 GPIO7FS GPIO bit 7 function select
0 = Configures the GPIO7 pin as General Purpose IO bit 7 (default).1 = Configures the GPIO7 pin as the host processor INTREQ output.The GPIO bit 6 and GPIO bit 5 function select bit is used by the hostprocessor to select the alternate function for both the GPIO6 and GPIO5device pins.GPIO bit 6 and GPIO bit 56 GPIO6FS 0 = Configures the GPIO6 pin as General Purpose IO bit 6 and GPIO5 pin asfunction select
General Purpose IO bit 5 (default).1 = Configures the GPIO5 pin as the SYNCOUT output. The GPIO6 pin isreserved.5:2 — Reserved Reserved for future use
NOTE: The GPIO1 pin is dedicated to Smart Antenna support. This pinoutputs the direction of the signal on pin 29 in Smart Antenna 1-pin mode (see1 — Reserved register 5Fh, bit 0).If GPIO1 = 0, signal input from antenna to TVP9900 pin 29If GPIO1 = 1, signal output from TVP9900 pin 29 to antenna
NOTE: The GPIO0 pin has an alternate function, which is the Antenna ControlInterface input (ANTCNTLIN) when 2-pin mode is selected for this interface.0 — Reserved
See the Antenna Control Interface Control and Status Register (5Fh), bit 0 (pinmode select), for information on how to select this alternate function.
Address 50h
Default 00h
Bit 76543210
Mnemonic GPDO7 GPDO6 GPDO5 GPDO4 GPDO3 GPDO2 Reserved GPDO0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
General purpose data General purpose data output bit 7 is used by the host processor to set the data7 GPDO7
output bit 7 value on the GPIO7 device pin.General purpose data General purpose data output bit 6 is used by the host processor to set the data6 GPDO6
output bit 6 value on the GPIO6 device pin.General purpose data General purpose data output bit 5 is used by the host processor to set the data5 GPDO5
output bit 5 value on the GPIO5 device pin.General purpose data General purpose data output bit 4 is used by the host processor to set the data4 GPDO4
output bit 4 value on the GPIO4 device pin.General purpose data General purpose data output bit 3 is used by the host processor to set the data3 GPDO3
output bit 3 value on the GPIO3 device pin.General purpose data General purpose data output bit 2 is used by the host processor to set the data2 GPDO2
output bit 2 value on the GPIO2 device pin.1 — Reserved Reserved for future useGeneral purpose data General purpose data output bit 0 is used by the host processor to set the data0 GPDO0
output bit 0 value on the GPIO0 device pin.
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6.2.40 GPIO Output Enable Register
6.2.41 GPIO Input Data Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 51h
Default FFh
Bit 76543210
Mnemonic GPIO7OE GPIO6OE GPIO5OE GPIO4OE GPIO3OE GPIO2OE Reserved GPIO0OE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 11111111
BIT MNEMONIC NAME DESCRIPTION
General purpose IO bit 7 output enable is used by the host processor toGeneral purpose IO bit 7 configure the GPIO7 device pin as either an input or output.7 GPIO7OE
output enable 0 = Configures GPIO7 as an output1 = Configures GPIO7 as an input (default)General purpose IO bit 6 output enable is used by the host processor toGeneral purpose IO bit 6 configure the GPIO6 device pin as either an input or output.6 GPIO6OE
output enable 0 = Configures GPIO6 as an output1 = Configures GPIO6 as an input (default)General purpose IO bit 5 output enable is used by the host processor toGeneral purpose IO bit 5 configure the GPIO5 device pin as either an input or output.5 GPIO5OE
output enable 0 = Configures GPIO5 as an output1 = Configures GPIO5 as an input (default)General purpose IO bit 4 output enable is used by the host processor toGeneral purpose IO bit 4 configure the GPIO4 device pin as either an input or output.4 GPIO4OE
output enable 0 = Configures GPIO4 as an output1 = Configures GPIO4 as an input (default)General purpose IO bit 3 output enable is used by the host processor toGeneral purpose IO bit 3 configure the GPIO3 device pin as either an input or output.3 GPIO3OE
output enable 0 = Configures GPIO3 as an output1 = Configures GPIO3 as an input (default)General purpose IO bit 2 output enable is used by the host processor toGeneral purpose IO bit 2 configure the GPIO2 device pin as either an input or output.2 GPIO2OE
output enable 0 = Configures GPIO2 as an output1 = Configures GPIO2 as an input (default)1 — Reserved Reserved for future useGeneral purpose IO bit 0 output enable is used by the host processor toGeneral purpose IO bit 0 configure the GPIO0 device pin as either an input or output.0 GPIO0OE
output enable 0 = Configures GPIO0 as an output1 = Configures GPIO0 as an input (default)
Address 52h
Default 00h
Bit 76543210
Mnemonic GPDI7 GPDI7 GPDI7 GPDI7 GPDI7 GPDI7 Reserved GPDI7
Type RRRRRRRR
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
General purpose data General purpose data input bit 7 is used by the host processor to read the7 GPDI7
input bit 7 data value on the GPIO7 device pin.General purpose data General purpose data input bit 6 is used by the host processor to read the6 GPDI6
input bit 6 data value on the GPIO6 device pin.General purpose data General purpose data input bit 5 is used by the host processor to read the5 GPDI5
input bit 5 data value on the GPIO5 device pin.General purpose data General purpose data input bit 4 is used by the host processor to read the4 GPDI4
input bit 4 data value on the GPIO4 device pin.
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6.2.42 MPEG Interface Output Enable Register 1
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
BIT MNEMONIC NAME DESCRIPTION
General purpose data General purpose data input bit 3 is used by the host processor to read the3 GPDI3
input bit 3 data value on the GPIO3 device pin.General purpose data General purpose data input bit 2 is used by the host processor to read the2 GPDI2
input bit 2 data value on the GPIO2 device pin.1 — Reserved Reserved for future useGeneral purpose data General purpose data input bit 0 is used by the host processor to read the0 GPDI0
input bit 0 data value on the GPIO0 device pin.
Address 53h
Default 00h
Bit 76543210
Mnemonic DO7OE DO6OE DO5OE DO4OE DO3OE DO2OE DO1OE DO0OE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
MPEG data output bit 7 output enable is used by the host processor to enableMPEG data output bit 7 the output. After power-on reset, the output is disabled.7 DO7OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 6 output enable is used by the host processor to enableMPEG data output bit 6 the output. After power-on reset, the output is disabled.6 DO6OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 5 output enable is used by the host processor to enableMPEG data output bit 5 the output. After power-on reset, the output is disabled.5 DO5OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 4 output enable is used by the host processor to enableMPEG data output bit 4 the output. After power-on reset, the output is disabled.4 DO4OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 3 output enable is used by the host processor to enableMPEG data output bit 3 the output. After power-on reset, the output is disabled.3 DO3OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 2 output enable is used by the host processor to enableMPEG data output bit 2 the output. After power-on reset, the output is disabled.2 DO2OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 1 output enable is used by the host processor to enableMPEG data output bit 1 the output. After power-on reset, the output is disabled.1 DO1OE
output enable 0 = Output is disabled (default)1 = Output is enabledMPEG data output bit 0 output enable is used by the host processor to enableMPEG data output bit 0 the output. After power-on reset, the output is disabled.0 DO0OE
output enable 0 = Output is disabled (default)1 = Output is enabled
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6.2.43 MPEG Interface Output Enable Register 2
6.2.44 Tuner Control Interface – I
2
C Slave Device Address Register
6.2.45 Tuner Control Interface – Data Register 1 Through 8
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 54h
Default 00h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved SYNCSOE DCLKOE
Type R R R R R R R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:2 — Reserved Reserved for future useMPEG sync signals output enable is used by the host processor to enable theMPEG interface sync signals, which are packet clock (PACCLK), byte startMPEG sync signals output (BYTESTART) and data error (DERROR). After power-on reset, the outputs1 SYNCSOE
enable are disabled.
0 = Outputs are disabled (default)1 = Outputs are enabledMPEG data clock output enable is used by the host processor to enable theMPEG data clock output clock output. After power-on reset, the output is disabled.0 DCLKOE
enable 0 = Output is disabled (default)1 = Output is enabled
The I
2
C slave device address register contains the 7-bit I
2
C slave device address and the read/writetransaction control bit to be used for the tuner device.
Address 55h
Default 00h
Bit 76543210
Mnemonic A6 A5 A4 A3 A2 A1 A0 RW
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
The slave device address bits are set by the host processor with the 7-bit I
2
C7:1 A(6:0) Slave device address
slave address of the Tuner device to be accessed.The read/write control bit value is set by the host processor to program thetype of Tuner Control Interface I
2
C transaction to be done.0 RW Read/write control
1 = Read transaction
0 = Write transaction (default)
Address 56h to 5Dh
Default 00h
Bit 76543210
Mnemonic D7 D6 D5 D4 D3 D2 D1 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
Data register 1 through data register 8 contain the data bytes to be sent to thetuner for a write transaction or the data bytes received from the tuner for a7:0 D(7:0) Data (7:0)
read transaction. The data byte contained in data register 1 (56h) shall be thefirst byte sent to or read from the tuner.
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6.2.46 Tuner Control Interface – Control and Status Register
6.2.47 Antenna Control Interface – Control and Status Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 5Eh
Default 00h
Bit 76543210
Mnemonic BCNT2 BCNT2 BCNT2 Reserved Reserved START Reserved MODE
Type R/W R/W R/W R R R/W R R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
The byte count is used by the host processor to set the number of data bytesto be transferred to/from the tuner device. The byte count should not include7:5 BCNT(2:0) Byte count
the tuner I
2
C slave address byte.000b = 1 byte, 001b = 2 bytes, ..., 110b = 7 bytes, 111b = 8 bytes4:3 — Reserved Reserved for future useThe transaction start bit is set to 1 by the host processor to indicate to the2 START Transaction start MCU to start the transaction to the tuner. The MCU clears this bit at the end ofthe transaction.1 — Reserved Reserved for future useThe mode bit is used by the host processor to set the I
2
C transfer mode andrate.0 MODE I
2
C mode
0 = Standard mode and 100-kbps transfer rate (default)1 = Fast mode and 400-kbps transfer rate
Address 5Fh
Default 00h
Bit 76543210
Mnemonic Reserved Reserved RXERR MODE TXSTART TXRXSEL TXDINV PINSEL
Type R R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useThe receive data error bit is set to 1 by the MCU to indicate an error occurred5 RXERR Receive data error when receiving data from a mode B antenna. The MCU clears this bit at thebeginning of the next transaction.The auto receive mode bit is set to 1 by the host processor to enable the4 MODE Auto receive mode antenna control interface logic to automatically set-up the receive mode after atransmit data transaction.This bit is set to 1 by the host processor to start the transmit data transaction3 TXSTART Transmit start
to the antenna. The MCU clears this bit when the transaction is complete.This bit is used by the host processor to select the next type of transaction tobe done by the antenna control interface. In manual mode, the host processorcontrols this bit. In auto receive mode, the host processor sets this bit to 1 for2 TXRXSEL Transmit/receive select the transmit data transaction, and the MCU sets this bit to 0 after thecompletion of the transmit transaction to enable the receive transaction.0 = Receive data transaction1 = Transmit data transactionThe transmit data polarity bit is set to 1 by the host processor to invert thetransmit data output.1 TXDINV Transmit data polarity
0 = Normal polarity in conformance with CEA9091 = Invert the transmit data output
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6.2.48 Antenna Control Interface – Transmit Data Register 1
6.2.49 Antenna Control Interface – Transmit Data Register 2
6.2.50 Antenna Control Interface – Receive Data Register 1
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
BIT MNEMONIC NAME DESCRIPTION
The pin mode select bit is used by the host processor to select the antennacontrol interface pin configuration. Before the 2-pin mode is selected, theGPIO0 pin must be configured as an input in register 51h, bit 0.0 PINSEL Pin mode select
0 = 2-pin mode (separate input and output pins are used, input = pin 72,output = pin 29) (default)1 = 1-pin mode (one bidirectional pin is used, pin 29)
Address 60h
Default 00h
Bit 76543210
Mnemonic TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
The least significant 8 bits of the 14-bit data word to be transmitted to the7:0 TXD(7:0) Transmit data (7:0) antenna. Bits (13:8) are stored in register 61h, bits (5:0). The data word is setby the host processor.
Address 61h
Default 00h
Bit 76543210
Mnemonic Reserved Reserved TXD13 TXD12 TXD11 TXD10 TXD9 TXD8
Type R R R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useThe most significant 6 bits of the 14-bit data word to be transmitted to the5:0 TXD(13:8) Transmit data (13:8)
antenna. The data word is set by the host processor.
Address 62h
Default 00h
Bit 76543210
Mnemonic RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
The least significant 8-bits of the 10-bit program code received from a mode B7:0 RXD(7:0) Receive data (7:0)
antenna. Bits (9:8) are stored in register 63h, bits (1:0).
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6.2.51 Antenna Control Interface – Receive Data Register 2
6.2.52 Firmware ID – ROM Version Register
6.2.53 Firmware ID – RAM Major Version Register
6.2.54 Firmware ID – RAM Minor Version Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 63h
Default 00h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved RXD9 RXD8
Type R R R R R R R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:2 — Reserved Reserved for future useThe most significant 2 bits of the 10-bit program code received from a mode B1:0 RXD(9:8) Receive data (9:8)
antenna.
Address 70h
Default 02h
Bit 76543210
Mnemonic ROMVER
Type R
Default 0x02
BIT MNEMONIC NAME DESCRIPTION
7:0 ROMVER ROM version Version identification for ROM code
Address 71h
Default 00h
Bit 76543210
Mnemonic RAM1VER
Type R
Default 0x00
BIT MNEMONIC NAME DESCRIPTION
7:0 RAM1VER Major RAM version Major version identification for RAM code
Address 72h
Default 00h
Bit 76543210
Mnemonic RAM2VER
Type R
Default 0x00
BIT MNEMONIC NAME DESCRIPTION
7:0 RAM2VER Minor RAM version Minor version identification for RAM code
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6.2.55 Device ID LSB Register
6.2.56 Device ID MSB Register
6.2.57 Miscellaneous Control Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Address 80h
Default 00h
Bit 76543210
Mnemonic DEVID1
Type R
Default 0x00
BIT MNEMONIC NAME DESCRIPTION
7:0 DEVID1 Device ID LSB The LSB of the device ID
Address 81h
Default 99h
Bit 76543210
Mnemonic DEVID2
Type R
Default 0x99
BIT MNEMONIC NAME DESCRIPTION
7:0 DEVID2 Device ID MSB The MSB of the device ID
Address EEh
Default 00h
Bit 76543210
Mnemonic Reserved Reserved Reserved Reserved Reserved INTRQPS MCUMDE MCURST
Type R R R R R R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:3 — Reserved Reserved for future useThe interrupt request pin polarity select bit is used by the host processor toselect either an active low or active high INTREQ output. Note that whenactive low is selected, the output goes tri-state when inactive (not driven high).Interrupt request pin2 INTRQPS Hence a pullup resistor needs to be used on the PCB. This is done so interruptpolarity select
request sources from multiple ICs can be wired together.0 = INTREQ output pin is active low (default)1 = INTREQ output pin is active highThe MCU memory mode is used by the host processor to select ROM or RAMas the code memory for the internal TVP9900 MCU.1 MCUMDE MCU memory mode
0 = MCU executes from ROM (default)1 = MCU executes from RAMThe MCU reset bit is used by the host processor to do a soft reset of theinternal TVP9900 MCU.0 MCURST MCU reset
0 = MCU not in reset mode (default)1 = MCU in reset mode
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6.2.58 Software Interrupt Raw Status Register
6.2.59 Software Interrupt Status Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The raw status bits in this register are cleared by the host processor by writing a 1 to the corresponding bitin the Software Interrupt Clear Register (FFh). The intended use of the raw status registers is for events tobe monitored by the host processor via polling instead of interrupt driven.
Address F9h
Default 00h
Bit 76543210
Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE
Type RRRRRRRR
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useThe Antenna Control Interface receive transaction complete raw status bit isset to 1 by the MCU when the receive transaction from a mode B antenna iscomplete. This means an entire 10-bit data word was received. If anAntenna Control Interface
incomplete receive transaction (less than 10-bits) occurs, then this bit is not5 ACIRXCT receive transaction
set; instead the ACIRXTO (bit 3) occurs. After the receive transaction iscomplete
complete, the host processor should also check the receive data error statusbit (RXERR) in the Antenna Control Interface Control and Status Register(5Fh) to ensure that an error was not detected while receiving the data.Antenna Control Interface
The Antenna Control Interface transmit transaction complete raw status bit is4 ACITXCT transmit transaction
set to 1 by the MCU when the transmit transaction to the antenna is complete.complete
The Antenna Control Interface receive timeout raw status bit is set to 1 by theMCU when the 100-ms timeout has occurred. If a 100-ms timeout occurs, thenAntenna Control Interface the antenna either did not reply to the transmit transaction (it is a mode A3 ACIRXTO
receive timeout antenna) or an incomplete (less than 10-bits) receive transaction occurred. Ifan incomplete transaction occurred, then the receive error status bit (RXERR)in the Antenna Control Interface Control and Status Register (5Fh) is also set.2 — Reserved Reserved for future useThe Tuner Control Interface transaction error raw status bit is set to 1 by theTuner Control Interface MCU to indicate to the host processor that the tuner device did not respond to1 TCIERROR
transaction error the I
2
C transaction or that a NO ACK was received from the tuner when anACK was expected.The Tuner Control Interface transaction done raw status bit is set to 1 by theTuner Control Interface MCU at the end of a normal transaction to indicate to the host processor that0 TCIDONE
transaction done the tuner I
2
C transaction completed successfully. If an error occurs during atransaction to the tuner, the MCU does not set this bit to 1.
The status bits in this register are the result of the logical AND of the corresponding raw status bits andmask bits. A status bit is also automatically cleared when the corresponding raw status bit is cleared.Unmasked status bits in this register assert the host processor interrupt request output pin, INTREQ, ofthe TVP9900 when the status bit is set to 1. All unmasked hardware and software status bits are ORedtogether to drive the INTREQ output pin.
Address FBh
Default 00h
Bit 76543210
Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE
Type RRRRRRRR
Default 00000000
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6.2.60 Software Interrupt Mask Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useAntenna Control Interface The Antenna Control Interface receive complete status bit is set to 1 (if5 ACIRXCT receive transaction unmasked) when the receive transaction from a mode B antenna is completecomplete and the bit is unmasked.Antenna Control Interface The Antenna Control Interface transmit complete status bit is set to 1 (if4 ACITXCT transmit transaction unmasked) when the transmit transaction to the antenna is complete and thecomplete bit is unmasked.Antenna Control Interface The Antenna Control Interface receive timeout status bit is set to 1 (if3 ACIRXTO
receive timeout unmasked) when the 100-ms timeout has occurred and the bit is unmasked.2 — Reserved Reserved for future useThe Tuner Control Interface transaction error status bit is set to 1 (ifTuner Control Interface unmasked) to indicate to the host processor that the tuner device did not1 TCIERROR
transaction error respond to the I
2
C transaction or that a NO ACK was received from the tunerwhen an ACK was expected.The Tuner Control Interface transaction done status bit is set to 1 (ifTuner Control Interface unmasked) at the end of a normal transaction to indicate to the host processor0 TCIDONE
transaction done that the tuner I
2
C transaction completed successfully. If an error occurs duringa transaction to the tuner, the MCU does not set this bit to 1.
The interrupt mask registers are used by the host processor to mask unused interrupt sources. When aninterrupt status bit is masked, the event results in the raw status bit being set but does not result in thestatus bit being set or the assertion of the interrupt request output pin, INTREQ.
Address FDh
Default 00h
Bit 76543210
Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useThis bit is used by the host processor to enable the Antenna Control InterfaceAntenna Control Interface
receive transaction complete interrupt.5 ACIRXCT receive transaction
0 = Interrupt disabled (default)complete interrupt mask
1 = Interrupt enabledThis bit is used by the host processor to enable the Antenna Control InterfaceAntenna Control Interface
transmit transaction complete interrupt.4 ACITXCT transmit transaction
0 = Interrupt disabled (default)complete interrupt mask
1 = Interrupt enabledThis bit is used by the host processor to enable the Antenna Control InterfaceAntenna Control Interface
receive timeout interrupt.3 ACIRXTO receive timeout interrupt
0 = Interrupt disabled (default)mask
1 = Interrupt enabled2 — Reserved Reserved for future useThis bit is used by the host processor to enable the Tuner Control InterfaceTuner Control Interface
transaction error interrupt.1 TCIERROR transaction error interrupt
0 = Interrupt disabled (default)mask
1 = Interrupt enabledThis bit is used by the host processor to enable the Tuner Control InterfaceTuner Control Interface
transaction done interrupt.0 TCIDONE transaction done interrupt
0 = Interrupt disabled (default)mask
1 = Interrupt enabled
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6.2.61 Software Interrupt Clear Register
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The interrupt clear registers are used by the host processor to clear the interrupt raw status and statusbits. To clear an interrupt, a 1 must be written to the corresponding bit in this register. The interrupt clearbits are automatically reset to 0 by the TVP9900 hardware. When all unmasked interrupts are cleared, theINTREQ device output pin is inactive.
Address FFh
Default 00h
Bit 76543210
Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE
Type WWWWWWWW
Default 00000000
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future useAntenna Control Interface This bit should be set to 1 by the host processor to clear the Antenna5 ACIRXCT receive transaction complete Control Interface receive transaction complete raw status bit, which alsointerrupt clear clears the status bit and interrupt if unmasked.Antenna Control Interface This bit should be set to 1 by the host processor to clear the Antenna4 ACITXCT transmit transaction complete Control Interface transmit transaction complete raw status bit, which alsointerrupt clear clears the status bit and interrupt if unmasked.This bit should be set to 1 by the host processor to clear the AntennaAntenna Control Interface3 ACIRXTO Control Interface receive timeout raw status bit, which also clears thereceive timeout interrupt clear
status bit and interrupt if unmasked.2 — Reserved Reserved for future useTuner Control Interface This bit should be set to 1 by the host processor to clear the Tuner Control1 TCIERROR transaction error interrupt Interface transaction error raw status bit, which also clears the status bitclear and interrupt if unmasked.Tuner Control Interface This bit should be set to 1 by the host processor to clear the Tuner Control0 TCIDONE transaction done interrupt Interface transaction done raw status bit, which also clears the status bitclear and interrupt if unmasked.
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7 Electrical Specifications
7.1 Absolute Maximum Ratings
(1)
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
This section provides the absolute maximum ratings and the recommended operating conditions for theTVP9900 device.
All electrical and timing characteristics in this specification shall be valid over the recommended operatingconditions, unless otherwise noted.
over operating free-air temperature range (unless otherwise noted)DVDD_1_5 Supply voltage range 1.5 V digital core supply –0.5 V to 2.1 VIOVDD_3_3 Supply voltage range 3.3 V IO cell supply –0.5 V to 4.2 VAVDD_1_5 Supply voltage range 1.5 V analog core supply –0.5 V to 2.1 VAVDD_3_3 Supply voltage range 3.3 V analog core supply –0.5 V to 4.2 VAVDD_REF_3_3 Supply voltage range 3.3 V reference supply –0.5 V to 4.2 VAVDD_PLL_1_5 Supply voltage range 1.5 V PLL supply –0.5 V to 2.1 VXTALIN, oscillator input –0.5 V to AVDD_PLL_1_5 + 0.5 VV
I
Input voltage range Fail-safe LVCMOS –0.5 V to IOVDD_3_3 + 0.5 VDifferential IF inputs: AIFIN_P, AIFIN_N –0.5 V to AVDD_3_3 + 0.5 VXTALOUT, oscillator output –0.5 V to AVDD_PLL_1_5 + 0.5 VV
O
Output voltage range
Fail-safe LVCMOS –0.5 V to IOVDD_3_3 + 0.5 VI
IK
Input clamp current V
I
< 0 or V
I
> V
CC
±20 mAI
OK
Output clamp current V
O
< 0 or V
O
> V
CC
±20 mAT
A
Operating free-air temperature range 0 °C to 70 °CT
stg
Storage temperature range –65 °C to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommendedoperating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
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7.2 Recommended Operating Conditions
7.3 DC Electrical Characteristics
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
MIN NOM MAX UNIT
DVDD_1_5 1.5-V digital core supply voltage 1.35 1.5 1.65 VIOVDD_3_3 3.3-V IO cell supply voltage 3 3.3 3.6 VAVDD_1_5 1.5-V analog core supply voltage 1.35 1.5 1.65 VAVDD_3_3 3.3-V analog core supply voltage 3 3.3 3.6 VAVDD_PLL_1_5 1.5-V PLL supply voltage 1.35 1.5 1.65 VAVDD_REF_3_3 3.3-V reference supply voltage 3 3.3 3.6 VXTALIN 0 AVDD_PLL_1_5V
I
Input voltage VLVCMOS 0 IOVDD_3_3XTALOUT 0 AVDD_PLL_1_5V
O
Output voltage VLVCMOS 0 IOVDD_3_3XTALIN 0.7(AVDD_PLL_1_5) AVDD_PLL_1_5V
IH
High-level input voltage VLVCMOS 0.7(IOVDD_3_3) IOVDD3_3XTALIN 0 0.3(AVDD_PLL_1_5)V
IL
Low-level input voltage VLVCMOS 0 0.3(IOVDD_3_3)I
OH
High-level output current LVCMOS –8 mAI
OL
Low-level output current LVCMOS 8 mAXTALIN 25f
clock
Clock input frequency MHzCLKIN 25t
t
Input transition, rise and fall time, 10% to 90% 0 25 nsT
A
Operating free-air temperature 0 25 70 °CT
J
Operating junction temperature 0 25 105 °C
over recommended operating conditions (unless otherwise noted)
TESTPARAMETER MIN TYP MAX UNITCONDITIONS
V
OH
High-level output voltage LVCMOS I
OH
= –8 mA 0.8(IOVDD_3_3) VV
OL
Low-level output voltage LVCMOS I
OL
= 8 mA 0.22(IOVDD_3_3) VI
IL
Low-level input current V
I
= V
IL
(min) ±1µAI
IH
High-level input current V
I
= V
IH
(max) ±1µAI
OZ
High-impedance output current ±20 µAI
DVDD_1_5
1.5-V digital core supply current
(1)
630 mAI
IOVDD_3_3
3.3-V IO cell supply current
(1)
3 mAI
AVDD_1_5
1.5-V analog core supply current
(1)
0.2 mAI
AVDD_3_3
3.3-V analog core supply current
(1)
45 mAI
AVDD_PLL_1_5
1.5-V analog PLL supply current
(1)
5 mAI
AVDD_REF_3_3
3.3-V analog reference supply current
(1)
22 mA8-VSB mode withparallel MPEG 1.2 WP
D
Power dissipation
output
(1)
Power-down mode 0.45 mWC
i
Input capacitance 8 pFC
o
Output capacitance 8 pF
(1) For typical values: nominal voltages, T
A
= 25 °C
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7.4 Analog Input Characteristics
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
over recommended operating conditions (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I
Differential input voltage C
coupling
= 0.1 µF 1 Vp-pR
I
Input resistance 2.4 k ΩC
I
Differential input capacitance 10 pFInput gain control –6 0 6 dBInput gain control ratio –3 3 %
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7.5 Timing Characteristics
7.5.1 Crystal and Input Clock
XTALIN
tcyc1
7.5.2 Device Reset
RESESTZ
VDD (all supplies)
tW1(L)
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
over recommended operating conditions (unless otherwise noted)
The TVP9900 can be used with an external crystal with a frequency of 25 MHz or with an external clock sourcewith a frequency of 4 MHz or 25 MHz. The on-chip oscillator in the TVP9900 is designed to work with an externalcrystal with a frequency range of 15 MHz to 35 MHz. Therefore, if a clock frequency of 4 MHz is required, anexternal clock source, not an external crystal, must be used. When an external clock source is used, the on-chiposcillator simply functions as an input buffer.
Table 7-1. Crystal and Input Clock Timing
PARAMETER MIN TYP MAX UNIT
f
XTALIN
Frequency, XTALIN (external crystal or clock source) 25 MHzt
cyc1
Cycle time, XTALIN (external crystal or clock source)
(1)
40 nsf
XTALIN
Frequency, XTALIN (external clock source only) 4 MHzt
cyc1
Cycle time, XTALIN (external clock source only)
(1)
250 nsFrequency stability –50 50 ppm
(1) Worst-case duty cycle is 45/55.
Figure 7-1. Crystal or Clock Timing Waveform
The power-on reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device atpower-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of 1 msafter all power-supply voltages are stable at the recommended operating voltage. Internal circuits synchronizethe power-on reset with internal clocks; therefore, the RESETZ signal must remain active low for a minimum of1µs after the crystal oscillator and clocks are stable.
Table 7-2. Device Reset Timing
PARAMETER MIN TYP MAX UNIT
Pulse duration, RESETZ low after all power supplies are stable at the recommendedt
w1(L)
1 msoperating voltage and the crystal oscillator is stable
Figure 7-2. Device Reset Signal Timing Waveforms
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7.5.3 MPEG Interface
7.5.3.1 Parallel Mode (Data Only)
PACCLK
DCLK
DATAOUT [7:0]
tpd1
Byte 0 Byte 1 Byte 187 Byte 0
BYTE_START
DERROR
Byte 186
tpd2 tpd3
tpd4 tpd5
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms inFigure 7-3 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the outputsignals transitioning with respect to the falling edge of DCLK. In this mode, PACCLK is always active. If an erroroccurs, the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes.
Table 7-3. Parallel Mode (Data Only) Timing
C
L
= 30 pF
PARAMETER MIN TYP MAX UNIT
8 VSB mode 2.42408f
DCLK
Frequency, DCLK 64 QAM mode 3.37129 MHz256 QAM mode 4.85133d
cyc
Duty cycle, DCLK 50 %t
pd1
Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid –2 3 nst
pd2
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high –2 3 nst
pd3
Propagation delay time, DCLK falling (or rising) edge to BYTE_START low –2 3 nst
pd4
Propagation delay time, DCLK falling (or rising) edge to DERROR high –2 3 nst
pd5
Propagation delay time, DCLK falling (or rising) edge to DERROR low –2 3 ns
Figure 7-3. MPEG Interface – Parallel Mode (Data Only) Timing Waveforms
Submit Documentation Feedback Electrical Specifications 55
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7.5.3.2 Serial Mode (Data Only)
PACCLK
DCLK
SERDATAO D7
BYTE_START
DERROR
D0 D7 D0 D7
tpd1
tpd2 tpd3
tpd4 tpd5
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms inFigure 7-4 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the outputsignals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cyclescorresponding to the eight bits of the first byte of data. In this mode, PACCLK is always active. If an error occurs,the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes.
Table 7-4. Serial Mode (Data Only) Timing
C
L
= 30 pF
PARAMETER MIN TYP MAX UNIT
8 VSB mode 19.39266f
DCLK
Frequency, DCLK 64 QAM mode 26.97035 MHz256 QAM mode 38.81070d
cyc
Duty cycle, DCLK 50 %t
pd1
Propagation delay time, DCLK falling (or rising) edge to SERDATAO valid –2 3 nst
pd2
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high –2 3 nst
pd3
Propagation delay time, DCLK falling (or rising) edge to BYTE_START low –2 3 nst
pd4
Propagation delay time, DCLK falling (or rising) edge to DERROR high –2 3 nst
pd5
Propagation delay time, DCLK falling (or rising) edge to DERROR low –2 3 ns
Figure 7-4. MPEG Interface – Serial Mode (Data Only) Timing Waveforms
Electrical Specifications56 Submit Documentation Feedback
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7.5.3.3 Parallel Mode (Data With Redundancy)
PACCLK
DCLK
DATAOUT [7:0]
tpd1
Byte 0 Byte 1
BYTE_START
DERROR
Byte 187
tpd2 tpd3
tpd4 tpd5
tpd6 tpd7
Byte 0
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms inFigure 7-5 are shown with BYTE_START, PACCLK and DERROR as active high signals and with the outputsignals transitioning with respect to the falling edge of DCLK. PACCLK is only active during the time period thatthe 188 bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of theentire packet.
Table 7-5. Parallel Mode (Data With Redundancy) Timing
C
L
= 30 pF
PARAMETER MIN TYP MAX UNIT
8 VSB mode 2.68196f
DCLK
Frequency, DCLK 64 QAM mode 3.65821 MHz256 QAM mode 5.26422d
cyc
Duty cycle, DCLK 50 %t
pd1
Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid –2 3 nst
pd2
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high –2 3 nst
pd3
Propagation delay time, DCLK falling or rising edge to BYTE_START low –2 3 nst
pd4
Propagation delay time, DCLK falling (or rising) edge to PACCLK high –2 3 nst
pd5
Propagation delay time, DCLK falling (or rising) edge to PACCLK low –2 3 nst
pd6
Propagation delay time, DCLK falling (or rising) edge to DERROR high –2 3 nst
pd7
Propagation delay time, DCLK falling (or rising) edge to DERROR low –2 3 ns
Figure 7-5. MPEG Interface – Parallel Mode (Data With Redundancy) Timing Waveforms
Submit Documentation Feedback Electrical Specifications 57
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7.5.3.4 Serial Mode (Data With Redundancy)
D7 D0 D0 D7
PACCLK
DCLK
SERDATAO
BYTE_START
DERROR
D7
tpd1
tpd2
tpd4
tpd6
tpd3
tpd5
tpd7
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms inFigure 7-6 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the outputsignals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cyclescorresponding to the eight bits of the first byte of data. PACCLK is only active during the time period that the 188bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the entirepacket.
Table 7-6. Serial Mode (Data With Redundancy) Timing
C
L
= 30 pF
PARAMETER MIN TYP MAX UNIT
8 VSB mode 2.42408f
DCLK
Frequency, DCLK 64 QAM mode 3.37129 MHz256 QAM mode 4.85133d
cyc
Duty cycle, DCLK 50 %t
pd1
Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid 3 nst
pd2
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high 3 nst
pd3
Propagation delay time, DCLK falling (or rising) edge to BYTE_START low 3 nst
pd4
Propagation delay time, DCLK falling (or rising) edge to DERROR high 3 nst
pd5
Propagation delay time, DCLK falling (or rising) edge to DERROR low 3 ns
Figure 7-6. MPEG Interface – Serial Mode (Data with Redundancy) Timing Waveforms
Electrical Specifications58 Submit Documentation Feedback
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7.5.4 Host and Tuner I
2
C Interface
SCL
SDA
tw(H) tw(L) trtf
tsu1 th1
Start Condition Stop Condition
SCL
SDA
tsu2
th2
tsu3
tbuf
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Host processor communication with the TVP9900 device is done via an I
2
C slave interface. The TVP9900 alsohas an I
2
C master interface that is used by the TVP9900 to communicate with the system tuner. Both of theseI
2
C interfaces are designed to work for both standard and fast modes of operation. The timing parameters andthe timing waveforms below pertain to both I
2
C interfaces.
Table 7-7. Host and Tuner I
2
C Interface Timing
STANDARD FASTMODE MODEPARAMETER UNITMIN MAX MIN MAX
f
SCL
Frequency, SCL 0 100 0 400 kHzt
W(H)
Pulse duration, SCL high 4 0.6 µst
W(L)
Pulse duration, SCL low 4.7 1.3 µst
r
Rise time, SCL and SDA 1000 300 nst
f
Fall time, SCL and SDA 300 300 nst
su1
Setup time, SDA to SCL 250 100 nst
h1
Hold time, SCL to SDA
(1)
0 0 nst
buf
Bus free time between stop and start condition 4.7 1.3 µst
su2
Setup time, SCL to start condition 4.7 0.6 µst
h2
Hold time, start condition to SCL 4 0.6 µst
su3
Setup time, SCL to stop condition 4 0.6 µsC
L
Load capacitance for each bus line 400 400 pF
(1) The TVP9900 internally provides a minimum hold time of 300 ns for the SDA signal in order to bridge the undefined region of the fallingedge of SCL.
Figure 7-7. I
2
C SCL and SDA Timing Waveforms
Figure 7-8. I
2
C Start and Stop Conditions Timing Waveforms
Submit Documentation Feedback Electrical Specifications 59
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8 Application Circuit
A
B
C
D
D
C
B
A
Title
NumberRevisionSize
B
Date: 17-Jul-2006 Sheet of
File: C:\TVP9900\TVP9900 App Circuit.ddb Drawn By:
TVP9900.Sch
DATAOUT[6..0]
DATAOUT7_S0
BYTE_VALID
PACK_SYNC
DCLK
D_ERROR
D3.3V D1.5V
C1
0.1uF
R1
24K 0.1%
DGND
DGND
A_REF_3.3V
D3.3V
A3.3V
A1.5V
C2
0.1uF
C3
0.1uF
Put AC Coupling Close to TVP9900
ANTCNTL ANTCNTL
TUNER_IF_OUT1
TUNER_IF_OUT2
R12
1.5K
C21
0.01uF
AGCOUT
DGND
AGCOUT
DGND
JP2
I2CA0
R10
10K
JP2: TVP9900 I2C Addr Selection
D3.3V
LOW (ON): Address = 0xB8h (default)
HIGH (OFF): Address = 0xBAh
1 2
X1
25MHz
C39
18pF
C40
18pF R7 0
CLKIN_4_25MHz
XTALOUT
XTALREF
APLL_1.5V
XTALIN
R6 0
XTALOUT
XTALIN
XTALREF
DGND
OFF: CLKIN_4MHz
DGND
R9
10K
ON: XTAL_25MHz (default)
JP1
CLKIN_SEL
D3.3V
DGND DGND
HIGH (OFF): PowerDown Mode
LOW (ON): Normal Operation (default)
JP3: POWERDOWN (Active High)
PWRDOWN
DGND
JP3
PWRDOWN
R11
10K
D3.3V
DEM_SDA_3_3V
DEM_SCL_3_3V
GPIO7_INTREQ
GPIO6_LOCK
GPIO5_SYNC
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
DEM_SCL_3_3V
DEM_SDA_3_3V
TUNSDA
TUNSCL
DGND
DGND DGND
DGND
C24
0.1uF
C4
0.01uF
C8
0.01uF
C26
0.1uF
C7
0.01uF
C25
0.1uF
C5
0.01uF
C22
0.1uF
APLL_1.5V
A1.5V
A_REF_3.3V
A3.3V
C6
0.01uF
C23
0.1uF
D3.3V
D3.3V
C30
0.1uF
C9
0.01uF
C27
0.1uF
C10
0.01uF
C29
0.1uF
C12
0.01uF
C31
0.1uF
C13
0.01uF
C28
0.1uF
C11
0.01uF
DGND
DGND
C14
0.01uF
C15
0.01uF
C17
0.01uF
C18
0.01uF
C16
0.01uF
C19
0.01uF
C20
0.01uF
C35
0.1uF
C32
0.1uF
C34
0.1uF
C36
0.1uF
C33
0.1uF
C37
0.1uF
C38
0.1uF
D1.5V
D1.5V
DGND
DGND
nRESET
AGND
1
AVDD _3_3
2
AIFIN_P
3
AIFIN_N
4
AVDD _3_3
5
AGND
6
AVDD _1_5
7
AGND
8
AGND_PLL
9
AVDD_PLL_1_5
10
XTALOUT
11
XTALREF
12
XTALIN
13
CLKIN
14
DIVINSEL
15
CLKOUT
16
DGND
17
DVDD_1_5
18
IOGND
19
IOVDD_3_3
20
RESETZ
21
TMSEL0
22
TMSEL1
23
DGND
24
DVDD_1_5
25
TMSEL2
26
TMSEL3
27
AGCOUT
28
ANTCNTLIO
29
TUNSDA
30
TUNSCL
31
IOGND
32
IOVDD_3_3
33
I2CSDA
34
I2CSCL
35
DGND
36
DVDD_1_5
37
I2CA0
38
PWRDOWN
39
DERROR
40
DGND 41
DCLK 42
IOGND 43
IOVDD_3_3 44
BYTESTART 45
PACCLK 46
DGND47
DVDD_1_5 48
DATAOUT7/SERDATA0 49
DATAOUT6 50
DATAOUT5 51
IOGND 52
IOVDD_3_3 53
DATAOUT4 54
DATAOUT3 55
DATAOUT2 56
DGND 57
DVDD_1_5 58
DATAOUT1 59
DATAOUT0 60
GPIO7/INTREQ 61
GPIO6/LOCK 62
IOGND 63
IOVDD_3_3 64
GPIO5/SYNCOUT 65
GPIO4 66
GPIO3 67
DVDD_1_5 68
DGND 69
GPIO2 70
GPIO1 71
GPIO0/ANTCNTLIN 72
DVDD_1_5 73
DGND 74
AGND 75
AGND_REF 76
AVDD_RE F_3_3 77
BIASRES 78
BGREFCAP 79
NSUB 80
PWRPAD
U1
TVP9900
DNP R6 and R7 for 4MHz Input from Tuner
Place R6, R7 and R8 close to Pins 11 and 13
GPIO7_INTREQ
GPIO6_LOCK
GPIO5_SYNC
DA
TAOUT[6..0]
AIFIN_P
AIFIN_N
R8
0
DNP R8 for 25MHz Input from crystal (default)
DNP
R2
RPACK8-10K
R5
RPACK4-33
R4
RPACK4-33
R3
RPACK4-33
JP1: CLKIN_SEL
DATAOUT0
DATAOUT1
DA
TAOUT2
DATAOUT3
DATAOUT4
DATAOUT5
DA
TAOUT6
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
TVP9900
VSB/QAM Receiver
SLEA064 – MARCH 2007
Application Circuit60 Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TVP9900PFP ACTIVE HTQFP PFP 80 96 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TVP9900PFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Apr-2007
Addendum-Page 1
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