SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. http://onsemi.com LOW POWER SCHOTTKY MODE SELECT - TRUTH TABLE INPUTS OUTPUTS OPERATING MODE Set Reset (Clear) *Undetermined Load "1" (Set) Hold Toggle Load "0" (Reset) * SD CD J K Q Q L H L H H H H H L L H H H H X X X h l h l X X X h h l l H L H H q q L L H H L q q H 16 1 PLASTIC N SUFFIX CASE 648 Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level 16 X = Don't Care 1 l, h (q) = Lower case letters indicate the state of the referenced input SOIC D SUFFIX CASE 751B i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition. GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 1 0 25 70 C SOEIAJ M SUFFIX CASE 966 TA Operating Ambient Temperature Range IOH Output Current - High -0.4 mA IOL Output Current - Low 8.0 mA 16 ORDERING INFORMATION Device Package Shipping SN74LS109AN 16 Pin DIP 2000 Units/Box SN74LS109AD SOIC-16 38 Units/Rail SN74LS109ADR2 SOIC-16 2500/Tape & Reel SN74LS109AM SOEIAJ-16 See Note 1 SN74LS109AMEL SOEIAJ-16 See Note 1 1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2001 June, 2001 - Rev. 7 1 Publication Order Number: SN74LS109A/D LOGIC DIAGRAM SET (SD) 5(11) Q 6(10) CLEAR (CD) 1(15) CLOCK 4(12) Q 7(9) J 2(14) K 3(13) LOGIC SYMBOL 5 2 4 3 J SD Q 11 6 CP K C Q D 7 14 J SD Q 12 CP 13 K C Q D 1 10 9 15 VCC = PIN 16 GND = PIN 8 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Typ 2.0 0.8 -0.65 2.7 IOS Output Short Circuit Current (Note 1) ICC Power Supply Current Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = -18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 40 A VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V -0.4 -0.8 mA VCC = MAX, VIN = 0.4 V -100 mA VCC = MAX 8.0 mA VCC = MAX J, K, Clock Set, Clear Input LOW Current J, K, Clock Set, Clear -1.5 3.5 Input HIGH Current J, K, Clock Set, Clear IIL Max 0.1 0.2 -20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 2 AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol Parameter fMAX Maximum Clock Frequency tPLH tPHL Clock Clear, Clear Set to Output Clock, Min Typ 25 33 Max Unit Test Conditions MHz 13 25 ns 25 40 ns Max Unit VCC = 5 5.0 0V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Parameter Min Clock High Clear, Set Pulse Width 25 ns ts Data Setu Setup Time -- HIGH Data Setup Time -- LOW 20 ns 20 ns th Hold time 5.0 ns Symbol tW Typ http://onsemi.com 3 Test Conditions VCC = 5 5.0 0V PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE -T- K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 9 1 8 -B- P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 4 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 PACKAGE DIMENSIONS M SUFFIX SOEIAJ PACKAGE CASE 966-01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) http://onsemi.com 5 DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.031 Notes http://onsemi.com 6 Notes http://onsemi.com 7 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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