ADS7816E/250 - Texas Instruments - Datasheet.Technology

ADS7816

DESCRIPTION

The ADS7816 is a 12-bit, 200kHz sampling analog-

to-digital converter. It features low power operation

with automatic power down, a synchronous serial

interface, and a differential input. The reference volt-

age can be varied from 100mV to 5V, with a corre-

sponding resolution from 24µV to 1.22mV.

Low power, automatic power down, and small size

make the ADS7816 ideal for battery operated systems

or for systems where a large number of signals must be

acquired simultaneously. It is also ideal for remote

and/or isolated data acquisition. The ADS7816 is

available in an 8-pin plastic mini-DIP, an 8-lead SOIC,

or an 8-lead MSOP package.

12-Bit High Speed Micro Power Sampling

ANALOG-TO-DIGITAL CONVERTER

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

FEATURES

●200kHz SAMPLING RATE

●MICRO POWER:

1.9mW at 200kHz

150µW at 12.5kHz

●POWER DOWN: 3µA Max

●8-PIN MINI-DIP, SOIC, AND MSOP

●DIFFERENTIAL INPUT

●SERIAL INTERFACE

APPLICATIONS

●BATTERY OPERATED SYSTEMS

●REMOTE DATA ACQUISITION

●ISOLATED DATA ACQUISITION

SAR Control

Serial

Interface

OUT

Comparator

S/H Amp CS/SHDN

DCLOCK

+In

REF

–In CDAC



OPA658

ADS7816

SBAS061

ADS7816

SPECIFICATIONS

At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.

ADS7816 ADS7816B ADS7816C

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

ANALOG INPUT

Full-Scale Input Span +In – (–In) 0

REF

✻✻✻✻V

Absolute Input Voltage +In –0.2

+0.2

✻✻✻✻V

–In –0.2 +0.2 ✻✻✻✻V

Capacitance 25 ✻✻pF

Leakage Current ±1✻✻µA

SYSTEM PERFORMANCE

Resolution 12 ✻✻Bits

No Missing Codes 11 12 ✻Bits

Integral Linearity Error ±0.5 ±2±0.5 ±2±0.5 ±1 LSB(1)

Differential Linearity Error ±0.5 ±2±0.5 ±1±0.25 ±0.75 LSB

Offset Error ±4✻✻LSB

Gain Error ±4✻✻LSB

Noise 33 ✻✻µVrms

Power Supply Rejection 82 ✻✻dB

SAMPLING DYNAMICS

Conversion Time 12 ✻✻

Clk Cycles

Acquisition Time 1.5 ✻✻

Clk Cycles

Throughput Rate 200 ✻✻kHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion VIN = 5.0Vp-p at 1kHz –84 ✻✻dB

VIN = 5.0Vp-p at 5kHz –82 ✻✻dB

SINAD VIN = 5.0Vp-p at 1kHz 72 ✻✻dB

Spurious Free Dynamic Range VIN = 5.0Vp-p at 1kHz 86 ✻✻dB

REFERENCE INPUT

Voltage Range 0.1 5 ✻✻✻✻V

Resistance

CS = GND, f

SAMPLE

= 0Hz

5✻✻GΩ

CS = VCC 5✻✻GΩ

Current Drain At Code 710h 38 100 ✻✻ ✻✻µA

SAMPLE

= 12.5kHz

2.4 20 ✻✻ ✻✻µA

CS = VCC 0.001 3 ✻✻ ✻✻µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻✻

Logic Levels:

VIH IIH = +5µA3

+VCC +0.

3✻✻✻✻V

VIL IIL = +5µA –0.3 0.8 ✻✻✻✻V

VOH IOH = –250µA 3.5 ✻✻V

VOL IOL = 250µA 0.4 ✻✻V

Data Format Straight Binary ✻✻

POWER SUPPLY REQUIREMENTS

VCC Specified Performance 4.50 5.25 ✻✻✻✻V

Quiescent Current 380 700 ✻✻ ✻✻µA

SAMPLE = 12.5kHz(2, 3) 30 ✻✻µA

SAMPLE = 12.5kHz(3) 280 400 ✻✻µA

Power Down

CS =

VCC

, f

SAMPLE

= 0Hz

3✻✻µA

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻✻✻°C

✻ Specifications same as grade to the left.

NOTE: (1) LSB means Least Significant Bit, with VREF equal to +5V, one LSB is 1.22mV. (2) fCLK = 3.2MHz, CS = VCC for 251 clock cycles out of every 256. (3) See

the Power Dissipation section for more information regarding lower sample rates.

ADS7816

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-

formance degradation to complete device failure. Burr-

Brown Corporation recommends that all integrated circuits

be handled and stored using appropriate ESD protection

methods.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

ABSOLUTE MAXIMUM RATINGS(1)

+VCC .....................................................................................................+6V

Analog Input...........................................................–0.3V to (+VCC + 0.3V)

Logic Input .............................................................–0.3V to (+VCC + 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +125°C

External Reference Voltage ..............................................................+5.5V

NOTE: (1) Stresses above these ratings may permanently damage the device.

PIN CONFIGURATION

PIN ASSIGNMENTS

PIN NAME DESCRIPTION

REF Reference Input.

2 +In Non Inverting Input.

3 –In Inverting Input. Connect to ground or to remote ground sense point.

4 GND Ground.

5 CS/SHDN Chip Select when LOW, Shutdown Mode when HIGH.

OUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The

second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.

7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed.

8+V

CC Power Supply.

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM

INTEGRAL DIFFERENTIAL PACKAGE

LINEARITY ERROR LINEARITY ERROR TEMPERATURE DRAWING

PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER(1)

ADS7816P ±2±2 –40°C to +85°C Plastic DIP 006

ADS7816U ±2±2 –40°C to +85°C SOIC 182

ADS7816E ±2±2 –40°C to +85°C MSOP 337

ADS7816PB ±2±1 –40°C to +85°C Plastic DIP 006

ADS7816UB ±2±1 –40°C to +85°C SOIC 182

ADS7816EB ±2±1 –40°C to +85°C MSOP 337

ADS7816PC ±1±0.75 –40°C to +85°C Plastic DIP 006

ADS7816UC ±1±0.75 –40°C to +85°C SOIC 182

ADS7816EC ±1±0.75 –40°C to +85°C MSOP 337

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

1

2

3

8

7

6



DCLOCK

OUT



CS/SHDN

REF



+In

–In

GND

ADS7816



8-Pin PDIP,

8-Lead SOIC,

8-Lead MSOP

ADS7816

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.

CHANGE IN OFFSET vs REFERENCE VOLTAGE

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

Change in Offset (LSB)

12345

Reference Voltage (V)



CHANGE IN OFFSET vs TEMPERATURE

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

Delta from 25°C (LSB)

–55 –40 –25 0 25 70 85

Temperature (°C)

CHANGE IN GAIN vs REFERENCE VOLTAGE

4

3.5

3

2.5

2

1.5

1

0.5

Change in Gain (LSB)

12345

Reference Voltage (V)

CHANGE IN GAIN vs TEMPERATURE

0.15

0.1

0.05

0

–0.05

–0.1

–0.15

Delta from 25°C (LSB)

–55 –40 –25 0 25 70 85

Temperature (°C)

EFFECTIVE NUMBER OF BITS 

vs REFERENCE VOLTAGE

12

11.75

11.5

11.25

11

10.75

10.5

10.25

Effective Number of Bits (rms)

0.1 1 10

Reference Voltage (V)

PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

10

9

8

7

6

5

4

3

2

1

Peak-to-Peak Noise (LSB)

0.1 1 10

Reference Voltage (V)

ADS7816

SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL

80

70

60

50

40

30

20

10

Signal-to-(Noise Ratio Plus Distortion) (dB)

–40 –35 –30 –25 –20 –15 –10 –5 0

Input Level (dB)

SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY

100

90

80

70

60

50

40

30

20

10

Signal-to-(Noise + Distortion) (dB)

1 10 100

Frequency (kHz)

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.

POWER SUPPLY REJECTION vs RIPPLE FREQUENCY

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

Power Supply Rejection (dB)

1 10 100 1000 10000

Ripple Frequency (kHz)

TOTAL HARMONIC DISTORTION vs FREQUENCY

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Total Harmonic Distortion (dB)

1 10 100

Frequency (kHz)

FREQUENCY SPECTRUM

(2048 Point FFT; f

= 9.9kHz, –0.5dB)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

Amplitude (dB)

0 255075100

Frequency (kHz)

SPURIOUS FREE DYNAMIC RANGE and

SIGNAL-TO-NOISE RATIO vs FREQUENCY

100

90

80

70

60

50

40

30

20

10

Spurious Free Dynamic Range

and Signal-to-Noise Ratio (dB)

1 10 100

Frequency (kHz)

Spurious Free Dynamic Range

Signal-to-Noise Ratio

ADS7816

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.

INTEGRAL LINEARITY ERROR vs CODE

1.00

0.75

0.50

0.25

0.00

–0.25

–0.50

–0.75

–1.00

Integral Linearity Error (LSB)

0 2048 4095

Code

DIFFERENTIAL LINEARITY ERROR vs CODE

1.00

0.75

0.50

0.25

0.00

–0.25

–0.50

–0.75

–1.00

Differential Linearity Error (LSB)

0 2048 4095

Code

CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL

LINEARITY vs REFERENCE VOLTAGE

0.10

0.05

0.00

–0.05

–0.10

–0.15

–0.20

Delta from +5V Reference (LSB)

12345

Reference Voltage (V)

Change in Differential

Linearity (LSB)

Change in Integral

Linearity (LSB)

INPUT LEAKAGE CURRENT vs TEMPERATURE

10

1

0.1

0.01

Leakage Current (nA)

–55 –40 –25 0 25 70 85

Temperature (°C)



SUPPLY CURRENT vs TEMPERATURE

450

400

350

300

250

200

150

Supply Current (µA)

–55 –40 –25 0 25 70 85

Temperature (°C)

SAMPLE

= 12.5kHz

SAMPLE

= 200kHz

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

3

2.5

2

1.5

1

0.5

Supply Current (µA)

–55 –40 –25 0 25 70 85

Temperature (°C)

ADS7816

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.

CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL

LINEARITY vs SAMPLE RATE

1.5

1.0

0.5

0

–0.5

Delta from f

SAMPLE

= 200kHz (LSB)

0 100 200 300 400 500

Sample Rate (kHz)

Change in Integral

Linearity (LSB)

Change in Differential

Linearity (LSB)

REFERENCE CURRENT vs TEMPERATURE

(Code = 710h)

55

50

45

40

35

30

Reference Current (µA)

–55 –40 –25 0 25 70 85

Temperature (°C)

REFERENCE CURRENT vs SAMPLE RATE

(Code = 710h)

40

35

30

25

20

15

10

5

Reference Current (µA)

0 40 80 120 160 200

Sample Rate (kHz)

ADS7816

THEORY OF OPERATION

The ADS7816 is a classic successive approximation register

(SAR) analog-to-digital (A/D) converter. The architecture is

based on capacitive redistribution which inherently includes

a sample/hold function. The converter is fabricated on a 0.6µ

CMOS process. The architecture and process allow the

ADS7816 to acquire and convert an analog signal at up to

200,000 conversions per second while consuming very little

power.

The ADS7816 requires an external reference, an external

clock, and a single +5V power source. The external refer-

ence can be any voltage between 100mV and VCC. The value

of the reference voltage directly sets the range of the analog

input. The reference input current depends on the conversion

rate of the ADS7816.

The external clock can vary between 10kHz (625Hz through-

put) and 3.2MHz (200kHz throughput). The duty cycle of

the clock is essentially unimportant as long as the minimum

high and low times are at least 150ns. The minimum clock

frequency is set by the leakage on the capacitors internal to

the ADS7816.

The analog input is provided to two input pins: +In and –In.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

The digital result of the conversion is clocked out by the

DCLOCK input and is provided serially, most significant bit

first, on the DOUT pin. The digital data that is provided on the

DOUT pin is for the conversion currently in progress—there

is no pipeline delay. It is possible to continue to clock the

ADS7816 after the conversion is complete and to obtain the

serial data least significant bit first. See the Digital Interface

section for more information.

ANALOG INPUT

The +In and –In input pins allow for a differential input signal.

Unlike some converters of this type, the –In input is not re-

sampled later in the conversion cycle. When the converter

goes into the hold mode, the voltage difference between +In

and –In is captured on the internal capacitor array.

The range of the –In input is limited to ±200mV. Because of

this, the differential input can be used to reject only small

signals that are common to both inputs. Thus, the –In input

is best used to sense a remote signal ground that may move

slightly with respect to the local ground potential.

The input current on the analog inputs depends on a number

of factors: sample rate, input voltage, source impedance, and

power down mode. Essentially, the current into the ADS7816

charges the internal capacitor array during the sample pe-

riod. After this capacitance has been fully charged, there is

no further input current. The source of the analog input

voltage must be able to charge the input capacitance (25pF)

to a 12-bit settling level within 1.5 clock cycles. When the

converter goes into the hold mode or while it is in the power

down mode, the input impedance is greater than 1GΩ.

Care must be taken regarding the absolute analog input

voltage. To maintain the linearity of the converter, the –In

input should not exceed GND ±200mV. The +In input

should always remain within the range of GND –200mV to

VCC +200mV. Outside of these ranges, the converter’s lin-

earity may not meet specifications.

REFERENCE INPUT

The external reference sets the analog input range. The

ADS7816 will operate with a reference in the range of 100mV

to VCC. There are several important implications of this.

As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the LSB (least significant bit) size and is equal

to the reference voltage divided by 4096. This means that

any offset or gain error inherent in the A/D converter will

appear to increase, in terms of LSB size, as the reference

voltage is reduced. The typical performance curves of

“Change in Offset vs Reference Voltage” and “Change in

Gain vs Reference Voltage” provide more information.

The noise inherent in the converter will also appear to

increase with lower LSB size. With a 5V reference, the

internal noise of the converter typically contributes only

0.16 LSB peak-to-peak of potential error to the output code.

When the external reference is 100mV, the potential error

contribution from the internal noise will be 50 times larger—

8 LSBs. The errors due to the internal noise are gaussian in

nature and can be reduced by averaging consecutive conver-

sion results.

For more information regarding noise, consult the typical

performance curves “Effective Number of Bits vs Reference

Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”

The effective number of bits (ENOB) figure is calculated

based on the converter’s signal-to-(noise + distortion) ratio

with a 1kHz, 0dB input signal. SINAD is related to ENOB

as follows: SINAD = 6.02 • ENOB +1.76.

With lower reference voltages, extra care should be taken to

provide a clean layout including adequate bypassing, a clean

power supply, a low-noise reference, and a low-noise input

signal. Because the LSB size is lower, the converter will also

be more sensitive to external sources of error such as nearby

digital signals and electromagnetic interference.

The current that must be provided by the external reference

will depend on the conversion result. The current is lowest

at full-scale (FFFh) and is typically 25µA at a 200kHz

conversion rate (25°C). For the same conditions, the current

will increase as the input approaches zero, reaching 50µA at

an output result of 000h. The current does not increase

linearly, but depends, to some degree, on the bit pattern of

the digital output.

ADS7816

SYMBOL

DESCRIPTION MIN TYP MAX UNITS

SMPL

Analog Input Sample TIme 1.5 2.0

Clk Cycles

CONV

Conversion Time 12

Clk Cycles

CYC

Throughput Rate 200 kHz

CSD

CS Falling to 0 ns

DCLOCK LOW

SUCS

CS Falling to 30 ns

DCLOCK Rising

hDO

DCLOCK Falling to 15 ns

Current D

OUT

Not Valid

dDO

DCLOCK Falling to Next 85 150 ns

OUT

Valid

dis

CS Rising to D

OUT

Tri-State 25 50 ns

DCLOCK Falling to D

OUT

50 100 ns

Enabled

OUT

Fall Time 70 100 ns

OUT

Rise Time 60 100 ns

value for one clock period. For the next 12 DCLOCK

periods, DOUT will output the conversion result, most sig-

nificant bit first. After the least significant bit (B0) has been

output, subsequent clocks will repeat the output data but in

a least significant bit first format.

After the most significant bit (B11) has been repeated, DOUT

will tri-state. Subsequent clocks will have no effect on the

converter. A new conversion is initiated only when CS has

been taken HIGH and returned LOW.

The reference current diminishes directly with both conver-

sion rate and reference voltage. As the current from the

reference is drawn on each bit decision, clocking the con-

verter more quickly during a given conversion period will

not reduce the overall current drain from the reference. The

reference current changes only slightly with temperature.

See the curves, “Reference Current vs Sample Rate” and

“Reference Current vs Temperature” in the Typical Perfor-

mance Curves section for more information.

DIGITAL INTERFACE

SERIAL INTERFACE

The ADS7816 communicates with microprocessors and other

digital systems via a synchronous 3-wire serial interface as

shown in Figure 1 and Table I. The DCLOCK signal

synchronizes the data transfer with each bit being transmit-

ted on the falling edge of DCLOCK. Most receiving systems

will capture the bitstream on the rising edge of DCLOCK.

However, if the minimum hold time for DOUT is acceptable,

the system can use the falling edge of DCLOCK to capture

each bit.

A falling CS signal initiates the conversion and data transfer.

The first 1.5 to 2.0 clock periods of the conversion cycle are

used to sample the input signal. After the second falling

DCLOCK edge, DOUT is enabled and will output a LOW

FIGURE 1. ADS7816 Basic Timing Diagrams.

TABLE I. Timing Specifications –40°C to +85°C.

CS/SHDN

DOUT

DCLOCK

tDATA

tSUCS

tCSD

tCYC

tCONV

POWER

DOWN

tSMPL

Note: (1) After completing the data transfer, if further clocks are applied with CS 

LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.



B11

(MSB)B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

(1)

NULL

BIT

HI-ZHI-Z B11 B10 B9 B8

NULL

BIT

CS/SHDN

DOUT

DCLOCK

tCONV tDATA

tSUCS

tCYC

POWER DOWN

tSMPL

Note: (2) After completing the data transfer, if further clocks are applied with CS 

LOW, the ADC will output zeroes indefinitely.

tDATA: During this time, the bias current and the comparator power down and the reference input

becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.

B11

(MSB)B10 B9 B8 B7 B6 B5 B4 B4B3 B3B2 B2B1 B1B0

NULL

BIT

HI-Z HI-Z

B5 B6 B7 B8 B9 B10 B11

(2)

tCSD



ADS7816

DOUT

1.4V

Test Point

3kΩ

100pF

CLOAD



tr

DOUT VOH

VOL

tf

tdDO

thDO

DOUT

DCLOCK

VOH

VOL

VIL

DOUT

Test Point

tdis Waveform 2, ten

tdis Waveform 1

100pF

CLOAD

3kΩ

tdis

CS/SHDN

DOUT

Waveform 1(1)

DOUT

Waveform 2(2)

90%

10%

VIH

B11

ten

CS/SHDN

DCLOCK

VOL

DOUT

VCC

Load Circuit for tdDO, tr, and tfVoltage Waveforms for DOUT Rise and Fall TImes tr, and tf

Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden

Voltage Waveforms for ten

FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.

Voltage Waveforms for tdis

DESCRIPTION ANALOG VALUE

Full Scale Range VREF

Least Significant VREF/4096

Bit (LSB)

Full Scale VREF –1 LSB 1111 1111 1111 FFF

Midscale VREF/2 1000 0000 0000 800

Midscale – 1 LSB VREF/2 – 1 LSB 0111 1111 1111 7FF

Zero 0V 0000 0000 0000 000

Table II. Ideal Input Voltages and Output Codes.

DIGITAL OUTPUT:

STRAIGHT BINARY

BINARY CODE HEX CODE

NOTES: (1) Waveform 1 is for an output with internal conditions such that

the output is HIGH unless disabled by the output control. (2) Waveform 2

is for an output with internal conditions such that the output is LOW unless

disabled by the output control.

DATA FORMAT

The output data from the ADS7816 is in Straight Binary

format as shown in Table II. This table represents the ideal

output code for the given input voltage and does not include

the effects of offset, gain error, or noise.

POWER DISSIPATION

The architecture of the converter, the semiconductor fabrica-

tion process, and a careful design allow the ADS7816 to

convert at up to a 200kHz rate while requiring very little

power. Still, for the absolute lowest power dissipation, there

are several things to keep in mind.

The power dissipation of the ADS7816 scales directly with

conversion rate. The first step to achieving the lowest power

dissipation is to find the lowest conversion rate that will

satisfy the requirements of the system.

In addition, the ADS7816 is in power down mode under two

conditions: when the conversion is complete and whenever

CS is HIGH (see Figure 1). Ideally, each conversion should

occur as quickly as possible, preferably, at a 3.2MHz clock

rate. This way, the converter spends the longest possible

time in the power down mode. This is very important as the

ADS7816

converter not only uses power on each DCLOCK transition

(as is typical for digital CMOS components) but also uses

some current for the analog circuitry, such as the compara-

tor. The analog section dissipates power continuously, until

the power down mode is entered.

Figure 3 shows the current consumption of the ADS7816

versus sample rate. For this graph, the converter is clocked

at 3.2MHz regardless of the sample rate—CS is HIGH for

the remaining sample period. Figure 4 also shows current

consumption versus sample rate. However, in this case, the

DCLOCK period is 1/16th of the sample period—CS is

HIGH for one DCLOCK cycle out of every 16.

There is an important distinction between the power down

mode that is entered after a conversion is complete and the

full power down mode which is enabled when CS is HIGH.

While both power down the analog section, the digital section

is powered down only when CS is HIGH. Thus, if CS is left

LOW at the end of a conversion and the converter is continu-

ally clocked, the power consumption will not be as low as

when CS is HIGH. See Figure 5 for more information.

By lowering the reference voltage, the ADS7816 requires

less current to completely charge its internal capacitors on

both the analog input and the reference input. This reduction

in power dissipation should be weighed carefully against the

resulting increase in noise, offset, and gain error as outlined

in the Reference section. The power dissipation of the

ADS7816 is reduced roughly 10% when the reference volt-

age and input range are changed from 5V to 100mV.

SHORT CYCLING

Another way of saving power is to utilize the CS signal to

short cycle the conversion. Because the ADS7816 places the

latest data bit on the DOUT line as it is generated, the

converter can easily be short cycled. This term means that

the conversion can be terminated at any time. For example,

if only 8-bits of the conversion result are needed, then the

conversion can be terminated (by pulling CS HIGH) after

the 8th bit has been clocked out.

This technique can be used to lower the power dissipation

(or to increase the conversion rate) in those applications

where an analog signal is being monitored until some con-

dition becomes true. For example, if the signal is outside a

predetermined range, the full 12-bit conversion result may

not be needed. If so, the conversion can be terminated after

the first n-bits, where n might be as low as 3 or 4. This

results in lower power dissipation in both the converter and

the rest of the system, as they spend more time in the power

down mode.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS7816 circuitry. This is particularly

true if the reference voltage is low and/or the conversion rate

is high. At 200kHz conversion rate, the ADS7816 makes a bit

decision every 312ns. That is, for each subsequent bit deci-

1000

100

10

Supply Current (µA)

1 10 100 1000

Sample Rate (kHz)

= 25°C

= V

REF

= +5V

CLK

= 3.2MHz

FIGURE 3. Maintaining fCLK at the Highest Possible Rate

Allows Supply Current to Drop Directly with

Sample Rate.

1000

100

10

Supply Current (µA)

1 10 100 1000

Sample Rate (kHz)

= 25°C

= V

REF

= +5V

CLK

= 16 • f

SAMPLE



FIGURE 4. Scaling fCLK Reduces Supply Current Only

Slightly with Sample Rate.

FIGURE 5. Shutdown Current is Considerably Lower with

CS HIGH than when CS is LOW.

60

50

40

30

20

10

Supply Current (µA)

1 10 100 1000

Sample Rate (kHz)

= 25°C

= V

REF

= +5V

CLK

= 16 • f

SAMPLE

CS LOW

(GND)

CS = HIGH (V

)

ADS7816

sion, the digital output must be updated with the results of the

last bit decision, the capacitor array appropriately switched

and charged, and the input to the comparator settled to a

12-bit level all within one clock cycle.

The basic SAR architecture is sensitive to spikes on the

power supply, reference, and ground connections that occur

just prior to latching the comparator output. Thus, during

any single conversion for an n-bit SAR converter, there are

n “windows” in which large external transient voltages can

easily affect the conversion result. Such spikes might origi-

nate from switching power supplies, digital logic, and high

power devices, to name a few. This particular source of error

can be very difficult to track down if the glitch is almost

synchronous to the converter’s DCLOCK signal—as the

phase difference between the two changes with time and

temperature, causing sporadic misoperation.

With this in mind, power to the ADS7816 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the ADS7816 package as possible. In

addition, a 1 to 10µF capacitor and a 10Ω series resistor may

be used to lowpass filter a noisy supply.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to lowpass filter the reference voltage. If the reference

voltage originates from an op amp, be careful that the op-

amp can drive the bypass capacitor without oscillation (the

series resistor can help in this case). Keep in mind that while

the ADS7816 draws very little current from the reference on

average, there are higher instantaneous current demands

placed on the external reference circuitry.

Also, keep in mind that the ADS7816 offers no inherent

rejection of noise or voltage variation in regards to the

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital

results. While high frequency noise can be filtered out as

ADS7816

µP

DCLOCK

OUT

CS/SHDN A

0

Thermocouple

ISO Thermal Block

MUX

OPA237 0.3V

0.4V

0.2V

0.1V

+5V



59kΩ



1kΩ



500kΩ



500Ω



10Ω



0.1µF



10µF C



0.1µF



1MΩ



150kΩ

+5V



0.1µF C



10µF

+5V R



46kΩ



1kΩ



1kΩ



1kΩ



1kΩ

REF

3-Wire

Interface

FIGURE 6. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7816.

described in the previous paragraph, voltage variation due to

the line frequency (50Hz or 60Hz), can be difficult to

remove.

The GND pin on the ADS7816 should be placed on a clean

ground point. In many cases, this will be the “analog”

ground. Avoid connecting the GND pin too close to the

grounding point for a microprocessor, microcontroller, or

digital signal processor. If needed, run a ground trace di-

rectly from the converter to the power supply connection

point. The ideal layout will include an analog ground plane

for the converter and associated analog circuitry.

The –In input pin should be connected directly to ground. In

those cases where the ADS7816 is a large distance from the

signal source and/or the circuit environment contains large

EMI or RFI sources, the –In input should be connected to the

ground nearest the signal source. This should be done with

a signal trace that is adjacent to the +In input trace. If

appropriate, coax cable or twisted-pair wire can be used.

APPLICATION CIRCUITS

Figures 6, 7, and 8 show some typical application circuits for

the ADS7816. Figure 6 uses an ADS7816 and a multiplexer

to provide for a flexible data acquisition circuit. A resistor

string provides for various voltages at the multiplexer input.

The selected voltage is buffered and driven into VREF. As

shown in Figure 6, the input range of the ADS7816 is

programmable to 100mV, 200mV, 300mV, or 400mV. The

100mV range would be useful for sensors such as the

thermocouple shown.

Figure 7 is more complex variation of Figure 6 with in-

creased flexibility. In this circuit, a digital signal processor

designed for audio applications is put to use in running three

ADS7816s and a DAC56. The DAC56 provides a variable

voltage for VREF—enabling the input range of the ADS7816s

to be programmed from 100mV to 3V.

ADS7816

The ADS7816s and the DSP56004 can all be placed into a

power down mode. Or, the DSP56004 can run the ADS7816s

at a full 3.2MHz clock rate while on-board software enables

the ADS7816s as needed. With additional glue logic, the

DSP56004 could be used to run multiple DAC56s or provide

CS controls for each of the three ADS7816s.

FIGURE 7. Flexible Data Acquisition System.

Figure 8 shows a basic data acquisition system. The ADS7816

input range is 0V to 5V, as the reference input is connected

directly to the +5V supply. The 5Ω to 10Ω resistor and 1µF

to 10µF capacitor filter the microcontroller “noise” on the

supply, as well as any high-frequency noise from the supply

itself. The exact values should be picked such that the filter

provides adequate rejection of the noise.

FIGURE 8. Basic Data Acquisition System.

ADS7816

CC



CS

OUT



DCLOCK

REF



+In

–In

GND

5Ω to 10Ω

1µF to

10µF

1µF to

10µF

0.1µF

Microcontroller

+5V

ADS7816

DSP56004

WST

SDO0

SDO1

SDO2

SCKT

SCKR

SDI0

SDI1

WSR



SCK/SCL

MISO/SDA

MOSI/HA0

HREQ

SS/HA2

CS

OUT



DCLOCK

REF



+In

–In

Serial Audio

Interface

Serial Host

Interface

ADS7816

CS

OUT



DCLOCK

REF



+In

–In

ADS7816

DAC56

CS

OUT



DCLOCK

REF



+In

–In

LE

CLK

DATA

OUT

+10µF 0.1µF

10Ω10Ω10Ω

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS7816E/250 ACTIVE MSOP DGK 8 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816E/250G4 ACTIVE MSOP DGK 8 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816E/2K5 ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816E/2K5G4 ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EB/250 ACTIVE MSOP DGK 8 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EB/250G4 ACTIVE MSOP DGK 8 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EB/2K5 ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EB/2K5G4 ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EC/250 ACTIVE MSOP DGK 8 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EC/250G4 ACTIVE MSOP DGK 8 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EC/2K5 ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816EC/2K5G4 ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816P ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

ADS7816PB ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

ADS7816PC ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

ADS7816PG4 ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

ADS7816U ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UB ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UB/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UBG4 ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UC ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UC/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PACKAGE OPTION ADDENDUM

www.ti.com 2-Oct-2006

Addendum-Page 1

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS7816UC/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UCG4 ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS7816UG4 ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Oct-2006

Addendum-Page 2

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