AD5764ASU - Analog Devices, Inc. - Datasheet.Technology

Complete Quad, 14-/16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DACs

Preliminary Technical Data

AD5744/AD5764

Rev. PrD

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FEATURES

Complete quad 14/16-bit digital-to-analog converter (DAC)

Programmable output range: ±10 V, ±10.25 V, or ±10.5 V

±1 LSB max INL error, ±1 LSB max DNL error

Low noise : 60 nV/√Hz

Settling time: 10 µs max

Integrated reference buffers

Internal reference: 10 ppm/°C

On-chip temp sensor: ±5°C accuracy

Output control during power-up/brownout

Programmable short-circuit protection

Simultaneous updating via LDAC

Asynchronous CLR to zero code

Digital offset and gain adjust

Logic output control pins

DSP-/microcontroller-compatible serial interface

Temperature range:−40°C to +85°C

iCMOS™ process technology1

APPLICATIONS

Industrial automation

Open-/closed-loop servo control

Process control

Data acquisition systems

Automatic test equipment

Automotive test and measurement

High accuracy instrumentation

1 For analog systems designers within industrial/instrumentation equipment

OEMs who need high performance ICs at higher voltage levels, iCMOS is a

technology platform that enables the development of analog ICs capable of

30 V and operating at ±15 V supplies while allowing dramatic reductions in

power consumption and package size, and increased AC and DC

performance.

GENERAL DESCRIPTION

The AD5744/AD5764 is a quad, 14/16-bit serial input, voltage

output digital-to analog converter that operates from supply

voltages of ±12 V up to ±15 V. Nominal full-scale output range

is ±10 V, provided are integrated output amplifiers, reference

buffers, internal reference, and proprietary power-up/power-

down control circuitry. It also features a digital I/O port that

may be programmed via the serial interface, and an analog

temperature sensor. The part incorporates digital offset and

gain adjust registers per channel.

The AD5744/AD5764 is a high performance converter that

offers guaranteed monotonicity, integral nonlinearity (INL) of

±1 LSB, low noise and 10 µs settling time and includes an on-

chip 5 V reference with a reference tempco of 10 ppm/°C max.

During power-up (when the supply voltages are changing),

Vout is clamped to 0V via a low impedance path.

The AD5744/AD5764 uses a serial interface that operates at clock

rates of up to 30 MHz and is compatible with DSP and

microcontroller interface standards. Double buffering allows the

simultaneous updating of all DACs. The input coding is

programmable to either twos complement or Offset binary

formats. The asynchronous clear function clears all DAC registers

to either bipolar zero or zero-scale depending on the coding used.

The AD5744/AD5764 is ideal for both closed-loop servo control

and open-loop control applications. The AD5744/AD5764 is

available in a 32-lead TQFP package, and offers guaranteed

specifications over the −40°C to +85°C industrial temperature

range. See Figure 1, the functional block diagram.

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 2 of 36

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics .................................................... 6

Timing Characteristics..................................................................... 7

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Terminology .................................................................................... 13

Typical Performance Characteristics ........................................... 14

General Description ....................................................................... 22

DAC Architecture....................................................................... 22

Reference Buffers........................................................................ 22

Serial Interface ............................................................................ 22

Simultaneous Updating Via LDAC.......................................... 23

Transfer Function....................................................................... 24

Asynchronous Clear (CLR)....................................................... 24

Function Register ....................................................................... 25

Data Register............................................................................... 26

Coarse Gain Register ................................................................. 26

Fine Gain Register...................................................................... 26

offset Register.............................................................................. 27

AD5744/AD5764 Features ............................................................ 28

Analog Output Control ............................................................. 28

Digital Offset and Gain Control............................................... 28

Programmable Short-Circuit Protection ................................ 28

Digital I/O Port........................................................................... 28

Temperature Sensor ................................................................... 28

Local Ground Offset Adjust...................................................... 28

Applications Information .............................................................. 29

Typical Operating Circuit ......................................................... 29

Layout Guidelines........................................................................... 30

Isolated Interface ........................................................................ 30

Microprocessor Interfacing....................................................... 30

Evaluation Board........................................................................ 32

Outline Dimensions....................................................................... 33

Ordering Guide .......................................................................... 33

REVISION HISTORY

4/05—Revision PrD: Preliminary Version

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 3 of 36

FUNCTIONAL BLOCK DIAGRAM

INPUT

REG C

GAIN REG C

OFFSET REG C

DAC

REG C

14/16 DAC C

INPUT

REG D

GAIN REG D

REFERENCE

BUFFERS

OFFSET REG D

DAC

REG D

14/16 DAC D G1

INPUT

REG B

GAIN REG B

OFFSET REG B

DAC

REG B

14/16 DAC B

INPUT

REG A

GAIN REG A

OFFSET REG A

DAC

REG A

14/16

14/16 DAC A

LDAC VREF CD TEMP

RSTINRSTOUTVREF AB

REFGND

AGNDD

VOUTD

AGNDC

VOUTC

AGNDB

VOUTB

AGNDA

VOUTA

ISCC

TEMP

SENSOR

REFERENCE

BUFFERS

SDIN

SCLK

SYNC

SDO

BIN/2SCOMP

CLR

PGND

DGND 5V

REFERENCE

VOLTAGE

MONITOR

AND

CONTROL

INPUT SHIFT

AND

CONTROL

LOGIC

REFOUT

05303-001

Figure 1. Functional Block Diagram

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 4 of 36

SPECIFICATIONS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;

DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter A Grade1 B Grade1 C Grade1 Unit Test Conditions/Comments

ACCURACY

Resolution 16

Bits AD5764

AD5744

Relative Accuracy (INL) ±4 ±2 ±1 LSB max

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic

Bipolar Zero Error ±1 ±1 ±1 mV max At 25°C. Error at other

temperatures obtained using

bipolar zero TC.

Bipolar Zero TC ±2 ±2 ±2 ppm FSR/°C max

Zero Code Error ±1 ±1 ±1 mV max At 25°C. Error at other

temperatures obtained using

zero code TC.

Zero Code TC ±2 ±2 ±2 ppm FSR/°C max

Gain Error ±0.02 ±0.02 ±0.02 % FSR max At 25°C. Error at other

temperatures obtained using

gain TC.

Gain TC 2 2 2 ppm FSR/°C max

DC Crosstalk2 0.5 0.5 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 5 5 V nom ±1% for specified performance

DC Input Impedance 1 1 1 MΩ min Typically 100 MΩ

Input Current ±10 ±10 ±10 µA max Typically ±30 nA

Reference Range 1/5 1/5 1/5 V min/max

Reference Output

Output Voltage 4.999/5.001 4.999/5.001 4.999/5.001 V min/max At 25°C

Reference TC ±10 ±10 ±10 ppm/°C max

Output Noise(0.1 Hz to 10 Hz) 18 18 18 µV p-p typ

Noise Spectral Density 75 75 75 nV/√Hz typ @ 10 kHz

OUTPUT CHARACTERISTICS2

Output Voltage Range3 ±10 ±10 ±10 V min/max AVDD/AVSS = ±11.4 V

±13 ±13 ±13 V min/max AVDD/AVSS = ±16.5 V

Output Voltage TC ±2 ±2 ±2 ppm FSR/°C max

Output Voltage Drift VS Time ±TBD ±TBD ±TBD ppm FSR/1000 Hours

typ

Short Circuit Current 10 10 10 mA max RISCC = 6 KΩ, see Figure X.

Load Current ±1 ±1 ±1 mA max For specified performance

Capacitive Load Stability

RL = ∞ 200 200 200 pF max

RL = 10 kΩ 1000 1000 1000 pF max

DC Output Impedance 0.3 0.3 0.3 Ω max

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 5 of 36

Parameter A Grade1 B Grade1 C Grade1 Unit Test Conditions/Comments

DIGITAL INPUTS2 DVCC = 2.7 V to 5.5 V, JEDEC

compliant

VIH, Input High Voltage 2 2 2 V min

VIL, Input Low Voltage 0.8 0.8 0.8 V max

Input Current ±10 ±10 ±10 µA max Total for All Pins. TA = TMIN to TMAX.

Pin Capacitance 10 10 10 pF max

DIGITAL OUTPUTS (D0,D1, SDO) 2

Output Low Voltage 0.4 0.4 0.4 V max DVCC= 5 V ± 10%, sinking 200 µA

Output High Voltage DVCC – 1 DVCC – 1 DVCC – 1 V min DVCC = 5 V ± 10%, Sourcing 200

µA

Output Low Voltage 0.4 0.4 0.4 V max DVCC = 2.7 V to 3.6 V, Sinking 200

µA

Output High Voltage DVCC – 0.5 DVCC – 0.5 DVCC – 0.5 V min DVCC = 2.7 V to 3.6 V, Sourcing

200 µA

High Impedance Leakage

Current

±1 ±1 ±1 µA max SDO only

High Impedance Output

Capacitance

5 5 5 pF typ SDO only

TEMP SENSOR

Accuracy ±1 ±1 ±1 °C typ At 25°C

±5 ±5 ±5 °C max −40°C < T <+85°C

Output Voltage @ 25°C 1.5 1.5 1.5 V typ

Output Voltage Scale Factor 5 5 5 mV/°C typ

Output Voltage Range 0/3.0 0/3.0 0/3.0 V min/max

Output Load Current 200 200 200 µA max Current source only.

Power On Time 10 10 10 ms typ To within ±5°C

POWER REQUIREMENTS

AVDD/AVSS 11.4/16.5 11.4/16.5 11.4/16.5 V min/max

DVCC 2.7/5.5 2.7/5.5 2.7/5.5 V min/max

Power Supply Sensitivity4

∆VOUT/∆ΑVDD −85 −85 −85 dB typ

AIDD 3.75 3.75 3.75 mA/Channel max Outputs unloaded

AISS 2.75 2.75 2.75 mA/Channel max Outputs unloaded

DICC 1 1 1 mA max VIH = DVCC, VIL = DGND. TBD mA

typ

Power Dissipation 244 244 244 mW typ ±12 V operation output

unloaded

1 Temperature range −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

2 Guaranteed by characterization. Not production tested.

3 Output amplifier headroom requirement is 1.4 V min.

4 Guaranteed by characterization. Not production tested.

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 6 of 36

AC PERFORMANCE CHARACTERISTICS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;

DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and

characterization, not production tested.

Table 2.

Parameter A Grade B Grade C Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 8 8 8 µs typ Full-scale step

10 10 10 µs max

1 1 1 µs max 512 LSB step settling @ 16 Bits

Slew Rate 5 5 5 V/µs typ

Digital-to-Analog Glitch Energy 5 5 5 nV-s typ

Glitch Impulse Peak Amplitude 5 5 5 mV max

Channel-to-Channel Isolation 100 100 100 dB typ

DAC-to-DAC Crosstalk 5 5 5 nV-s typ

Digital Crosstalk 5 5 5 nV-s typ

Digital Feedthrough 1 1 1 nV-s typ Effect of input bus activity on DAC

output under test

Output Noise (0.1 Hz to 10 Hz) 0.1 0.1 0.1 LSB p-p typ

Output Noise (0.1 kHz to 100 kHz)5 45 45 45 µV rms max

1/f Corner Frequency 1 1 1 kHz typ

Output Noise Spectral Density 60 60 60

nV/√Hz typ Measured at 10 kHz

Complete System Output Noise Spectral

Density6

80 80 80 nV/√Hz typ Measured at 10 kHz

5 Guaranteed by design and characterization. Not production tested.

6 Includes noise contributions from integrated reference buffers, 14/16-bit DAC and output amplifier.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 7 of 36

TIMING CHARACTERISTICS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;

DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter7,8,9 Limit at TMIN, TMAX Unit Description

t1 33 ns min SCLK cycle time

t2 13 ns min SCLK high time

t3 13 ns min SCLK low time

t4 13 ns min SYNC falling edge to SCLK falling edge setup time

t5 10 13 ns min

24th SCLK falling edge to SYNC rising edge

t6 40 ns min Minimum SYNC high time

t7 5 ns min Data setup time

t8 0 ns min Data hold time

t9 20 ns min SYNC rising edge to LDAC falling edge

t10 20 ns min LDAC pulse width low

t11 5 ns max LDAC falling edge to DAC output response time

t12 10 µs max DAC output settling time

t13 20 ns min CLR pulse width low

t14 3 µs max CLR pulse activation time

t1511,12 20 ns max SCLK rising edge to SDO valid

t1612 8 ns min

SYNC rising edge to SCLK rising edge

t1712 TBD ns min

SYNC rising edge to DAC output response time (LDAC = 0)

7 Guaranteed by design and characterization. Not production tested.

8 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

9 See Figure 2, Figure 3, and Figure 4.

10 Stand-alone mode only.

11 Measured with the load circuit of Figure 5.

12 Daisy-chain mode only.

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 8 of 36

05303-002

DB23

SCLK

SYNC

SDIN

LDAC

OUT

LDAC = 0

OUT

CLR

OUT

12 24

DB0

Figure 2. Serial Interface Timing Diagram

05303-003

LDAC

SDO

SDIN

SYNC

SCLK 24 48

DB23 DB0 DB23 DB0

DB23

INPUT WORD FOR DAC NUNDEFINED

INPUT WORD FOR DAC N+1INPUT WORD FOR DAC N

DB0

Figure 3. Daisy Chain Timing Diagram

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 9 of 36

05303-004

SDO

SDIN

SYNC

SCLK 24 48

DB23 DB0 DB23 DB0

DB23

SELECTED REGISTER DATA

CLOCKED OUT

UNDEFINED

NOP CONDITIONINPUT WORD SPECIFIES

DB0

Figure 4. Readback Timing Diagram

05303-005

200µAI

VOH (MIN) OR

VOL (MAX)

TO OUTPUT

PIN CL

50pF

Figure 5. Load Circuit for SDO Timing Diagram

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 10 of 36

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted. Transient currents of up to

100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD to AGND, DGND −0.3 V to +17 V

AVSS to AGND, DGND +0.3 V to −17 V

DVCC to DGND −0.3 V to +7 V

Digital Inputs to DGND −0.3 V to DVCC + 0.3 V

Digital Outputs to DGND −0.3 V to DVCC + 0.3 V

REF IN to AGND, PWRGND −0.3 V to AVDD + 0.3V

REF OUT to AGND AVSS to AVDD

TEMPOUT AVSS to AVDD

VOUTA,B,C,D to AGND AVSS to AVDD

AGND to DGND −0.3 V to +0.3 V

Operating Temperature Range

Industrial −40°C to +85°C

Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ max) 150°C

32-Lead TQFP Package,

θJA Thermal Impedance

65°C/W

θJC Thermal Impedance 12°C/W

Reflow Soldering

Peak Temperature 220°C

Time at Peak Temperature 10 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 11 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SYNC

SCLK

SDIN

SDO

CLR

LDAC

AGNDA

VOUTA

VOUTB

AGNDB

AGNDC

VOUTC

VOUTD

AGNDD

RSTOUT

RSTIN

DGND

PGND

ISCC

BIN/2sCOMP

TEMP

REFGND

REFOUT

REFCD

REFAB

PIN 1

910 11 12 13 14 15 16

32 31 30 29 28 27 26 25

AD5744/AD5764

TOP VIEW

(Not to Scale)

05303-006

Figure 6. 32-Lead TQFP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

1 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

transferred in on the falling edge of SCLK.

2 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock

speeds up to 30 MHz.

3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.

4 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.

5 CLR2 Negative edge triggered Input. Asserting this pin sets the DAC registers to 0x0000.

6 LDAC Load DAC. Logic input. This is used to update the DAC registers and consequently the analog output. When tied

permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during

the write cycle, the DAC input register is updated but the output is held off until the falling edge of LDAC. In this

mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.

7, 8 D0, D1 D0 and D1 form a digital I/O port. The user can configure these pins as inputs or outputs that are configurable

and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to

DVCC.

9 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it

may be used to control other system components.

10 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input

resets the DAC output to 0 V. In normal operation, RSTIN should be tied to Logic 1.

11 DGND Digital GND Pin.

12 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as outputs, D0 and D1 are referenced

to DVCC.

13, 31 AVDD Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.

14 PGND Ground Reference Point for Analog Circuitry.

15, 30 AVSS Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.

16 ISCC This pin us used in association with an external resistor to AGND to program the short-circuit current of the

output amplifiers.

17 AGNDD Ground Reference Pin for DAC D Output amplifier.

18 VOUTD Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output

amplifier is capable of directly driving a 10 kΩ, 200 pF load.

19 VOUTC Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of ±10 V. The output

amplifier is capable of directly driving a 10 kΩ, 200 pF load.

2 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 12 of 36

Pin No. Mnemonic Function

20 AGNDC Ground Reference Pin for DAC C Output Amplifier.

21 AGNDB Ground Reference pin for DAC B Output Amplifier.

22 VOUTB Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output

amplifier is capable of directly driving a 10 kΩ, 200 pF load.

23 VOUTA Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output

amplifier is capable of directly driving a 10 kΩ, 200 pF load.

24 AGNDA Ground Reference Pin for DAC A Output Amplifier.

25 REFAB External Reference Voltage Input for Channels A and B. Reference input range is 1 V to 5 V; programs the full-

scale output voltage. REFIN = 5 V for specified performance.

26 REFCD External Reference Voltage Input for Channels C and D. Reference input range is 1 V to 5 V; programs the full-

scale output voltage. REFIN = 5 V for specified performance.

27 REFOUT Reference Output. This is the buffered reference output from the internal voltage reference. The internal

reference is 5 V ± 1 mV, with a reference tempco of 10 ppm/°C.

28 REFGND Reference Ground Return for the Reference Generator and Buffers.

29 TEMP This pin provides an output voltage proportional to temperature. The output voltage is 1.5 V typical at 25°C;

variation with temperature is 5 mV/°C.

32 BIN/2sCOMP3 Determines the DAC Coding. This pin should be hardwired to either DVCC or 0V. When hardwired to DVCC, input

coding is offset binary. When hardwired to 0V, input coding is twos complement. (See Table 6 and Table 7)

3 Internal pull-down device on this logic input. Therefore, it can be left floating and defaults to a logic low condition.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 13 of 36

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or Integral Nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer

function. A typical INL vs. code plot can be seen in Figure ?

Differential Nonlinearity

Differential Nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of ±1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. A typical DNL vs. code plot can be seen

in Figure ?

Monotonicity

A DAC is monotonic, if the output either increases or remains

constant for increasing digital input code. The

AD5744/AD5764 is monotonic over its full operating

temperature range

Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the

ideal half-scale output of 0 V when the DAC register is loaded

with 0x8000 (Offset Binary coding) or 0x0000 (2sComplement

coding)

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code is loaded to the DAC register. Ideally the output voltage

should be full scale value – 1 LSB. Full-scale error is expressed

in percentage of full-scale range.

Negative Full-Scale Error / Zero Scale Error

Negative full-scale error is the error in the DAC output voltage

when 0x0000 (Offset Binary coding) or 0x8000 (2sComplement

coding) is loaded to the DAC register. Ideally the output voltage

should be negative full scale value – 1 LSB.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for

the output to settle to a specified level for a full-scale input

change.

Slew Rate

The slew rate of a device is a limitation in the rate of change of

the output voltage. The output slewing speed of a voltage-

output D/A converter is usually limited by the slew rate of the

amplifier used at its output. Slew rate is measured from 10% to

90% of the output signal and is given in V/µs.

Gain Error

This is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range. A plot of

gain error vs. temperature can be seen in Figure ?

Tota l Una dju ste d Er r or

Total Unadjusted Error (TUE) is a measure of the output error

taking all the various errors into account. A typical TUE vs.

code plot can be seen in Figure ?.

Zero-Code Error Drift

This is a measure of the change in zero-code error with a

change in temperature. It is expressed in µV/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV secs

and is measured when the digital input code is changed by

1 LSB at the major carry transition (7FFF Hex to 8000 Hex). See

Figure ?.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC but is measured when the DAC output is not updated. It is

specified in nV secs and measured with a full-scale code change

on the data bus, that is, from all 0s to all 1s and vice versa.

Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is

affected by changes in the power supply voltage.

DC Crosstalk

This is the dc change in the output level of one DAC in response

to a change in the output of another DAC. It is measured with a

full-scale output change on one DAC while monitoring another

DAC. It is expressed in µV.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC

due to a digital code change and subsequent output change of

another DAC. This includes both digital and analog crosstalk. It

is measured by loading one of the DACs with a full-scale code

change (all 0s to all 1s and vice versa) with LDAC low and

monitoring the output of another DAC. The energy of the glitch

is expressed in nV-s.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of

one DAC to a sine wave on the reference input of another DAC.

It is measured in dB

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 14 of 36

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. AD5764 Integral Non Linearity Error vs. Code, VDD/VSS = ±15V

Figure 8. AD5764 Integral Non Linearity Error vs. Code, VDD/VSS = ±12V

Figure 9. AD5744 Integral Non Linearity Error vs. Code, VDD/VSS = ±15V

Figure 10. AD5744 Integral Non Linearity Error vs. Code, VDD/VSS = ±12V

Figure 11. AD5764 Differential Non Linearity Error vs. Code, VDD/VSS = ±15V

Figure 12. AD5764 Differential Non Linearity Error vs. Code, VDD/VSS = ±12V

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 15 of 36

Figure 13. AD5744 Differential Non Linearity Error vs. Code, VDD/VSS = ±15V

Figure 14. AD5744 Differential Non Linearity Error vs. Code, VDD/VSS = ±12V

Figure 15. AD5764 Integral Non Linearity Error vs. Temperature, VDD/VSS =

±15V

Figure 16. AD5764 Integral Non Linearity Error vs. Temperature, VDD/VSS =

±12V

Figure 17. AD5744 Integral Non Linearity Error vs. Temperature, VDD/VSS =

±15V

Figure 18. AD5744 Integral Non Linearity Error vs. Temperature, VDD/VSS =

±12V

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 16 of 36

Figure 19. AD5764 Differential Non Linearity Error vs. Temperature, VDD/VSS =

±15V

Figure 20. AD5764 Differential Non Linearity Error vs. Temperature, VDD/VSS =

±12V

Figure 21. AD5744 Differential Non Linearity Error vs. Temperature, VDD/VSS =

±15V

Figure 22. AD5744 Differential Non Linearity Error vs. Temperature, VDD/VSS =

±12V

Figure 23. AD5764 Integral Non Linearity Error vs. Supply Voltage

Figure 24. AD5744 Integral Non Linearity Error vs. Supply Voltage

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 17 of 36

Figure 25. AD5764 Differential Non Linearity Error vs. Supply Voltage

Figure 26. AD5744 Differential Non Linearity Error vs. Supply Voltage

Figure 27. AD5764 Integral Non Linearity Error vs. Reference Voltage, VDD/VSS

= ±15V

Figure 28. AD5764 Integral Non Linearity Error vs. Reference Voltage, VDD/VSS

= ±12V

Figure 29. AD5744 Integral Non Linearity Error vs. Reference Voltage, VDD/VSS

= ±15V

Figure 30. AD5744 Integral Non Linearity Error vs. Reference Voltage, VDD/VSS

= ±12V

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 18 of 36

Figure 31. AD5764 Differential Non Linearity Error vs. Reference Voltage,

VDD/VSS = ±15V

Figure 32. AD5764 Differential Non Linearity Error vs. Reference Voltage,

VDD/VSS = ±12V

Figure 33. AD5744 Differential Non Linearity Error vs. Reference Voltage,

VDD/VSS = ±15V

Figure 34. AD5744 Differential Non Linearity Error vs. Reference Voltage,

VDD/VSS = ±12V

Figure 35. AD5764 Total Unadjusted Error vs. Reference Voltage, VDD/VSS =

±12V

Figure 36. AD5764 Total Unadjusted Error vs. Reference Voltage, VDD/VSS =

±12V

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 19 of 36

Figure 37. AD5744 Total Unadjusted Error vs. Reference Voltage, VDD/VSS =

±15V

Figure 38. AD5744 Total Unadjusted Error vs. Reference Voltage, VDD/VSS =

±12V

Figure 39. IDD/ISS vs. VDD/VSS

Figure 40. Offset Error vs. Temperature

Figure 41. Bipolar Zero Error vs. Temperature

Figure 42. Gain Error vs. Temperature

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 20 of 36

Figure 43. DICC vs. Logic Input Voltage Increasing and Decreasing

Figure 44. Source and Sink Capability of Output Amplifier with Positive Full

Scale Loaded

Figure 45. Source and Sink Capability of Output Amplifier with Negative Full

Scale Loaded

Figure 46. Full Scale Settling Time

Figure 47. Settling Time vs. Load Capacitance

Figure 48. Major Code Transition Glitch Energy, VDD/VSS = ±15V

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 21 of 36

Figure 49. Major Code Transition Glitch Energy, VDD/VSS = ±12V

Figure 50. Peak-to-Peak Noise (100kHz Bandwidth)

Figure 51. Vout vs. VDD/VSS on Power-up

Figure 52. Short Circuit Current vs. RISCC

Figure 53. TEMPOUT Voltage vs. Temperature

Figure 54.

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 22 of 36

GENERAL DESCRIPTION

The AD5744/AD5764 is a quad 14/16-bit, serial input, bipolar

voltage output DAC. It operates from supply voltages of ±11.4 V

to ±16.5 V and has a buffered output voltage of up to ± 10.5 V.

Data is written to the AD5744/AD5764 in a 24-bit word format,

via a 3-wire serial interface. The device also offers an SDO pin,

which is available for daisy chaining or readback.

The AD5744/AD5764 incorporates a power-on reset circuit,

which ensures that the DAC registers power up loaded with

0x0000. The AD5744/AD5764 also features a digital I/O port

that may be programmed via the serial interface, an analog

temperature sensor, on-chip 10 ppm/°C voltage reference, on-

chip reference buffers and per channel digital gain and offset

registers.

DAC ARCHITECTURE

The DAC architecture of the AD5744/AD5764 consists of a

14/16-bit current-mode segmented R-2R DAC. The simplified

circuit diagram for the DAC section is shown in Figure 13.

The four MSBs of the 14/16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

the 15 matched resistors to either AGND or IOUT. The

remaining 12 bits of the data word drive switches S0 to S11 of

the 12-bit R-2R ladder network.

05303-007

E15

REF

E14 E1

S11

RR R

S10

12-BIT, R-2R LADDER

VOUT

AGND

R/8

4 MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 55. DAC Ladder Structure

REFERENCE BUFFERS

The AD5744/AD5764 can operate with either an external or

internal reference. The reference inputs (REFAB and REFCD)

have an input range up to 5 V. This input voltage is then used to

provide a buffered positive and negative reference for the DAC

cores. The positive reference is given by

+ VREF = 2* VREF

While the negative reference to the DAC cores is given by

−VREF = -2*VREF

These positive and negative reference voltages (along with the

gain register values) define the output ranges of the DACs.

SERIAL INTERFACE

The AD5744/AD5764 is controlled over a versatile 3-wire serial

interface that operates at clock rates of up to 30 MHz and is

compatible with SPI, QSPI, MICROWIRE and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. The input register consists of a read/write

bit, three register select bits, three DAC address bits and 14/16

data bits as shown in Table 8.The timing diagram for this

operation is shown in Figure 2.

Upon power-up the DAC registers are loaded with zero code

(0x0000). The corresponding output voltage depends on the

state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to

DGND then the data coding is 2s Complement and the outputs

power-up to 0V. If the BIN/2sCOMP pin is tied high then the

data coding is Offset binary and the outputs power-up to

Negative Full-scale.

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can only be

used if SYNC is held low for the correct number of clock cycles.

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used and SYNC must be taken high after

the final clock to latch the data. The first falling edge of SYNC

starts the write cycle. Exactly 24 falling clock edges must be

applied to SCLK before SYNC is brought back high again; if

SYNC is brought high before the 24th falling SCLK edge, the

write is aborted. If more than 24 falling SCLK edges are applied

before SYNC is brought high, the input data is corrupted. The

input register addressed is updated on the rising edge of SYNC.

In order for another serial transfer to take place, SYNC must be

brought low again. After the end of the serial data transfer, data

is automatically transferred from the input shift register to the

input register of the addressed DAC.

When the data has been transferred into the input register of

the addressed DAC, all DAC registers and outputs can be

updated by taking LDAC low while SYNC is high.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 23 of 36

68HC11*

MISO

SYNC

SDIN

SCLK

MOSI

SCK

PC7

PC6 LDAC

SDO

SYNC

SCLK

LDAC

SDO

SYNC

SCLK

LDAC

SDO

SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5744/

AD5764*

05303-008

AD5744/

AD5764*

AD5744/

AD5764*

Figure 56. Daisy chaining the AD5744/AD5764

Daisy-Chain Operation

For systems that contain several devices, the SDO pin may be

used to daisy-chain several devices together. This daisy-chain

mode can be useful in system diagnostics and in reducing the

number of serial interface lines. The first falling edge of SYNC

starts the write cycle. The SCLK is continuously applied to the

input shift register when SYNC is low. If more than 24 clock

pulses are applied, the data ripples out of the shift register and

appears on the SDO line. This data is clocked out on the rising

edge of SCLK and is valid on the falling edge. By connecting the

SDO of the first device to the DIN input of the next device in

the chain, a multidevice interface is constructed. Each device in

the system requires 24 clock pulses. Therefore, the total number

of clock cycles must equal 24N, where N is the total number of

AD5744/AD5764s in the chain. When the serial transfer to all

devices is complete, SYNC is taken high. This latches the input

data in each device in the daisy chain and prevents any further

data from being clocked into the input shift register. The serial

clock may be a continuous or a gated clock. A continuous SCLK

source can only be used if SYNC is held low for the correct

number of clock cycles. In gated clock mode, a burst clock

containing the exact number of clock cycles must be used and

SYNC must be taken high after the final clock to latch the data.

Readback Operation

Readback mode is invoked by setting the R/W bit = 1 in the

serial input register write. With R/W = 1, Bits A2–A0, in

association with Bits REG2 , REG1, and REG0, select the

sequence are don’t cares. During the next SPI write, the data

appearing on the SDO output contain the data from the

previously addressed register. For a read of a single register, the

NOP command can be used in clocking out the data from the

selected register on SDO. The readback diagram in Figure 4

shows the readback sequence. For example, to read back the

fine gain register of Channel A on the AD5744/AD5764, the

following sequence should be implemented. First, write

0xA0XXXX to the AD5744/AD5764 input register. This

configures the AD5744/AD5764 for read mode with the fine

gain register of Channel A selected. Note that all the data bits,

DB15 to DB0, are don’t cares. Follow this with a second write, a

NOP condition, 0x00XXXX. During this write, the data from

the fine gain register is clocked out on the SDO line, that is, data

clocked out contains the data from the fine gain register in Bits

DB5 to DB0.

SIMULTANEOUS UPDATING VIA LDAC

After data has been transferred into the input register of the

DACs, there are two ways in which the DAC registers and DAC

outputs can be updated. Depending on the status of both SYNC

and LDAC.

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into

the input shift register. The addressed DAC output is updated

on the rising edge of SYNC.

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked

into the input shift register. All DAC outputs are updated by

taking LDAC low any time after SYNC has been taken high.

The update now occurs on the falling edge of LDAC.

OUT

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

REFIN

SYNC

INPUT

SCLK

05303-009

Figure 57. Simplified Serial Interface of Input Loading Circuitry for One DAC

Channel

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 24 of 36

TRANSFER FUNCTION

Table 6 and Table 7 Show the ideal input code to output voltage

relationship for the AD5744/AD5764 for both Offset binary and

twos complement data coding.

Table 6. Ideal Output Voltage to Input Code Relationship for

the AD5764

Digital Input Analog Output

Offset Binary Data Coding

MSB LSB VOUT

1111 1111 1111 1111 +2 VREF × (32767/32768)

1000 0000 0000 0001 +2 VREF × (1/32768)

1000 0000 0000 0000 0 V

0111 1111 1111 1111 −2 VREF × (1/32768)

0000 0000 0000 0000 −2 VREF × (32767/32768)

Twos Complement Data Coding

MSB LSB VOUT

0111 1111 1111 1111 +2 VREF × (32767/32768)

0000 0000 0000 0001 +2 VREF × (1/32768)

0000 0000 0000 0000 0 V

1111 1111 1111 1111 −2 VREF × (1/32768)

1000 0000 0000 0000 −2 VREF × (32767/32768)

Table 7. Ideal Output Voltage to Input Code Relationship for

the AD5744

Digital Input Analog Output

Offset Binary Data Coding

MSB LSB VOUT

11 1111 1111 1111 +2 VREF × (8192/8192)

10 0000 0000 0001 +2 VREF × (1/8192)

10 0000 0000 0000 0 V

01 1111 1111 1111 −2 VREF × (1/8192)

00 0000 0000 0000 −2 VREF x (8192/8192)

Twos Complement Data Coding

MSB LSB VOUT

01 1111 1111 1111 +2 VREF × (8192/8192)

00 0000 0000 0001 +2 VREF × (1/8192)

00 0000 0000 0000 0 V

11 1111 1111 1111 −2 VREF × (1/8192)

10 0000 0000 0000 −2 VREF × (8192/8192)

The output voltage expression for the AD5764 is given by:

⎥

⎦

⎤

⎢

⎣

⎡

×+×−= 65536

42 D

VVV REFINREFINOUT

The output voltage expression for the AD5744 is given by:

⎥

⎦

⎤

⎢

⎣

⎡

×+×−= 16384

42 D

VVV REFINREFINOUT

where:

D is the decimal equivalent of the code loaded to the DAC.

VREFIN is the reference voltage applied at the REFIN pin.

ASYNCHRONOUS CLEAR (CLR)

CLR is a negative edge triggered clear that allows the outputs to

be cleared to either 0 V (twos complement coding) or negative

full scale (offset binary coding). It is necessary to maintain CLR

low for a minimum amount of time (refer to Figure 3) for the

operation to complete. When the CLR signal is returned high,

the output remains at the cleared value until a new value is

programmed. If at power-on CLR is at 0V, all DAC outputs will

be updated with the clear value. A clear can also be initiated

through software by writing the command 0x04XXXX to the

AD5744/AD5764.

Table 8. AD5744/AD5764 Input Register Format

MSB LSB

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R/W 0 REG2 REG1 REG0 A2 A1 A0 DATA

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 25 of 36

Table 9. Input Register Bit Functions

R/W Indicates a read from or a write to the addressed register.

REG2, REG1, REG0 Used in association with the address bits to determine if a read or write operation is to the data register, offset

REG2 REG1 REG0 Function

0 0 0 Function Register

0 1 0 Data Register

0 1 1 Coarse Gain Register

1 0 0 Fine Gain Register

1 0 1 Offset Register

A2, A1, A0 These bits are used to decode the DAC channels

A2 A1 A0 Channel Address

0 0 0 DAC A

0 0 1 DAC B

0 1 0 DAC C

0 1 1 DAC D

1 0 0 ALL DACs

D15 – D0 Data Bits

FUNCTION REGISTER

The Function Register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine

the function addressed. The Functions available through the function register are shown in Table 10 and Table 11.

Table 10. Function Register Options

REG2 REG1 REG0 A2 A1 A0 DB15 .. DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 NOP, Data = Don’t Care

0 0 0 0 0 1 Don’t Care

Local-

Ground-

Offset Adjust

Direction

D1 Value D0

Direction

Value

SDO

Disable

0 0 0 1 0 0 CLR, Data = Don’t Care

0 0 0 1 0 1 LOAD, Data = Don’t Care

Table 11. Explanation of Function Register Options

Option Description

NOP No operation instruction used in readback operations.

Local-Ground-

Offset Adjust

Set by the user to enable local-ground-offset adjust function.

Cleared by the user to disable local-ground-offset adjust function (default).

D0 / D1

Direction

Set by the user to enable D0/D1 as outputs.

Cleared by the user to enable D0/D1 as inputs (default). Have weak internal pull-ups.

D0 / D1 Value I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when

configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When

enabled as inputs, these bits are don’t cares during a write operation.

SDO Disable Set by the user to disable the SDO output.

Cleared by the user to enable the SDO output (default).

CLR Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary

mode.

LOAD Addressing this function updates the DAC registers and consequently the analog outputs.

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 26 of 36

DATA REGISTER

The Data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The data bits are in positions DB15 to DB0 for the AD5764 as shown in Table 12 and DB15 to

DB2 for the AD5744 as shown in Table 13.

Table 12. Programming the AD5764 Data Register

REG2 REG1 REG0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 DAC Address 16 Bit DAC Data

Table 13. Programming the AD5744 Data Register

REG2 REG1 REG0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 DAC Address 14 Bit DAC Data X X

COARSE GAIN REGISTER

The Coarse Gain Register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC Channel the

Data transfer is to take place (Refer to Table 9). The Coarse Gain Register is a 2-bit register and allows the user to select the output range

of each DAC as shown in Table 15.

Table 14. Programming the AD5744/AD5764 Coarse Gain Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB2 DB1 DB0

0 1 1 DAC Address Don’t Care CG1 CG0

Table 15. Output Range Selection

Output Range CG1 CG0

± 10 V 0 0

± 10.25 V 0 1

± 10.5 V 1 0

FINE GAIN REGISTER

The Fine Gain Register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The AD5764 Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each

DAC channel by -32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 16 and Table 17. The AD5744 Fine Gain Register is a 4-bit register

and allows the user to adjust the gain of each DAC channel by -8 LSBs to +7 LSBs as shown in Table 17 and Table 19.

Table 16. Programming AD5764 Fine Gain Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 0 DAC Address Don’t Care FG5 FG4 FG3 FG2 FG1 FG0

Table 17. AD5764 Fine Gain Register Options

16 Bit Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0

+31 LSBs 0 1 1 1 1 1

+30 LSBs 0 1 1 1 1 0

- - - - - -

No Adjustment 0 0 0 0 0 0

- - - - - -

-31 LSBs 1 0 0 0 0 1

-32 LSBs 1 0 0 0 0 0

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 27 of 36

Table 18. Programming AD5744 Fine Gain Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 0 DAC Address Don’t Care FG3 FG2 FG1 FG0 X X

Table 19. AD5744 Fine Gain Register Options

16 Bit Gain Adjustment FG3 FG2 FG1 FG0

+7 LSBs 0 1 1 1

+6 LSBs 0 1 1 0

- - - -

No Adjustment 0 0 0 0

- - - -

-7 LSBs 1 0 0 1

-8 LSBs 1 0 0 0

OFFSET REGISTER

The Offset Register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The AD5764 Offset Register is an 8-bit register and allows the user to adjust the offset of each

channel by – 16 LSBs to + 15.875 LSBs in steps of 1/8 LSB as shown in Table 20 and Table 21. The AD5744 Offset Register is a 6-bit

register and allows the user to adjust the offset of each channel by -4 LSBs to +3.875 LSBs as shown in Table 22 and Table 23.

Table 20. Programming the AD5764 Offset Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 1 DAC Address Don’t Care OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0

Table 21. AD5764 Offset Register options

Offset Adjustment OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0

+15.875 LSBs 0 1 1 1 1 1 1 1

+15.75 LSBs 0 1 1 1 1 1 1 0

- - - - - - - -

No Adjustment 0 0 0 0 0 0 0 0

- - - - - - - -

-15.875 LSBs 1 0 0 0 0 0 0 1

-16 LSBs 1 0 0 0 0 0 0 0

Table 22. Programming the AD5744 Offset Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 1 DAC Address Don’t Care OF5 OF4 OF3 OF2 OF1 OF0 X X

Table 23. AD5744 Offset Register options

Offset Adjustment OF5 OF4 OF3 OF2 OF1 OF0

+3.875 LSBs 0 1 1 1 1 1

+3.75 LSBs 0 1 1 1 1 0

- - - - - -

No Adjustment 0 0 0 0 0 0

- - - - - -

-3.875 LSBs 1 0 0 0 0 1

-4 LSBs 1 0 0 0 0 0

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 28 of 36

AD5744/AD5764 FEATURES

ANALOG OUTPUT CONTROL

In many industrial process control applications, it is vital that

the output voltage be controlled during power up and during

brownout conditions. When the supply voltages are changing,

the VOUT pin is clamped to 0 V via a low impedance path. To

prevent the output amp being shorted to 0 V during this time,

transmission gate G1 is also opened. These conditions are

maintained until the power supplies stabilize and a valid word is

written to the DAC register. At this time, G2 opens and G1

closes. Both transmission gates are also externally controllable

via the Reset In (RSTIN) control input. For instance, if RSTIN is

driven from a battery supervisor chip, the RSTIN input is

driven low to open G1 and close G2 on power-off or during a

brownout. Conversely, the on-chip voltage detector output

(RSTOUT) is also available to the user to control other parts of

the system. The basic transmission gate functionality is shown

in Figure 58.

05303-010

RSTOUT RSTIN

VOUTA

AGNDA

VOLTAGE

MONITOR

AND

CONTROL

Figure 58. Analog Output Control Circuitry

DIGITAL OFFSET AND GAIN CONTROL

The AD5744/AD5764 incorporates a digital offset adjust

function with a ±16 LSB adjust range and 0.125 LSB resolution.

The gain register allows the user to adjust the

AD5744/AD5764’s full-scale output range. The full-scale output

can be programmed to achieve full-scale ranges of ±10 V,

±10.25 V, and ±10.5 V. A fine gain trim is also available,

allowing a trim range of ±16 LSB in 1 LSB steps.

PROGRAMMABLE SHORT-CIRCUIT PROTECTION

The short-circuit current of the output amplifiers can be pro-

grammed by inserting an external resistor between the ISCC

pin and PGND. The programmable range for the current is

500 µA to 10 mA, corresponding to a resistor range of 120 kΩ

to 6 kΩ .

The resistor value is calculated as follows;

Isc

R60

If the ISCC pin is left unconnected the short circuit current

limit defaults to 5 mA. It should be noted that limiting the short

circuit current to a small value can affect the slew rate of the

output when driving into a capacitive load, therefore the value

of short-circuit current programmed should take into account

the size of the capacitive load being driven.

DIGITAL I/O PORT

The AD5744/AD5764 contains a 2-bit digital I/O port (D1 and

D0), these bits can be configured as inputs or outputs

independently, and can be driven or have their values read back

via the serial interface. The I/O port signals are referenced to

DVCC and DGND. When configured as outputs, they can be

used as control signals to multiplexers or can be used to control

calibration circuitry elsewhere in the system. When configured

as inputs, the logic signals from limit switches, for example can

be applied to D0 and D1 and can be read back via the digital

interface.

TEMPERATURE SENSOR

The on-chip temperature sensor provides a voltage output that

is linearly proportional to the Centigrade temperature scale.

The typical accuracy of the temperature sensor is ±1°C at +25°C

and ±5°C over the −40°C to +105°C range. Its nominal output

voltage is 1.5V at +25°C, varying at 5 mV/°C, giving a typical

output range of 1.175V to 1.9 V over the full temperature range.

Its low output impedance, low self heating, and linear output

simplify interfacing to temperature control circuitry and A/D

converters.

LOCAL GROUND OFFSET ADJUST

The AD5744/AD5764 incorporates a Local Ground Offset

Adjust feature which when enabled in the Function Register

adjusts the DAC outputs for voltage differences between The

individual DAC ground pins and the REFGND pin ensuring

that the DAC output voltages are always with respect to the

local DAC ground pin. For instance if pin AGNDA is at +5 mV

with respect to the REFGND pin and VOUTA is measured with

respect to AGNDA then a +5mV error results, enabling the

Local Ground Offset Adjust feature offsets VOUTA by +5 mV,

eliminating the error.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 29 of 36

APPLICATIONS INFORMATION

TYPICAL OPERATING CIRCUIT

Figure 59 shows the typical operating circuit for the

AD5744/AD5764. The only external components needed for

this precision 14/16-bit DAC are decoupling capacitors on the

supply pins, R-C connection from REFOUT to REFAB and

REFCD and a short circuit current setting resistor. Because the

device incorporates a voltage reference, and reference buffers, it

eliminates the need for an external bipolar reference and

associated buffers. This leads to an overall saving in both cost

and board space.

In the circuit below, VDD and VSS are both connected to ±15 V,

but VDD and VSS can operate with supplies from ±11.4 V to

±16.5 V. In Figure 11, AGNDA is connected to REFGND.

910 11 12 13 14 15 16

32 31 30 29 28 27 26 25

AD5744/

AD5764

SYNC

SCLK

SDIN

SDO

LDAC

CLR

VOUTA

VOUTB

AGNDB

VOUTD

VOUTC

AGNDC

AGNDA

AGNDD

RSTOUT

RSTIN

DGND

DVCC

AVDD

PGND

AVSS

ISCC

BIN/2sCOMP

AVDD

AVSS

TEMP

REFGND

REFOUT

REFCD

REFAB

SYNC

SCLK

SDIN

SDO

LDAC

RSTOUT

RSTIN

BIN/2sCOMP

+5V

+5V +15V –15V

+15V –15V

VOUTA

VOUTB

VOUTC

VOUTD

6kΩ

100nF

10µF

100nF

10µF

3kΩ

TEMP

10µF

05303-011

Figure 59. Typical Operating Circuit

Precision Voltage Reference Selection

To achieve the optimum performance from the

AD5744/AD5764 over it’s full operating temperature range an

external voltage reference must be used. Thought should be

given to the selection of a precision voltage reference. The

AD5744/AD5764 has two reference inputs, REFAB and REFCD.

The voltages applied to the reference inputs are used to provide

a buffered positive and negative reference for the DAC cores.

Therefore, any error in the voltage reference is reflected in the

outputs of the device.

There are four possible sources of error to consider when

choosing a voltage reference for high accuracy applications:

initial accuracy, temperature coefficient of the output voltage,

long term drift and output voltage noise.

Initial accuracy error on the output voltage of an external refer-

ence could lead to a full-scale error in the DAC. Therefore, to

minimize these errors, a reference with low initial accuracy

error specification is preferred. Also, choosing a reference with

an output trim adjustment, such as the ADR425, allows a

system designer to trim system errors out by setting the refer-

ence voltage to a voltage other than the nominal. The trim ad-

justment can also be used at temperature to trim out any error.

Long term drift is a measure of how much the reference output

voltage drifts over time. A reference with a tight long-term drift

specification ensures that the overall solution remains relatively

stable over its entire lifetime.

The temperature coefficient of a reference’s output voltage

affects INL, DNL and TUE. A reference with a tight

temperature coefficient specification should be chosen to

reduce the dependence of the DAC output voltage on ambient

conditions.

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be considered.

Choosing a reference with as low an output noise voltage as

practical for the system resolution required is important.

Precision voltage references such as the ADR435 (XFET design)

produce low output noise in the 0.1 Hx to 10 Hz region.

However, as the circuit bandwidth increases, filtering the output

of the reference may be required to minimize the output noise.

Table 24. Some Precision References Recommended for Use with the AD5744/AD5764

Part No. Initial Accuracy(mV max) Long-Term Drift (ppm typ) Temp Drift (ppm/°C max) 0.1 Hz to 10 Hz Noise (µV p-p typ)

ADR435 ± 6 30 3 3.4

ADR425 ± 6 50 3 3.4

ADR02 ± 5 50 3 15

ADR395 ± 6 50 25 5

AD586 ± 2.5 15 10 4

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 30 of 36

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consider-

ation of the power supply and ground return layout helps to

ensure the rated performance. The printed circuit board on

which the AD5744/AD5764 is mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD5744/AD5764 is in a

system where multiple devices require an AGND-to-DGND

connection, the connection should be made at one point only.

The star ground point should be established as close as possible

to the device. The AD5744/AD5764 should have ample supply

bypassing of 10 µF in parallel with 0.1 µF on each supply

located as close to the package as possible, ideally right up

against the device. The 10 µF capacitors are the tantalum bead

type. The 0.1 µF capacitor should have low effective series

resistance (ESR) and low effective series inductance (ESI) such

as the common ceramic types, which provide a low impedance

path to ground at high frequencies to handle transient currents

due to internal logic switching.

The power supply lines of the AD5744/AD5764 should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with digital

ground to avoid radiating noise to other parts of the board, and

should never be run near the reference inputs. A ground line

routed between the SDIN and SCLK lines helps reduce cross-

talk between them (not required on a multilayer board, which

has a separate ground plane, but separating the lines helps). It is

essential to minimize noise on the reference inputs, because it

couples through to the DAC output. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board

should run at right angles to each other. This reduces the effects

of feed through the board. A microstrip technique is by far the

best, but not always possible with a double-sided board. In this

technique, the component side of the board is dedicated to

ground plane, while signal traces are placed on the solder side.

ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled. Opto-isolators can provide voltage isolation in

excess of 3 kV. The serial loading structure of the AD5744/

AD5764 makes it ideal for opto-isolated interfaces, because the

number of interface lines is kept to a minimum. Figure 60

shows a 4-channel isolated interface to the AD5744/AD5764.

To reduce the number of opto-isolators, if the simultaneous

updating of the DAC is not required, the LDAC pin may be tied

permanently low. The DAC can then be updated on the rising

edge of SYNC.

TO SDIN

TO SCLK

TO SYNC

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

µCONTROLLER

OPTO-COUPLER

TO LDAC

CONTROL OUT

05303-012

Figure 60. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5744/AD5764 is via a

serial bus that uses standard protocol compatible with

microcontrollers and DSP processors. The communications

channel is a 3-wire (minimum) interface consisting of a clock

signal, a data signal, and a synchronization signal. The

AD5744/AD5764 requires a 24-bit data word with data valid on

the falling edge of SCLK.

For all the interfaces, the DAC output update may be done

automatically when all the data is clocked in, or it may be done

under the control of LDAC. The contents of the DAC register

may be read using the readback function.

AD5744/AD5764 to MC68HC11 Interface

Figure 61 shows an example of a serial interface between the

AD5744/AD5764 and the MC68HC11 microcontroller. The

serial peripheral interface (SPI) on the MC68HC11 is config-

ured for master mode (MSTR = 1), clock polarity bit (CPOL =

0), and the clock phase bit (CPHA = 1). The SPI is configured

by writing to the SPI control register (SPCR) — see the

68HC11User Manual. SCK of the 68HC11 drives the SCLK of

theAD5744/AD5764, the MOSI output drives the serial data

line (DIN) of the AD5744/AD5764, and the MISO input is

driven from SDO. The SYNC is driven from one of the port

lines, in this case PC7.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 31 of 36

When data is being transmitted to the AD5744/AD5764, the

SYNC line (PC7) is taken low and data is transmitted MSB first.

Data appearing on the MOSI output is valid on the falling edge

of SCK. Eight falling clock edges occur in the transmit cycle, so,

in order to load the required 24-bit word, PC7 is not brought

high until the third 8-bit word has been transferred to the

DACs input shift register.

AD5744/

AD5764*

SCLK

SDIN

SYNC

MOSI

SCLK

PC7

MC68HC11*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO

MISO

05303-013

Figure 61. AD5744/AD5764 to MC68HC11 Interface

LDAC is controlled by the PC6 port output. The DAC can be

updated after each 3-byte transfer by bringing LDAC low. This

example does not show other serial lines for the DAC. If CLR

were used, it could be controlled by port output PC5, for

example.

AD5744/AD5764 to 8051 Interface

The AD5744/AD5764 requires a clock synchronized to the

serial data. For this reason, the 8051 must be operated in Mode

0. In this mode, serial data enters and exits through RxD, and a

shift clock is output on TxD.

P3.3 and P3.4 are bit programmable pins on the serial port and

are used to drive SYNC and LDAC, respectively. The 8051

provides the LSB of its SBUF register as the first bit in the data

stream. The user must ensure that the data in the SBUF register

is arranged correctly, because the DAC expects MSB first. When

data is to be transmitted to the DAC, P3.3 is taken low. Data on

RxD is clocked out of the microcontroller on the rising edge of

TxD and is valid on the falling edge. As a result, no glue logic is

required between this DAC and the microcontroller interface.

The 8051 transmits data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. Because the DAC

expects a 24-bit word, SYNC (P3.3) must be left low after the

first eight bits are transferred. After the third byte has been

transferred, the P3.3 line is taken high. The DAC may be

updated using LDAC via P3.4 of the 8051.

AD5744/AD5764 to ADSP2101/ADSP2103 Interface

An interface between the AD5744/AD5764 and the ADSP2101/

ADSP2103 is shown in Figure 62. The ADSP2101/

ADSP2103should be set up to operate in the SPORT transmit

alternate framing mode. The ADSP2101/ADSP2103 are

programmed through the SPORT control register and should be

configured as follows: internal clock operation, active low

framing, and 24-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled. As the data is clocked out of

the DSP on the rising edge of SCLK, no glue logic is required to

interface the DSP to the DAC. In the interface shown, the DAC

output is updated using the LDAC pin via the DSP.

Alternatively, the LDAC input could be tied permanently low,

and then the update takes place automatically when TFS is

taken high.

SCLK

SDIN

SYNC

SCLK

RFS

ADSP2101/

ADSP2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO

TFS

LDAC

AD5744/

AD5764*

05303-014

Figure 62. AD5744/AD5764 to ADSP2101/ADSP2103 Interface

AD5744/AD5764 to PIC16C6x/7x Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit set to 0. This is done

by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In

this example, I/O port RA1 is being used to pulse SYNC and

enable the serial port of the AD5744/AD5764. This

microcontroller transfers only eight bits of data during each

serial transfer operation; therefore, three consecutive write

operations are needed. Figure 63 shows the connection

diagram.

SCLK

SDIN

SYNC

SDO/RC5

SCLK/RC3

RA1

PIC16C6x/7x*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO

SDI/RC4

AD5744/

AD5764*

05303-015

Figure 63. AD5744/AD5764 to PIC16C6x/7x Interface

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 32 of 36

EVALUATION BOARD

The AD5744/AD5764 comes with a full evaluation board to aid

designers in evaluating the high performance of the part with a

minimum of effort. All that is required with the evaluation

board is a power supply, and a PC. The AD5744/AD5764

evaluation kit includes a populated, tested AD5744/AD5764

printed circuit board. The evaluation board interfaces to the

USB interface of the PC. Software is available with the

evaluation board, which allows the user to easily program the

AD5744/AD5764. The software runs on any PC that has

Microsoft Windows® 2000/XP installed.

An application note is available that gives full details on

operating the evaluation board.

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 33 of 36

OUTLINE DIMENSIONS

TOP VIEW

(PINS DOWN)

24 17

0.45

0.37

0.30

0.80

BSC

7.00

9.00 SQ

1.05

1.00

0.95 SEATING

PLANE

1.20

MAX

0.15

0.05

7°

0°

0.75

0.60

0.45

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 64. 32-Lead Thin Quad Flatpack [TQFP]

(SU-32)

Dimensions shown in millimeters

ORDERING GUIDE

Model Function INL Package Description Package Option

AD5764CSU Quad 16-bit DAC ± 1 LSB max 32-lead TQFP SU-32

AD5764BSU Quad 16-bit DAC ± 2 LSB max 32-lead TQFP SU-32

AD5764ASU Quad 16-bit DAC ± 4 LSB max 32-lead TQFP SU-32

AD5744CSU Quad 14-bit DAC ± 1 LSB max 32-lead TQFP SU-32

AD5744BSU Quad 14-bit DAC ± 2 LSB max 32-lead TQFP SU-32

AD5744ASU Quad 14-bit DAC ± 4 LSB max 32-lead TQFP SU-32

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 34 of 36

NOTES

Preliminary Technical Data AD5744/AD5764

Rev. PrD | Page 35 of 36

NOTES

AD5744/AD5764 Preliminary Technical Data

Rev. PrD | Page 36 of 36

NOTES

registered trademarks are the property of their respective owners.

PR05303–0–4/05(PrD)