UPD800232F1-014-HN2-A - Renesas Electronics

Document No. A17813EE2V0DS00

Data Published: November 2009

ERTEC 400

Enhanced Real-Time Ethernet Controller

with 3 2-bit RIS C CPU C ore

The information in this document is subject to change without no tice. Before using this document, please confirm that

this is the latest version.

Not all products and/or types are available in every countr y. Please check with an NEC Electronics sales representative

for ava ilabilit y a nd a dditional infor m a tion.

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD800232

DESCRIPTION

ERTEC 400 is a powerful communication block for development of Ethernet-based automation prod-

ucts. ERTEC 400 contains a 32-bit RISC processor, an external memory interface with SDRAM and

SRAM controller, a PCI/LBU interface, a 4-channel real-time Ethernet interface, synchronous and

asynchronous serial ports, and general purpose I/Os. Its robust construction, specific automation func-

tions, and openness to the IT world are distinguishing features. The ERTEC 400 is housed in a 304-pin

plastic FBGA package (19 mm × 19 mm).

Detailed functions are described in the following user’s manual. Be sure to read this manual

when you design your systems.

Preliminary User’s Manual ERTEC 400 : A17812EE2V0UM00

•ARM946E- S cor e with max. 150 MHz

- 8 kBytes of instruction cach e

- 4 kBytes of d ata cache

- 4 kBytes of D-TCM

- Memory protection unit

- On-ch ip debug and trace functionality via

JTAG interface

- ETM9 embedded trace macrocell

- Interrupt controller for 16 IRQs and 8 FIQs

•Internal Multilayer AHB bus running at 50 MHz

•8 kBytes of internal SRAM accessible by

ARM946 core, IRT and PCI/LBU interface

•External memory interface (EMIF) supports up

to 256 MBytes of SDRAM and up to 64 MBytes

for static memories and I/O with 4 chip selects

•Integrated PLL to generate internal clocks for

ARM946E-S, AHB, AP B and IRT switch

•Predefined Boot ROM content supporting dif-

ferent download sourc es

•32-bit/66 MHz PCI Rev. 2.2 interface

- supports power management V1.1

- 3.3 V interface level (5 V tolerant)

- master/target capability

- host bridge functionality

•Local bus unit (LBU) with 16-bit data bus to

connect external host with access to internal

ERTEC 400 resource s

•IRT switch block with 4 Ethernet ports (10/100

Mbps) supporting RT and IRT traffic

- autonegotiation, broadcast filter

- 192 kBytes internal communication SRAM

•Two UARTs (16550 like) and one SPI interface

•Two 32-bit timers with prescaler, one 32-bit F-

timer and two watchdog timers

•Max. 32 GPIOs, partly usable as interrupts

•1.5 V (logic) and 3.3 V (I/O) power supply

•Temperature range: TA = -40 to 85°C

•Compact 304-pin plastic FBGA package

ORDERING INFORMATION

Remark: Products with -A at the end of the part number are lead-free products.

Device Par t Number Package

ERTEC 400 µPD800232F1-014-HN2-A P-FBGA304, 19 × 19 mm

FEATURES

2Data Sheet A17 813 EE 2V0 DS00

µPD800232

INTERNAL BLOCK DIAGRAM

PCI

Bridge

(32 bit, 66 MHz)

Master/Target-

capable

ARM

Interrupt

Controller

ARM946E-S

with

I-Cache (8 kBytes)

D-Cache (4 kBytes)

D-TCM (4 kBytes)

50/100/150 MHz

AHB/APB

Bridge

GPIO

Slave

AHB-

Wrapper

Master

APB

(32 bit, 50 MHz)

PCI/Local Bus

External Memory Interface

2 x UART

SPI

Interface

2 x Timer,

Watchdog,

F-Timer

12.5 MHz

SC-Bus (32 bit, 50 MHz)MC-Bus (32 bit, 50 MHz)

IRT

Switch

Macro

Switch Control

Communi-

cation

SRAM

(192 kBytes)

Ethernet

Channel

(Port 0)

Ethernet

Channel

(Port 1)

Ethernet

Channel

(Port 2)

Ethernet

Channel

(Port 3)

Slave

JTAG / Debug

4 x R

2 x MI

AHB-

Wrapper

Slave

Master

Boot

ROM

(8 kBytes)

BS-

TA P

Multilayer AHB

(32 bit, 50 MHz)

Local

Bus Unit

(LBU)

(16 bit)

Master Slave

MUX/Arb.

Input

stage

Input

stage

Input

stage

MUX/Arb. MUX/Arb. Decode

SMI

Reset

System

Control

Clock

Unit

REF_CLK

Trace

Port

MUX/Arb.

74 7

Slave

MUX/Arb.

Slave

Master

100 MHz

50 MHz

ARM9

Clock

Ports

(UAR

SPI,

WDT)

Peripheral Ports

Master

ETM

Slave

SRAM

(8 kBytes)

External

Memory

Interface

(EMIF)

MC_

Data Sheet A17813EE2V0DS00

µPD800232

PIN IDENTIFICATION

(1/2)

A(23:0) : Address bus PAR : PCI parity

D(31:0) : Data b u s SERR_N : PCI system error

WR_N : Write strobe PERR_N : PCI parity error

RD_N : Read strobe ST OP_ N : PCI stop

CLK_SDRAM : Cloc k to SDRAM DEVSEL_N : PCI dev ice select

BE(3:0)_DQM(3:0)_N : Byte enable TRDY_N : PCI target ready

CS_SDRAM_N : Chip select to SDRAM IRDY_N : PCI initiator ready

RAS_SDRAM_N : Row address strobe to

SDRAM FRAME_N : PCI cycle frame

CAS_SDRAM_N : Column address strobe to

SDRAM LBU_AB(20:0) : LBU address bus

WE_SDRAM_N : RD/WR SDRAM LBU_DB(15:0) : LBU data bus

CS_PER(3:0)_N : Chip select LBU_WR_N : LBU write control

RDY_PER_N : Ready signal LBU_RD_N : LBU read control

DTR_N : Direction signal for external

driver or scan clock LBU_BE(1:0)_N : LBU byte enable

OE_DRIVER _N : Enable sign al for e x ternal

driver or scan clock LBU_SEG_( 1:0) : LBU page selection

BOOT(2:0) : Boot mode LBU_IRQ_(1:0)_N : LBU interrupt request

CONFIG(4:0) : System configuration LBU_RDY_N : LBU ready signal

GPIO(31:0) : GPIO pins LBU_CS_M_N : LBU chip select to ERTEC

400 internal resourc es

TXD(2:1) : UART transmit data output LBU_CS_R_N : LBU chip select to page

configuration registers

RXD(2:1) : UART receive data input LBU_CFG : LBU separate RD/WR

DCD(2:1)_N : UART carrier detection

signal LBU_POL_RDY : LBU polari ty selection for

pin LBU_RDY_N

DSR(2:1)_N : UART data set ready signal SSPRXD : SPI receive data

CTS(2:1)_N : UART transmit enable

signal SSPT XD : SPI transm it data

AD(31:0) : PCI address data bits SCLKOUT : SPI clock out

IDSEL : PCI initialization device

select SFRMOUT : SPI serial frame output

CBE(3:0)_N : PCI byte enable SFRMIN : SPI ser ial frame input

PME_N : PCI power management SCLKIN : SPI clock in

REQ_N : PCI request SSPCTLOE : SPI clock and serial frame

output enable

GNT_N : PCI gr ant SSPOE : SPI output enable

CLK_PCI : PCI clock TXD_P(3:0) 0 : (R)MII transmit data bit 0

RES_PCI_N : PCI reset TXD_P(3:0) 1 : (R)MII transmit data bit 1

INTA_N : PCI interrupt INTA_N TXD_P(1:0) 2 : MII transmit data bit 2

INTB_N : PCI interrupt INTB_N TXD_P(1:0) 3 : MII transmit data bit 3

M66EN : PCI clock selection RXD_P(3:0) 0 : (R)MII receive data bit 0

4Data Sheet A17 813 EE 2V0 DS00

µPD800232

RXD_P(3:0) 1 : (R)MII receive data bit 1 TRST_N : JTAG reset

RXD_P(1:0) 2 : MII receive data bit 2 TCK : JTAG clock

RXD_P(1:0) 3 : MII receive data bit 3 TDI : JTAG data in

TX_EN_P(3:0) : (R)MII transmit enable TMS : JTAG test mode select

TX_ERR_P(1:0) : MII transmit error TDO : JTAG data out

CRS_DV_P(3:0) : RMII carrier sense/data

valid DBGREQ : Debug request to ARM9

RX_ER_P(3:0) : (R)MII receive error DBGACK : Debug acknowledge

CRS_P(1:0) : MII carrier sense TAP_SEL : Select TAP controller

RX_DV_P(1:0) : MII receive data valid CLKP_A : Quartz connection

COL_P(1:0) : MII collision CLKP_B : Quartz connection

RX_CLK_P(1:0) : MII receive clock REF_CLK : Reference clock input

TX_CLK_P(1:0) : MII transmit clock F_CLK : Clock for F-counter

SMI_MDC : (R)MII SMI clock RESET_N : HW reset

SMI_MDIO : (R)MII SMI input/output WDOUT0_N : Watchdog output

RES_PHY_N : Reset to PHY VDD Core : Power sup ply for core, 1.5 V

PLL_EXT_IN_N : MC_PLL input signal GND Core : GND for core

TGEN_OUT1_N : MC_PLL output signal VDD IO : Power supply for IO, 3.3 V

TRACEPKT(7:0) : Trace pins of ETM GND IO : GND for IO

ETMEXTOUT : ETM output signal P5V_PCI : Power supply for PCI, 5 V

ETMEXTIN1 : ETM input signal AVDD : Analog power supply for

PLL, 1.5 V

PIPESTA(2:0) : Trace pipeline status AGND : Analog GND fo r PLL

TRACESYNC : Trace sync signal AVDD_PCI : Analog power supply for

PLL in PCI I/F, 1.5 V

TRACECLK : ETM trace or scan clock AGND_PCI : Analog GND for PLL in PCI

I/F

(2/2)

Data Sheet A17813EE2V0DS00

µPD800232

PIN CONFIGURATION

•304-Pin Plastic FBGA (19 mm × 19 mm)

(1/5)

Number Pin Name Pin

Number Pin Name

A2 AD1/LBU_DB1 A21 GND IO

A3 VDD IO B1 A0

A4 AD7/LBU_DB7 B2 AD2/LBU_DB2

A5 VDD IO B3 AD3/LBU_DB3

A6 AD12/LBU_DB12 B4 AD5/LBU_DB5

A7 GND IO B5 AD8/LBU_DB8

A8 VDD IO B6 AD10/LBU_DB10

A9 PERR_N/LBU_RD_N B7 AD14/LBU_DB14

A10 IRDY_N/LBU_AB3 B8 CBE1_N/LBU_BE1_N

A11 VDD IO B9 SERR_N/LBU_POL_RDY

A12 FRAME_N/LBU_AB4 B10 DEVSEL_N/LBU_AB1

A13 CBE2_N/LBU_AB5 B11 VDD Core

A14 AD19/LBU_AB9 B12 AD16/LBU_AB6

A15 VDD IO B13 AD17/LBU_AB7

A16 CBE3_N/LBU_AB15 B14 AD21/LBU_AB11

A17 AD27/LBU_AB19 B15 AD23/LBU_AB13

A18 VDD IO B16 AD25/LBU_AB17

A19 REQ_N/LBU_CS_M_N B17 AD29/LBU_SEG_0

A20 VDD IO B18 AD31/LBU_CS_R_N

INDEX MARK

6Data Sheet A17 813 EE 2V0 DS00

µPD800232

B19 CLK_PCI E15 P5V_PCI

B20 INTB_N/LBU_IRQ1_N E16 GND IO

B21 RXD_P3(1)/RXD_P1(3) E17 RES_PCI_N

B22 RXD_P3(0)/RXD_P1(2) E18 VDD Core

C1 A2 E19 VDD Core

C2 A1 E21 RX_ER_P3/COL_P1

C21 TXD_P3(1)/TXD_P1(3) E22 RXD_P2(1)/RXD_P1(1)

C22 TXD_P3(0)/TXD_P1(2) F1 A7

D1 A4 F2 A6

D2 A3 F4 A16/BOOT0

D4 AD0/LBU_DB0 F5 A15

D5 AD4/LBU_DB4 F6 VDD Core

D6 VDD Core F7 GND IO

D7 CBE0_N/LBU_BE0_N F8 P5V_PCI

D8 AD9/LBU_DB9 F9 AD15/LBU_DB15

D9 VDD Core F10 GND Core

D10 STOP_N/LBU_AB00 F13 GND IO

D11 TRDY_N/LBU_AB2 F14 AD24/LBU_AB16

D12 P5V_PCI F15 AD28/LBU_AB20

D13 IDSEL/LBU_AB14 F16 GND Core

D14 AD30/LBU_SEG_1 F17 VDD Core

D15 VDD Core F1 8 GN D IO

D16 PME_N/LBU_RDY_N F19 CRS_DV_P3/RX_DV_P1

D17 GNT_N/LBU_CFG F21 RXD_P2(0)/RXD_P1(0)

D18 INTA_N/LBU_IRQ0_N F22 AVDD_PCI

D19 M66EN G1 A9

D21 TX_EN_P3/TX_ERR_P1 G2 A8

D22 VDD IO G4 A17/BOOT1

E1 VDD IO G5 GND IO

E2 A5 G6 GND Core

E4 A14 G17 GND Core

E5 VDD Core G18 CRS_DV_P2/CRS_P1

E6 GND Core G19 CRS_DV_P1/RX_DV_P0

E7 AD6/LBU_DB6 G21 AGND_PCI

E8 AD11/LBU_DB11 G22 TXD_P2(1)/TXD_P1(1)

E9 AD13/LBU_DB13 H1 A11

E10 PAR/LBU_WR_N H2 A10

E11 AD18/LBU_AB8 H4 VDD Core

E12 AD20/LBU_AB10 H5 A20/CONFIG1

E13 AD22/LBU_AB12 H6 A19/CONFIG0

E14 AD26/LBU_AB18 H17 leave open

(2/5)

Number Pin Name Pin

Number Pin Name

Data Sheet A17813EE2V0DS00

µPD800232

H18 RX_CLK_P1 N2 D0

H19 CRS_DV_P0/CRS_P0 N4 D18

H21 TXD_P2(0)/TXD_P1(0) N5 VDD Core

H22 TX_EN_P2/TX_EN_P1 N6 D16

J1 A13 N17 GPIO4

J2 A12 N18 SMI_MDIO

J4 A18/BOOT2 N19 VDD Core

J5 A22/CONFIG3 N21 TXD_P0(1)/TXD_P0(1)

J6 A21/CONFIG2 N22 RXD_P0(0)/RXD_P0(0)

J17 TX_CLK_P1 P1 D1

J18 RX_ER_P2/RX_ER_P1 P2 D2

J19 VDD Core P4 VDD Core

J21 RXD_P1(1)/RXD_P0(3) P5 D19

J22 VDD IO P6 GND IO

K1 RAS_SDRAM_N P17 leave open

K2 CS_SDRAM_N P18 VDD Core

K4 VDD Core P19 GPIO5

K5 A23/CONFIG4 P21 TX_EN_P0/TX_EN_P0

K6 GND Core P22 TXD_P0(0)/TXD_P0(0)

K17 TX_CLK_P0 R1 VDD IO

K18 RX_ER_P0/RX_ER_P0 R2 D3

K19 RX_CLK_P0 R4 D21

K21 RXD_P1(0)/RXD_P0(2) R5 D22

K22 GND IO R6 D20

L1 VDD IO R17 G ND IO

L2 CLK_SDRAM R18 VDD Core

L4 CAS_SDRAM_N R19 GPIO6

L5 BE2_DQM2_N R21 RES_PHY_N

L18 GND Core R22 REF_CLK

L19 VDD Core T1 D4

L21 TXD_P1(1)/TXD_P0(3) T2 D5

L22 TXD_P1(0)/TXD_P0(2) T4 BE3_DQM3_N

M1 GND IO T5 D23

M2 WE_SDRAM_N T6 GND IO

M4 VDD Core T17 GND Core

M5 D17 T18 GND IO

M18 SMI_MDC T19 GPIO7

M19 TX_EN_P1/TX_ERR_P0 T21 GPIO0

M21 RXD_P0(1)/RXD_P0(1) T22 VDD IO

M22 RX_ER_P1/COL _P0 U1 GND Core

N1 BE0_DQM0_N U2 D6

(3/5)

Number Pin Name Pin

Number Pin Name

8Data Sheet A17 813 EE 2V0 DS00

µPD800232

U4 VDD Core W7 VDD Core

U5 G ND Core W8 VDD Core

U6 VDD Core W9 GPIO28

U7 GND Core W10 GPIO27

U8 DTR_N W11 AVDD

U9 G ND Core W12 CLKP_B

U10 AGND W13 G PIO12/C T S1_N/ ETM EXTOUT

U13 GND Core W14 VDD Core

U14 GND Core W15 VDD Core

U15 GPIO14/RXD2 W16 GPIO15/DCD2_N/WDOUT0_N

U16 GND IO W17 VDD Core

U17 VDD Core W1 8 TDI

U18 GND Core W19 TCK

U19 TMS W21 DBGREQ

U21 GPIO1 W22 GPIO18/SSPRXD

U22 GND IO Y1 VDD IO

V1 BE1_DQM1_N Y2 D10

V2 D7 Y21 PIPESTA0

V4 D24 Y22 GPIO23/SCLKIN/DBGACK

V5 VDD Core AA1 D11

V6 CS_PER3_N AA2 D13

V7 GND IO AA3 D15

V8 OE_DRIVER_N AA4 D26

V9 GND Core AA5 D28

V10 GPIO29 AA6 D30

V11 GPIO30 AA7 CS_PER1_N

V12 GPIO31 AA8 RDY_PER_N

V13 GND IO AA9 WR_N

V14 VDD Core AA10 GPIO25/TGEN_OUT1_N

V15 GPIO13/TXD2 AA11 GPIO24/PLL_EXT_IN_N

V16 TDO AA12 F_CLK

V17 GND Core AA13 CLKP_A

V18 VDD Core AA14 GPIO17/CTS2_N/S SPOE

V19 TRST_N AA15 RESET_N

V21 GPIO3 AA16 GPIO22/SFRMIN/TRACEPKT7

V22 GPIO2 AA17 GPIO20/SCLKOUT/TRACEPKT5

W1 D8 AA18 GPIO11/DSR1_N/TRACEPKT3

W2 D9 AA19 GPIO10/DCD1_N/TRACEPKT2

W4 D12 AA20 GPIO8/TXD1/TRACEPKT0

W5 D25 AA21 PIPESTA2

W6 CS_PER2_N AA22 PIPESTA1

(4/5)

Number Pin Name Pin

Number Pin Name

Data Sheet A17813EE2V0DS00

µPD800232

AB2 D14 AB12 TAP_SEL

AB3 VDD IO AB13 GND IO

AB4 D27 AB14 GPIO16/DSR2_N/SSPCTLOE/ETMEXTIN1

AB5 D29 AB15 VDD IO

AB6 D31 AB16 TRACECLK

AB7 VDD IO AB17 GPIO21/SFRMOUT/TRACEPKT6

AB8 CS_PER0_N AB18 GPIO19/SSPTXD/TRACEPKT4

AB9 RD_N AB19 VDD IO

AB10 GPIO26 AB20 GPIO9/RXD1/TRACEPKT1

AB11 VDD IO AB21 TRACESYNC

(5/5)

Number Pin Name Pin

Number Pin Name

10 Data Sheet A17 813 EE 2V0 DS00

µPD800232

Table of Contents

1. Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.2 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.3 Pin Status and Recommended Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.4 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4.1 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4.2 I/O timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4.3 LBU timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.4 SPI timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2.4.5 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.4.6 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3. Package Drawin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4. Recommended Solderi ng Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Data Sheet A17813EE2V0DS00

µPD800232

List of Figures

Figure 2-1: Clock Waveforms ........................................................................................................ 32

Figure 2-2: Input Setup and Hold Waveforms ............................................................................... 35

Figure 2-3: Output Delay Waveforms ............................................................................................ 35

Figure 2-4: LBU Read from ERTEC 400 with Separate Read/Write line....................................... 37

Figure 2-5: LBU Write to ERTEC 400 with Separate Read/Write line ........................................... 38

Figure 2-6: LBU Read from ERTEC 400 with Common Read/Write line....................................... 39

Figure 2-7: LBU Write to ERTEC 400 with Common Read/Write line ........................................... 40

Figure 2-8: SPI Timing in Slave Mode (TI-format Example).......................................................... 41

Figure 2-9: SPI Timing in Master Mode (TI-format Example)........................................................ 42

Figure 2-10: Power-Up Sequence Timing Diagram......................................................................... 43

Figure 2-11: Reset Timing Diagram................................................................................................. 44

Figure 3-1: Package Drawing ........................................................................................................ 45

12 Data Sheet A17 813 EE 2V0 DS00

µPD800232

List of Tables

Table 1-1: External Memory Interface Pin Functions....................................................................... 13

Table 1-2: PCI Interface Pin Functions............................................................................................14

Table 1-3: Local Bus Interface Pin Functions..................................................................................15

Table 1-4: RMII Interface Pin Functions..........................................................................................16

Table 1-5: MII Interface Pin Functions............................................................................................. 17

Table 1-6: General Purpose I/O Pin Functions................................................................................ 18

Table 1-7: UART1 and UART2 Pin Functions................................................................................. 19

Table 1-8: SPI Pin Functions........................................................................................................... 19

Table 1-9: MC_PLL Pin Functions................................................................................................... 20

Table 1-10: Clock and Reset Pin Functions ...................................................................................... 20

Table 1-11: JTAG and Debug Interface Pin Functions...................................................................... 20

Table 1-12: Trace Port Pin Functions................................................................................................21

Table 1-13: Power Supply Pin Functions...........................................................................................21

Table 1-14: Pin Characteristics..........................................................................................................22

Table 1-15: Pin Status During Reset and Recommended Connections............................................24

Table 2-1: Absolute Maximum Ratings............................................................................................ 27

Table 2-2: Recommended Operating Conditions ............................................................................ 28

Table 2-3: Thermal Characteristics of Package...............................................................................30

Table 2-4: Clock AC Characteristics................................................................................................31

Table 2-5: I/O Timing Specifications................................................................................................ 33

Table 2-6: LBU Read from ERTEC 400 with Separate Read/Write line.......................................... 37

Table 2-7: LBU Write to ERTEC 400 with Separate Read/Write line .............................................. 38

Table 2-8: LBU Read from ERTEC 400 with Common Read/Write line.......................................... 39

Table 2-9: LBU Write to ERTEC 400 with Common Read/Write line .............................................. 40

Table 2-10: SPI Timing Specifications (slave mode).........................................................................41

Table 2-11: SPI Timing Specifications (master mode) ......................................................................42

Table 4-1: Soldering Conditions for Lead-free Device..................................................................... 46

Data Sheet A17813EE2V0DS00

µPD800232

1. Pin Functions

1.1 List of Pin Functions

Table 1-1: External Memory Interface Pin Functions

Pin Name I/O Function Alternate Function

A(23:19) I/ONote External memory address bus (23:19) CONFIG(4:0)Note

A(18:16) I/ONote External memory address bus (18:16) BOOT(2:0)Note

A(15:0) O External memory address bus (15:0) -

D(31:0) I/O External memory data bus (31:0) -

WR_N O Write strobe signal -

RD_N O Read strobe signal -

CLK_SDRAM O Clock to SDRAM -

CS_SDRAM_N O Chi p select to SDRAM -

RAS_SDRAM_N O Row address strobe to SDRAM -

CAS_SDRAM_ N O Column address strobe to SDRAM -

WE_SDRAM_N O RD/WR signal to SDRAM -

CS_PER(3:0)_N O Chip select to static memories/peripherals -

BE(3:0)_DQM(3:0)_N O Byte enable to static memories/peripherals and SDRAM -

RDY_PER_N I Ready signal from static peripherals -

DTR_N O Direction signal for external driver or scan clock -

OE_DRIVER_N O Enable signal for external driver or scan clock -

Note: The BOOT(2:0) and CONFIG(4:0) pins are used as inputs and read into the Boot_REG respectively

Config_REG system configuration registers during the active RESET phase. After a reset, these pins are

available as normal function pins and used as outputs.

14 Data Sheet A17813EE2V0DS00

µPD800232

Table 1-2: PCI Interface Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

AD31 I/O PCI address/data bit LBU_CS_R_N

AD(30:29) I/O PCI address/data bits LBU_SEG_(1:0)

AD(28:24) I/O PCI address/data bits LBU_AB(20:16)

AD(23:16) I/O PCI address/data bits LBU_AB(13:6)

AD(15:0) I/O PCI address data bits LBU_DB(15:0)

IDSEL I PCI initialization device select LBU_AB14

CBE3_N I/O PCI byte enable LBU_AB15

CBE2_N I/O PCI byte enable LBU_AB5

CBE1_N I/O PCI byte enable LBU_BE1_N

CBE0_N I/O PCI byte enable LBU_BE0_N

PME_N I/O PCI power management LBU_RDY_N

REQ_N O PCI request LBU_CS_M_N

GNT_N I PCI grant LBU_CFG

CLK_PCI I PCI clock -

RES_PCI_N I PCI reset -

INTA_N O PCI INTA_N LBU_IRQ0_N

INTB_N O PCI INTB_N LBU_IRQ1_N

M66EN I PCI clock selection -

PAR I/O PCI parity LBU_WR_N

SERR_N I/O PCI system Error LBU_POL_RDY

PERR_N I/O PCI parity Error LBU_RD_N

STOP_N I/O PCI stop LBU_AB0

DEVSEL_N I/O PCI device select LBU_AB1

TRDY_N I/O PCI target ready LBU_AB2

IRDY_N I/O PCI initiator ready LBU_AB3

FRAME_N I/O PCI cycle frame LBU_AB4

Note: PCI pins are alternatively used as local bus interface pins; in this table the I/O type is listed for the PCI

function.

Data Sheet A17813EE2V0DS00

µPD800232

Table 1-3: Local Bus Interface Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

LBU_AB(20:16) I LBU address bits AD(28:24)

LBU_AB15 I LBU address bit CBE3_N

LBU_AB14 I LBU address bit IDSEL

LBU_AB(13:6) I LBU address bits AD(23:16)

LBU_AB5 I LBU address bit CBE2_N

LBU_AB4 I LBU address bit FRAME_N

LBU_AB3 I LBU address bit IRDY_N

LBU_AB2 I LBU address bit TRDY_N

LBU_AB1 I L BU address bit DEVSEL_N

LBU_AB0 I LBU address bit STOP_N

LBU_DB(15:0) I/O LBU data bits AD(15:0)

LBU_WR_N I LBU write control signal PAR

LBU_RD_N I LBU read control signal PERR_N

LBU_BE(1:0)_N I LBU byte enable CBE(1:0)_N

LBU_SEG_(1:0) I LBU page selection signal AD(30:29)

LBU_IRQ_1_N O LBU interrupt request signal INTB_N

LBU_IRQ_0_N O LBU interrupt request signal INTA_N

LBU_RDY_N O LBU ready signal PME_N

LBU_CS_M_N I LBU chip select for ERTEC 400 internal resources REQ_N

LBU_CS_R_N I LBU chip select for page configuration registers AD31

LBU_CFG I LBU RD/WR control selection GNT_N

LBU_POL_RDY I LBU polarity selection for LBU_RDY_N pin SERR_N

Note: Local bus interface pins are alternatively used as PCI pins; in this table the I/O type is listed for the local

bus function.

16 Data Sheet A17813EE2V0DS00

µPD800232

Table 1-4: RMII Interface Pin Functions

Pin NameNote I/O Function Alternate FunctionNote

SMI_MDC O S MI clock SMI_M DC

SMI_MDIO I/O SMI inp ut/o utp ut SMI _M DIO

RES_PHY_N O Reset PHY RES_PHY_N

TXD_P0(1:0) O Transmit Data Port 0 bits TXD_P0(1:0)

RXD_P0(1:0) I Receive Data Port 0 bits RXD_P0(1:0)

TX_EN_P0 O Transmit Enable Port 0 TX_EN_P0

CRS_DV_P0 I Carrier Sense/Data Valid Port 0 CRS_P0

RX_ ER_P0 I Receive Error Port 0 RX_ ER_ P0

TXD_P1(1:0) O Transmit Data Port 1 bits TXD_P0(3:2)

RXD_P1(1:0) I Receive Data Port 1 bits RXD_P0(3:2)

TX_EN_P1 O Transmit Enable Port 1 TX_ERR_P0

CRS_DV_P1 I Carrier Sense/Data Valid Port 1 RX_DV_P0

RX_ ER_P1 I Receive Error Port 1 COL_P0

TXD_P2(1:0) O Transmit Data Port 2 bits TXD_P1(1:0)

RXD_P2(1:0) I Receive Data Port 2 bits RXD_P1(1:0)

TX_EN_P2 O Transmit Enable Port 2 TX_EN_P1

CRS_DV_P2 I Carrier Sense/Data Valid Port 2 CRS_P1

RX_ ER_P2 I Receive Error Port 2 RX_ ER_ P1

TXD_P3(1:0) O Transmit Data Port 3 bits TXD_P1(3:2)

RXD_P3(1:0) I Receive Data Port 3 bits RXD_P1(3:2)

TX_EN_P3 O Transmit Enable Port 3 TX_ERR_P1

CRS_DV_P3 I Carrier Sense/Data Valid Port 3 RX_DV_P1

RX_ER_P3 I Receive Error Port 3 COL_P1

Note: The alte rnate func ti ons of RMI I pi ns are M II p ins ; t here for e s ome p in names a re i dentical fo r bo th con fig -

ura ble functi ons.

Data Sheet A17813EE2V0DS00

µPD800232

Table 1-5: MII Interface Pin Functions

Pin NameNote I/O Function Alternate FunctionNote

SMI_MDC O Serial management interface clock SMI_MDC

SMI_MDIO I/O Serial management interface data input/output SMI_MDIO

RES_PHY_N O Reset signal to PHYs RES_PHY_N

TXD_P0(3:2) O Transmit data port 0 bits TXD_P1(1:0)

TXD_P0(1:0) O Transmit data port 0 bits TXD_P0(1:0)

RXD_P0(3:2) I Receive data port 0 bits RXD_P1(1:0)

RXD_P0(1:0) I Receive data port 0 bits RXD_P0(1:0)

TX_EN_P0 O Transmit enable port 0 TX_EN_P0

CRS_P0 I Carrier sense port 0 CRS_DV_ P0

RX_ER_P0 I Receive error port 0 RX_ER_P0

TX_E RR_P0 O Transmit err or port 0 TX_EN_P1

RX_DV_P0 I Receive data valid port 0 CRS_DV_P1

COL_P0 I Collision port 0 RX_ER_P1

RX_CLK_P0 I Receive clock port 0 -

TX_CLK_ P0 I Tran smit clock port 0 -

TXD_P1(3:2) O Transmit data port 1 bits TXD_P3(1:0)

TXD_P1(1:0) O Transmit data port 1 bits TXD_P2(1:0)

RXD_P1(3:2) I Receive data port 1 bits RXD_P3(1:0)

RXD_P1(1:0) I Receive data port 1 bits RXD_P2(1:0)

TX_EN_P1 O Transmit enable port 1 TX_EN_P2

CRS_P1 I Carrier sense port 1 CRS_DV_ P2

RX_ER_P1 I Receive error port 1 RX_ER_P2

TX_E RR_P1 O Transmit err or port 1 TX_EN_P3

RX_DV_P1 I Receive data valid port 1 CRS_DV_P3

COL_P1 I Collision port 1 RX_ER_P3

RX_CLK_P1 I Receive clock port 1 -

TX_CLK_ P1 I Tran smit clock port 1 -

Note: The alte rnate func tio ns of MII pins are RMII pi ns ; th erefore some pin n am es are id en tic al for bot h c on fig-

urable functions.

18 Data Sheet A17813EE2V0DS00

µPD800232

Table 1-6: General Purpose I/O Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

GPIO(31:26) I/O General purpose I/O signal -

GPIO25 I/O General purpose I/O signal TGEN_OUT1_N

GPIO24 I/O General purpose I/O signal PLL_EXT_IN_N

GPIO23 I/O General purpose I/O signal SCLKIN, DBGACK

GPIO22 I/O General purpose I/O signal SFRMIN, TRACEPKT7

GPIO21 I/O General purpose I/O signal SFRMOUT, TRACEPKT6

GPIO20 I/O General purpose I/O signal SCLKOUT, TRACEPKT5

GPIO19 I/O General purpose I/O signal SSPTXD, TRACEPKT4

GPIO18 I/O General purpose I/O signal SSPRXD

GPIO17 I/O General purpose I/O signal CTS2_N, SSPOE

GPIO16 I/O General purpose I/O signal DSR2_N, SSPCTLOE, ETMEXTIN1

GPIO15 I/O General purpose I/O signal DCD2_N, WDOUT0_N

GPIO14 I/O General purpose I/O signal RXD2

GPIO13 I/O General purpose I/O signal TXD2

GPIO12 I/O General purpose I/O signal CTS1_N, ETMEXTOUT

GPIO11 I/O General purpose I/O signal DSR1_N, TRACEPKT3

GPIO10 I/O General purpose I/O signal DCD1_N, TRACEPKT2

GPIO9 I/O General purpose I/O signal RXD1, TRACEPKT1

GPIO8 I/O General purpose I/O signal TXD1, TRACEPKT0

GPIO(7:0) I/O General purpose I/O signal -

Note: Function and alternative functions are selected with the GPIO_PORT_MODE_H and

GPIO_PORT_MODE_L registers. In this table the I/O types are listed for the GPIO function.

Data Sheet A17813EE2V0DS00

µPD800232

Table 1-7: UART1 and UART2 Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

TXD1 O UART1 transmit data output GPIO8, TRACEPKT0

RXD1 I UART1 receive data input GPIO9, TRACEPKT1

DCD1_N I UART1 carrier detection signal GPIO10, TRACEPKT2

DSR1_N I UART1 data set ready signal GPIO11, TRACEPKT3

CTS1_N I UART1 transmit enable signal GPIO12, ETMEXTOUT

TXD2 O UART2 transmit data output GPIO13

RXD2 I UART2 receive data input GPIO14

DCD2_N I UART2 carrier detection signal GPIO15, WDOUT0_N

DSR2_N I UART2 data set ready signal GPIO16, SSPCTLOE, ETMEXTIN1

CTS2_N I UART2 transmit enable signal GPIO17, SSPOE

Note: Function and alternative functions are selected with the registers GPIO_PORT_MODE_H and

GPIO_PORT_MODE_L. In this table the I/O types are listed for the UART1 and UART2 functions.

Table 1-8: SPI Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

SSPRXD I SPI receive data input GPIO18

SSPTXD O SPI transmit data output GPIO19, TRACEPKT4

SCLKOUT O SPI clock output GPIO20, TRACEPKT5

SFRMOUT O SPI serial frame input signal GPIO21, TRACEPKT6

SFRMIN I SPI serial frame output signal GPIO22, TRACEPKT7

SCLKIN I SPI clock input GPIO23, DBGACK

SSPCTLOE O SPI clock and serial frame output ena b l e GPIO16, DSR2_N, ETMEXTIN1

SSPOE O SPI output enable GPIO17, CTS2_N

Note: Function and alternative functions are selected with the GPIO_PORT_MODE_H register. In this table

the I/O types are listed for the SPI function.

20 Data Sheet A17813EE2V0DS00

µPD800232

Table 1 -9: MC_PLL Pin Functions

Pin Name I/ONote 1 Function Alternate FunctionNote 1

PLL_EXT_IN_N I MC_PLL input signal GPIO24

TGEN_OUT1_N O MC_PLL output signalNote 2 GPIO25

Notes: 1. Functio n and a lternativ e funct ions a re sel ected with the GPI O_PORT_MODE_H regis ter. In this tab le

the I/O types are listed for the MC_PLL function.

2. For a PROF INET IRT applicatio n, GPI O2 5 must be c onf igu r ed as TGEN _O UT1 _N o utpu t p in. A s yn -

chronous clock signal is then output at this pin; during certification of a PROFINET IO device with

IRT support this signal must be accessible from the outside.

Table 1-10: Clock and Reset Pin Functions

Pin Name I/O Function Alternate Function

TRACECLK O E TM tr ace or scan cl ock -

CLKP_A I Quartz connection -

CLKP_B O Quartz connection -

F_CLK I F_CLK f or F-coun ter -

REF_CLK I Reference clock -

RESET_N I Hardware reset -

Table 1-11: JTAG and Debug Interface Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

TRST_N I JTAG reset signal -

TCK I JTAG clock signal -

TDI I JTAG data input signal -

TMS I JTAG test mode sel ect signal -

TDO O JTAG data output signal -

DBGREQ I Deb ug requ es t sign al -

DBGACK O De bug ac kn o w l edg e sign al GPIO2 3/SCLKIN

TAP_SEL I TAP controller select signal -

Note: The DBGACK pin is alternatively used as GPIO or SPI pin; the function is selected with the

GPIO_PORT_MODE_H register. In this table the I/O type is listed for the DBGACK function.

Data Sheet A17813EE2V0DS00

µPD800232

Note: In PCI mode the P5V_PCI pins must be connected to the PCI bus supply pins +VIO (name

according to PCI specification). In LBU mode the P5V_PCI pins must be connected to VDD IO.

Table 1-12: Trace Port Pin Functions

Pin Name I/ONote Function Alternate FunctionNote

TRACEPKT7 O Trace packet bit GPIO22/SFRMIN

TRACEPKT6 O Trace packet bit GPIO21/SFRMOUT

TRACEPKT5 O Trace packet bit GPIO20/SCLKOUT

TRACEPKT4 O Trace packet bit GPIO19/SSPTXD

TRACEPKT3 O Trace packet bit GPIO11/DSR1_N

TRACEPKT2 O Trace packet bit GPIO10/DCD1_N

TRACEPKT1 O Trace packet bit GPIO9/RXD1

TRACEPKT0 O Trace packet bit GPIO8/TXD1

PIPESTA(2:0) O CPU pipeline status -

TRACESYNC O Trace sync signal -

ETMEXTIN1 I External input to the ETM GPIO16/DSR2_N/SSPCTLOE

ETMEXTOUT O Output signal from the ETM GPIO12/CTS1_N

Note: Several trace por t pins are alternatively used as GPIO, UART or SPI pins; the function is selected with

the GPIO_PORT_MODE_H and GPIO_PORT_MODE_L registers. In this table the I/O types are listed

for the trace port pin functions.

Table 1-13: Power Supply Pin Functions

Pin Name Function

VDD Core Power supply for core, 1.5 V

GND Core GND for core

VDD IO Power supply for IO, 3.3 V

GND IO GND for IO

P5V_PCI Power supply for PCI, 5V Note

AVDD Analog power supply for PLL, 1.5 V

AGND Analog GND for PLL

AVDD_PCI Analog power supply for PLL in PCI I/F, 1.5 V

AGND_PCI Analog GND for PLL in PCI I/F

22 Data Sheet A17813EE2V0DS00

µPD800232

1.2 Pin Characteristics

Table 1-14: Pin Characteristics (1/2)

Pin Name I/O Input type Output type Internal pull

up/down Drive capabil ity

IOH IOL

A(23:16) I/ONote 1 SchmittNote 1 3.3 V CMOS - 9 mA 9 mA

A(15:0) O - 3.3 V CMOS - 9 mA 9 mA

D(31:0) I/O Schmitt 3.3 V CMOS 50 kΩ pull up 9 mA 9 mA

WR_N O - 3.3 V CMOS - 9 mA 9 mA

RD_N O - 3.3 V CMOS - 9 mA 9 mA

CLK_SDRAM O - 3.3 V CMOS - 9 mA 9 mA

CS_SDRAM_N O - 3.3 V CMOS - 9 mA 9 mA

RAS_SDRAM_N O - 3.3 V CMOS - 9 mA 9 mA

CAS_SDRAM_N O - 3.3 V CMOS - 9 mA 9 mA

WE_SDRAM_N O - 3.3 V CMOS - 9 mA 9 mA

CS_PER(3:0)_N O - 3.3 V CMOS - 6 mA 6 mA

BE(3:0)_DQM(3:0)_N O - 3.3 V CMOS - 9 mA 9 mA

RDY_PER_N I Schmitt - 50 kΩ pull up - -

DTR_N O - 3.3 V CMOS - 9 mA 9 mA

OE_DRIVER_N O - 3.3 V CMOS - 9 mA 9 mA

AD(31:0) I/O PCINote 2 PCINote 2 -

PCINote 2

IDSEL I PCINote 2 --

CBE(3:0)_N I/O PCINote 2 PCINote 2 -

PME_N I/O PCINote 2 PCINote 2 -

REQ_N O - PCINot e 2 -

GNT_N I PCINote 2 --

CLK_PCI I PCINote 2 --

RES_PCI_N I PCINote 2 --

INTA_N O - PCINote 2 -

INTB_N O - PCINot e 2 -

M66EN I Schmitt - - - -

PAR I/O PCINote 2 PCINote 2 -

PCINote 2

SERR_N I/O PCINote 2 PCINote 2 -

PERR_N I/O PCINote 2 PCINote 2 -

STOP_N I/O PCINote 2 PCINote 2 -

DEVSEL_N I/O PCINote 2 PCINote 2 -

TRDY_N I/O PCINote 2 PCINote 2 -

IRDY_N I/O PCINote 2 PCINo t e 2 -

FRAME_N I/O PCINote 2 PCINot e 2 -

Notes: 1. The address pins A(23:16) are used as inputs only during the active reset phase.

2. PCI I/Os c an b e eit her 3. 3 V PCI (if the PCI in terface is operated with 3.3 V) or 5 V tolerant PCI (if th e

PCI inte rface is con f igu red to 5 V to lerant ope ra tio n). Ple ase c heck Tables 2-1 an d 2 -2 for diff ere nc es.

Drive capability complies to the PCI specification R2.2.

Data Sheet A17813EE2V0DS00

µPD800232

PIPESTA(2:0) O - 3.3 V CMOS - 9 mA 9 mA

TRACESYNC O - 3.3 V CMOS - 9 mA 9 mA

SMI_MDC O - 3.3 V CMOS - 6 mA 6 mA

SMI_MDIO I/O Schmitt 3.3 V CMOS - 6 mA 6 mA

RES_PHY_N O - 3.3 V CMOS - 6 mA 6 mA

TXD_Pn(1:0)Note 1 O - 3.3 V CMOS - 6 mA 6 mA

RXD_Pn(1:0)Note 1 ISchmitt -50 kΩ pull down - -

TX_EN_PnNote 1 O - 3.3 V CMOS - 6 mA 6 mA

CRS_DV_PnNote 1 ISchmitt -50 kΩ pull d own - -

RX_ER_PnNote 1 ISchmitt -50 kΩ pull down - -

TXD_Pn(3:0)Note 2 O - 3.3 V CMOS - 6 mA 6 mA

RXD_Pn(3:0)Note 2 ISchmitt -50 kΩ pull down - -

TX_EN_PnNote 2 O - 3.3 V CMOS - 6 mA 6 mA

CRS_PnNote 2 ISchmitt -50 kΩ pull down - -

RX_ER_PnNote 2 ISchmitt -50 kΩ pull down - -

TX_ERR_PnNote 2 O - 3.3 V CMOS - 6 mA 6 mA

RX_DV_PnNote 2 ISchmitt -50 kΩ pull down - -

COL_PnNote 2 ISchmitt -50 kΩ pull down - -

RX_CLK_PnNote 2 ISchmitt -50 kΩ pull down - -

TX_CLK_PnNote 2 ISchmitt -50 kΩ pull down - -

GPIO(31:23) I/O Schmitt 3.3 V CMOS 50 kΩ pull u p 6 mA 6 mA

GPIO(22:19) I/O Schmitt 3.3 V CMOS 50 kΩ pull u p 9 mA 9 mA

GPIO(18:12) I/O Schmitt 3.3 V CMOS 50 kΩ pull u p 6 mA 6 mA

GPIO(11:0) I/O Schmitt 3.3 V CMOS 50 kΩ pull up 9 mA 9 mA

TRACECLK O - 3.3 V CMOS - 18 mA 18 mA

CLKP_A I Osc. in - - - -

CLKP_B O - Osc. out - 6 mA 6 mA

F_CLK I 3.3 V CMOS - - - -

REF_CLK I 3.3 V CMOS - - - -

RESET_N I Schmitt - 50 kΩ pull up - -

TRST_N I Schmitt - - - -

TCK I Schmitt - 50 kΩ pull up - -

TDI I Schmitt - 50 kΩ pull up - -

TMS I Schmitt - 50 kΩ pull up - -

TDO O - 3.3 V CMOS - 6 mA 6 mA

DBGREQ I Schmitt - 50 kΩ pull down - -

TAP_SEL I Schmitt - 50 kΩ pull up - -

Notes: 1. The number “n” can take the integer values 0 to 3 and refers to the RMII ports.

2. The number “n” can take the integer values 0 and 1 and refers to the MII ports.

Remark: Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-13 for possible

pin names first, before looking up pin characteristics in Table 1-14.

Table 1-14: Pin Characteristics (2/2)

Pin Name I/O Input type Output type Internal pull

up/down Drive capability

IOH IOL

24 Data Sheet A17813EE2V0DS00

µPD800232

1.3 Pin Status and Recommended Connections

Table 1-15: Pin Status During Reset and Recommended Connections (1/3)

Pin Name I/O Internal pull

up/down I/O during

reset Level

during reset External pull

up/dow n require d

A(23:16) I/ONote 1 -INote 1 -No t e 1

A(15:0) O - O L -

D(31:0) I/O 50 kΩ pull up I H -

WR_N O - O H -

RD_N O - O H -

CLK_SDRAM O - O L -

CS_SDRAM_N O - O H -

RAS_SDRAM_N O - O H -

CAS_SDRAM_N O - O H -

WE_SDRAM_N O - O H -

CS_PER(3:0)_N O - O H -

BE(3:0)_DQM(3:0)_N O - O H -

RDY_PER_N I 50 kΩ pull up I H -

DTR_N O - O H -

OE_DRIVER_N O - O H -

AD(31:0) I/O - I - Pull upNote 2

IDSEL I - I - Pull upNote 2

CBE(3:0)_N I/O - I - Pull upNote 2

PME_NNote 3 I/O - I H Pull upNote 4

REQ_NNote 3 O-tri-state-

Pull upNote 2, 4

GNT_NNote 3 I- I-

Pull upNote 2, 4

CLK_PCINote 3 I- I-

Pull dow n Note 2, 5

RES_PCI_N I - I - Pull upNote 2, 4, 5

INTA_NNote 3 O-tri-stateH

Pull upNote 4

INTB_NNote 3 O-tri-stateH

Pull upNote 4

M66ENNote 3 I- I-

Pull dow n Note 2, 5

PARNote 3 I/O - I - Pull upNote 2

SERR_NNote 3 I/O - I H Pull upNote 2, 4

PERR_NNote 3 I/O - I - Pull upNote 2, 4

STOP_NNote 3 I/O - I - Pull upNote 2, 4

Notes: 1. The addres s pins A(23:16) are us ed as inpu ts only during the activ e rese t phase in ord er to read the

devices proper start up configurations. A(23:16) must therefore be equipped with external pull up/

down r es ist or s a cc ord i ng t o t he d e si red s t art up c onf ig u rati on . Pl e as e co ns ult t h e us er’s manual for

details.

2. These resistors are required, when neither the PCI interface nor the LBU interface are used. In this

case ERTEC 400 must be configured to LBU mode (CONFIG2 = 0b).

3. The reset signal, that affects these pins, is RES_PCI_N.

4. These pull-up resistors are required, when the interface is operated in PCI mode.

5. These resistors are required, when the interface is operated in LBU mode.

Data Sheet A17813EE2V0DS00

µPD800232

DEVSEL_NNote 1 I/O - I - Pull upNote 2, 4

TRDY_NNote 1 I/O - I - Pull upNote 2, 4

IRDY_NNote 1 I/O - I - Pull upNote 2, 4

FRAME_NNote 1 I/O - I - Pull upNo te 4

PIPESTA(2:0) O - O L -

TRACESYNC O - O L -

SMI_MDC O - O L -

SMI_MDIO I/O - I H Pull up

RES_PHY_N O - O L -

TXD_Pn(1:0)Note 3 O- OL -

RXD_Pn(1:0)Note 3 I50 kΩ pull down I L -

TX_EN_PnNote 3 O- OL -

CRS_DV_PnNote 3 I50 kΩ pull down I L -

RX_ER_PnNote 3 I50 kΩ pull down I L -

TXD_Pn(3:0)Note 5 O- OL -

RXD_Pn(3:0)Note 5 I50 kΩ pull down I L -

TX_EN_PnNote 5 O- OL -

CRS_PnNote 5 I50 kΩ pull down I L -

RX_ER_PnNote 5 I50 kΩ pull down I L -

TX_ERR_PnNote 5 O- OL -

RX_DV_PnNote 5 I50 kΩ pull down I L -

COL_PnNote 5 I50 kΩ pull down I L -

RX_CLK_PnNot e 5 I50 kΩ pull down I L -

TX_CLK_PnNote 5 I50 kΩ pull down I L -

GPIO(31:0) I/O 50 kΩ pull up I H -

TRACECLK O - O L -

CLKP_A I - I - -

CLKP_B O - O - -

F_CLK I - I - -

REF_CLK I - I - -

RESET_N I 50 kΩ pull up I LNote 6 -

Notes: 1. The reset signal, that affects these pins is RES_PCI_N.

2. These resistors are required, when neither the PCI interface nor the LBU interface are used. In this

case ERTEC 400 must be configured to LBU mode (CONFIG2 = 0b).

3. The number “n” can take the integer values 0 to 3.

4. These pull-up resistors are required, when the interface is operated in PCI mode.

5. The number “n” can take the integer values 0 and 1.

6. RESET_N must be externally driven low in order to reset the device.

Table 1-15: Pin Status During Reset and Recommended Connections (2/3)

Pin Name I/O Internal pull

up/down I/O during

reset Level

during reset External pull

up/down required

26 Data Sheet A17813EE2V0DS00

µPD800232

TRST_N I - I HNote 1 Pull up

TCKNote 2 I 50 kΩ pull up I H -

TDINote 2 I 50 kΩ pull up I H -

TMSNote 2 I 50 kΩ pull up I H -

TDONote 2 O- OL -

DBGREQ I 50 kΩ pull down I L -

TAP_SEL I 50 kΩ pull up I H -

Notes: 1. High level is generated from external pull up resistor and not by internal device circuitry.

2. The reset signal, that affects these pins, is TRST_N.

Remark: Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-13 for possible

pin names first, before looking up reset characteristics and recommended connections in

Table 1-15.

Table 1-15: Pin Status During Reset and Recommended Connections (3/3)

Pin Name I/O Internal pull

up/down I/O during

reset Level

during reset External pull

up/dow n require d

Data Sheet A17813EE2V0DS00

µPD800232

2. Electrical Specifications

2.1 Absolute Maximum Ratings

Caution: Product quality may suffer if the absolute maximum rating is exceeded even momen-

tarily for any parameter. That is, the absolute maximum ratings are rated values at

which the product is on the verge of suffering physical damage, and therefore the

product must be used under conditions that ensure that the absolute maximum rat-

ings are not exceeded. The ratings and conditions indicated for DC characteristics

and AC characteristics represent the quality assurance range during normal opera-

tion.

Remark: 3.3 V must be applied to the I/O pins only after applying the power supply voltage.

Table 2-1: Absolute Maximum Ratings

Parameter Symbol Ratings Unit

Supply voltage 1.5 V supply VDD Core -0.5 to +2.0 V

3.3 V supply VDD IO -0.5 to +4.6 V

PLL supply AVDD, AVDD_PCI -0.5 to +2.0 V

Input voltage

3.3 V CMOS,

VI < VDD + 0.5 V

-0.5 to+ 4.6 V

3.3 V PCI,

VI < VDD + 0.5 V -0.5 to 5.1 V

5 V tol. PCI -0.6 to VDD IO + 2.4 V

Junction temperature TJ-40 to +120 °C

Stor age temperatur e TSTG -65 to +150 °C

28 Data Sheet A17813EE2V0DS00

µPD800232

2.2 Operating Conditions

Table 2-2: Recommended Operating Conditions (1/2)

Parameter Symbol Test

Conditions MIN. TYP. MAX. Unit

Supply voltage

1.5 V supply VDD Core 1.35 1.5 1.65 V

3.3 V supply VDD IO 3.0 3.3 3.6 V

5V supply Note P5V_PCI 4.75 5 5.25 V

PLL supply AVDD,

AVDD_PCI 1.35 1.5 1.65 V

Ambient temperature TA-40 +85 °C

Output voltage high

3.3 V CMOS

VOH

IOH = 0 mA VDD IO -

0.1 V V

nominal

output cur-

rent 2.4 V

3.3 V PCI IOH = -0.5

mA 0.9 x

VDD IO V

5 V tol. PCI IOH = -2 mA 2.4 V

Output voltage low

3.3 V CMOS

VOL

IOL = 0 mA 0.1 V

nominal

output cur-

rent 0.4 V

3.3 V PCI IOH = 1.5

mA 0.1 x

VDD IO V

5 V tol. PCI IOH = 3 mA 0.55 V

Input v ol tag e high

3.3 V CMOS

VIH

2 VDD IO V

3.3 V PCI 0.5 x

VDD IO VDD IO

+ 0.5 V V

5 V tol. PCI 2 P5V_PCI

+ 0.5 V V

Input v ol tag e lo w

3.3 V CMOS

VIL

00.8V

3.3 V PCI -0.5 0.3 x

VDD IO V

5 V tol. PCI -0.5 0.8 V

Pos itive trigger v olt age Schmitt

input

VP1.2 2.4 V

Negative trigger voltage VN0.6 1.8 V

Hysteresis voltage VH0.3 1.5 V

Input rise time 3.3 V CMOS tRI 0200ns

Input fall time tFI 0200ns

Input rise time Schmitt

input tRI 010ms

Input fall time tFI 010ms

Note: This condition applies only, if the PCI interface is actually operated at 5 V.

Data Sheet A17813EE2V0DS00

µPD800232

Parameter Symbol Test

Conditions MIN. TYP. MAX. Unit

Pull up resistor (nominal 50 kΩ) 14.2 31.9 80.7 kΩ

Pull down resistor (nominal 50 kΩ) 20.6 44.9 116.4 kΩ

CPU clock frequencyNote 1 PFC 150 MHz

Oscillator clock frequencyNote 2 PLL_FC 12.5

- 50 ppm 12.5 12.5

+ 5 0 ppm MHz

Ref e rence cloc k frequen cyNote 3 REF_PLL_FC 50

- 50 ppm 50 50

+ 5 0 ppm MHz

MII transmit/receive clock frequencyNote 4 PHY_Tx/

Rx_M_FC 2.5 25 MHz

Supply currentNote 5, 6 1.5 V supply IDD Core 300 495 mA

3.3 V supply IDD IO 80 145 mA

Power

consumptionNote 5, 6

1.5 V supply PDD Core 450 740 mW

3.3 V supply PDD IO 265 470 mW

total PDD 715 1210 mW

Notes: 1. The CPU clock is an internal signal. Different CPU core operation frequencies can be selected via

hardware settings during reset; possible settings are 50/100/150 MHz.

2. The oscillator clock is present at the CLKP_A and CLKP_B pins.

3. The reference clock must be applied to the REF_CLK pin. If ERTEC 400 is operated in RMII mode,

the reference clock is also used for the RMII interface.

4. The MII transmit/receive clock must be applied to the RX_CLK_P(1:0) and TX_CLK_P(1:0) pins, if

ERTEC 400 is operated in MII mode. It is not required in RMII mode.

5. Typical values for supply currents and power consumption have been measured under the following

conditions:

•Operation of ERTEC 400 on the EB400 evaluation board with 150 MHz core clock frequency

•SDRAM test program and Ethernet traffic running

•No activity on PCI respectively LBU interfaces

6. Maximum values for supply currents and power consumption have been calculated for

VDD IO = 3.6 V and VDD Core = 1.65 V at TA = 85°C.

Table 2-2: Recommended Operating Conditions (2/2)

30 Data Sheet A17813EE2V0DS00

µPD800232

2.3 Thermal Characteristics

Table 2-3: Thermal Characteristics of Package

Parameter Symbol Airflow (m/s) Unit

00.21 2

Thermal resistance junction to ambientNote 1 Θ

ja 30 27 23 21 K/W

Thermal resistance junction to top center of

the package surfaceNote 1 Ψ

jt 0.2 0.3 0.6 0.8 K/W

Thermal resistance top center of the package

surface to ambientNote 1 Ψ

ta 29.8 26.7 22.4 20.2 K/W

Thermal resistance junction to caseNote 2 Θ

jc 5.2 5.2 5.2 5.2 K/W

Maximum case temper ature Tcmax 105 °C

Notes: 1. The parameters are valid, if no heat sink is used and a PCB with at least 4 layers and massive

ground and power planes.

2. The parameter is valid, if a heat sink is used.

Data Sheet A17813EE2V0DS00

µPD800232

2.4 AC Characteristics

2.4.1 Clock timing

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Table 2-4: Clock AC Characteristics (1/2)

Parameter Symbol MIN. TYP. MAX. Unit

Processor clock frequencyNote 1 PFC 50/100/

150 MHz

Processor clock periodNote 1 PTC 20/10/

6.66 ns

Oscillator clock frequency PLL_FC 12.5

- 50 ppm 12.5 12.5

+ 50 ppm MHz

Reference clock frequency REF_PLL_FC 50

- 50 ppm 50 50

+ 50 ppm MHz

PCIClk input frequency PCI_FC 66.66 MHz

PCIClk input period PCI_TC 15 ns

PCIClk input high timeNote 2 PCI_TCH 40 60 %

PCIClk input low timeNote 2 PCI_TCL 40 60 %

JTAGClk frequency JTAG_FC 10 MHz

JTAGClk period JTAG_TC 100 ns

MII transmit clock frequency PHY_Tx_M_FC 2.5 25 MHz

MII transmit clock period PHY_Tx_M_TC 40 400 ns

MII transmit clock input high timeNote 2 PHY_Tx_M_TCH 35 %

MII transmit clock input low timeNote 2 PHY_Tx_M_TCL 35 %

MII receive clock frequency PHY_Rx_M_FC 2.5 25 MHz

MII receive clock period PHY_Rx_M_TC 40 400 ns

MII receive clock input high timeNote 2 PHY_Rx_M_TCH 35 %

MII receive clock input low timeNote 2 PHY_Rx_M_TCL 35 %

SPI1_SCLKIN frequ en cy (slav e mo de) SPI1_S_FC 0 4.16 MHz

SPI1_SCLKIN low time (slave mode) SPI1_S_TCL 120 ns

SPI1_SCLKIN high time (slave mode) SPI1_S_TCH 120 ns

SPI1_SCLKOUT frequency

(master mode) SPI1_M_FC 769 x 10-6 25 MHz

SPI1_SCLKOUT period

(master mode) SPI1_M_TC 40 1.3 x 106ns

SPI1_SCLKOUT low time

(master mode)Note 2 SPI1_M_TCL 45 55 %

SPI1_SCLKOUT high time

(master mode)Note 2 SPI1_M_TCH 45 55 %

Notes: 1. The actually permitted maximum clock frequency respectively minimum clock period is given by the

CONFIG(4:3) pin setting during reset and depends additionally on the accuracy of the oscillator

clock.

2. High time and low time are specified in per cent of the nominal clock period.

32 Data Sheet A17813EE2V0DS00

µPD800232

Figure 2-1: Clo ck Waveforms

CLK_SDRAM frequency SDRAM_FC 50 MHz

CLK_SDRAM period SDRAM_TC 20 ns

CLK_SDRAM clock stability SDRAM_TCS +/- 0.2 ns

CLK_SDRAM input high timeNote SDRAM_TCH 40 60 %

CLK_SDRAM input low timeNote SDRAM_TCL 40 60 %

Note: High time and low time are specified in per cent of the nominal clock period.

Table 2-4: Clock AC Characteristics (2/2)

Parameter Symbol MIN. TYP. MAX. Unit

TCL

2.0 V

1.5 V

0.8 V

Data Sheet A17813EE2V0DS00

µPD800232

2.4.2 I/O timing specifications

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Table 2-5: I/O Timing Specifications (1/2)

Signal Input Output Unit Clock Notes

Setup time

TIS min. Hold time

TIH min. Valid delay

TOV max. Hold time

TOHmin.

D(31:0) 10 0 12.5 2 ns CLK_SDRAM 6

A(23:0) 11 2 ns CLK_SDRAM 6

BE(3:0)_DQM_N(3:0) 11 2 ns CLK_SDRAM 6

CAS_SDRAM_N 11 2 ns CLK_SDRAM 5

RAS_SDRAM_N 11 2 ns CLK_SDRAM 5

WE_SDRAM_N 11 2 ns CLK_SDRAM 5

CS_SDRAM_N 11 2 ns CLK_SDRAM 5

AD(31:0) 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

CBE_N(3:0) 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

PAR 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

SERR_N 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

PERR_N 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

STOP_N 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

DEVSEL_N 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

TRDY_N 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

IRDY_N 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

FRAME_N 7/3 0 11/6 2 /1 ns PCI_CLK 1, 7

IDSEL 7/3 0 11/6 2/1 ns PCI_CLK 1, 7

GNT_N 10/5 0 ns PCI_CLK 1, 7

REQ_N 12/6 2/1 ns PCI_CLK 1

TRACESYNC Tc - 3 2 ns TRACECLK 3, 4

PIPESTA(2:0) Tc - 3 2 ns TRACECLK 3, 4

TRACEPKT(7:0) Tc - 3 2 ns TRACECLK 3, 4

Notes: 1. Timing parameters are given for 33 MHz and 66 MHz PCI clock frequency (<for 33 MHz> / <for

66 MHz>). The available frequencies are between 0 - 33 MHz, if M66_EN is pulled to VDD and

between 33 - 66 MHz, if M66_EN is pulled to GND.

2. Ethernet Signals in MII Mode and in RMII corresponding to the Ethernet mode of the ERTEC 400

(Available are 2 Port-MII or 4 Por t-RMII).

3. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising

and the su bs equent fallin g ed ge of TR ACECL K ; if th e tr ac e i nte rface i s o perated i n ful l r ate mode, Tc

corresponds to a full period of the trace clock TRACECLK.

4. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 10 pF

load.

5. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 30 pF

load.

6. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 50 pF

load.

7. Minimum hold time for 33 MHz PCI is measured at 10 pF and maximum valid delay is measured at

50 pF; minimum hold time for 66 MHz PCI is measured at 10 pF and maximum valid delay is mea-

sured at 40 pF load.

34 Data Sheet A17813EE2V0DS00

µPD800232

MDIO 10 10 30 10 ns MDC 6

RXD(3:0) 4 1 ns RX_CLK 2

RX_DV 4 1 ns RX_CLK 2

RX_ER 4 1 ns RX_CLK 2

TXD (3:0) 14 2 ns TX_CLK 2, 5

TX_E N 14 2 ns TX_CLK 2, 5

TX_E R 14 2 ns TX_CLK 2, 5

RXD(1:0) 4 1 ns REF_CLK 2

CRS_DV 4 1 ns REF_CLK 2

RX_ER 4 1 ns REF_CLK 2

TXD (1:0) 13 2 ns REF_CLK 2, 5

TX_EN 13 2 ns REF_CLK 2, 5

Notes: 1. Timing parameters are given for 33 MHz and 66 MHz PCI clock frequency (<for 33 MHz> / <for

66 MHz>). The available frequencies are between 0 - 33 MHz, if M66_EN is pulled to VDD and

between 33 - 66 MHz, if M66_EN is pulled to GND.

2. Ethernet Signals in MII Mode and in RMII corresponding to the Ethernet mode of the ERTEC 400

(Available are 2 Por t-MII or 4 Po rt-RMII).

3. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising

and the s ubs eq uen t fa lli ng e dge of TRACECLK; if the tra ce inte rfa ce is opera ted in fu ll r ate mode , Tc

corresponds to a full period of the trace clock TRACECLK.

4. Minimum ho ld time is measure d with 10 pF load a nd maximum valid de lay is me asured wit h 10 pF

load.

5. Minimum ho ld time is measure d with 10 pF load a nd maximum valid de lay is me asured wit h 30 pF

load.

6. Minimum ho ld time is measure d with 10 pF load a nd maximum valid de lay is me asured wit h 50 pF

load.

7. Minimum hold time for 33 MHz PCI is measured at 10 pF and maximum valid delay is measured at

50 pF; minimum hold time for 66 MHz PCI is measured at 10 pF and maximum valid delay is mea-

sured at 40 pF load.

Table 2-5: I/O Timing Specifications (2/2)

Signal Input Output Unit Clock Notes

Setup time

TIS min. Hold time

TIH min. Valid delay

TOV max. Hold time

TOHmin.

Data Sheet A17813EE2V0DS00

µPD800232

Figure 2-2: Input Setup and Hold Waveforms

Figure 2-3: Output Delay Waveforms

Valid

Clock

Inputs

TISmin. TIHmin.

Valid

Clock

Outputs

Valid

High (Drive)

Low (Drive)

Float (High-Z)

max.

min.

36 Data Sheet A17813EE2V0DS00

µPD800232

2.4.3 LBU timing specifications

Remarks: 1. The polarity of the LBU_RDY_N signal can be configured using the LBU_POL_RDY sig-

nal. LBU_RDY_N must be pulled to its "r eady" l evel by an exter nal pul l-down or pul l-up

resistor.

LBU_POL_RDY = 0bLBU_RDY_N active low use external pull-down resistor

LBU_POL_RDY = 1bLBU_RDY_N active high use external pull-up resistor

2. The LBU_CFG signal is us ed to s ele ct acc es s co ntrol thr oug h separate rea d/wr i te l ine s

or a common read/write line.

LBU_CFG = 0buse separate read/write lines LBU_RD_N and LBU_WR_N

LBU_CFG = 1buse common read/write line LBU_WR_N

In case of a com mon read/writ e line, LBU_WR_N must be high for a read access and

low for a write access. The unused LBU_RD_N input must then be pulled to inactive

(high) level by an external pull-up resistor.

3. ERTEC 400 responds to a read or write access by first driving LBU_RDY_N to "not

ready" level. Then LBU_RDY_N is driven to "ready" lev el f or tRAP

.. The length of the "not

ready" phas e of LBU_RDY_N varies strong ly on the inter nal state s of ERTEC 400 a nd

the currently ongoing internal communication processes. Therefore no upper limit for

the length of the "not ready" period is specified.

4. ERTEC 400 has two LBU chip select inputs; one for access to the page configuration

registe rs (LBU_CS_ R_N) and one to acce ss to the ERTEC 400 memor y addes s space

(LBU_CS_M_ N). Only one of the se ch ip sel ect sign als may be active at a tim e and it i s

not allowed to change the chip select during the complete access.

Data Sheet A17813EE2V0DS00

µPD800232

(1) LBU Read from ERTEC 400 with Separate Read/Write line (LBU_RDY_N active low)

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-4: LBU Read from ERTEC 400 with Sepa rate Read/Write line

Table 2-6: LBU Read from ERTEC 400 with Separate Read/Write line

Parameter Symbol Condition MIN. MAX. Unit

Chip select asserted to read pulse

asse rted delay tCSRS -0-ns

Address valid to read pulse asser ted

setup time tARS -0-ns

Read pulse asserted to ready enabled

delay tRRE - 5 12 ns

Read pulse asserted to data enable

delay tRDE - 5 12 ns

Ready active pulse width tRAP -1723ns

Ready asserted to data valid delay tRTD --5ns

Read pulse deasserted to chip select

deasserted delay tRCSH -0-ns

Address valid to read pulse deasserted

hold time tRAH -0-ns

Data valid/enabled to read pulse deas-

serted hold time tRDH - 0 12 ns

Read recovery time tRR -25-ns

LBU_CS_R_N/

LBU_CS_M_N

LBU_RD_N

LBU_AB(20:0)/

LBU_SEG(1:0)/

LBU_BE(1:0)_N

LBU_RDY_N

LBU_DB(15:0)

tCSRS

tARS

tRRE

tRDE

tRAP

tRTD

tRDH

tRAH

tRR

tRCSH

38 Data Sheet A17813EE2V0DS00

µPD800232

(2) LBU Write to ERTEC 400 with separate Read/Write line (LBU_RDY_N active low)

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-5: LBU Write to ERTEC 400 with Separate Read/Write line

Table 2-7: LBU Write to ERTEC 400 with Separate Read/Write line

Parameter Symbol Condition MIN. MAX. Unit

Chip select asserted to write pulse

asserted delay tCSWS -0-ns

Address valid to write pulse asserted

setup time tAWS -0-ns

Write pulse asserted to ready enabled

delay tWRE - 5 12 ns

Write pulse asserted to data valid delay tWDV - - 40 ns

Ready active pulse width tRAP -1723ns

Write pulse deasserted to chip select

deasserted delay tWCSH -0-ns

Address hold time after w rite strobe

deasserted tWAH -0-ns

Ready asserted to write pulse deas-

serted delay tRTW -0-ns

Data hold time after write pulse deas-

serted tWDH -0-ns

Write recove ry time tWR -25-ns

LBU_CS_R_N/

LBU_CD_M_N

LBU_WR_N

LBU_AB(20:0)/

LBU_SEG(1:0)

LBU_BE(1:0)_N

LBU_RDY_N

LBU_DB(15:0)

CSWS

AWS

WRE

WDV

RAP

RTW

WAH

WDH

WCSH

Data Sheet A17813EE2V0DS00

µPD800232

(3) LBU Read from ERTEC 400 with Common Read/Write line (LBU_RDY_N active low)

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-6: LBU Read from ERTEC 4 00 with Common Read/Write line

Table 2-8: LBU Read from ERTEC 400 with Common Read/Write line

Parameter Symbol Condition MIN. MAX. Unit

Write signal deasserted to chip select

asserted setup time tWCS -2-ns

Address valid t o chip select asserted

setup time tACS -0-ns

Chip select asserted to ready enabled

delay tCRE - 5 12 ns

Chip select asserted to data enable

delay tCDE - 5 12 ns

Ready active pulse width tRAP -1723ns

Ready asserted to data valid delay tRTD --5ns

Write signal inactive to chip select deas-

serted hold time tCWH -0-ns

Address valid to chip select deasserted

hold time tCAH -0-ns

Data valid/enabled to chip select deas-

serted hold time tCDH - 0 12 ns

Read recovery time tRR -25-ns

LBU_CS_R_N/

LBU_CS_M_N

LBU_W R_N

LBU_AB(20:0)/

LBU_SEG(1:0)/

LBU_BE(1:0)_N

LBU_RDY_N

LBU_DB(15:0)

tACS

tWCS

tCRE

tCDE

tRAP

tRTD

tCDH

tCAH

tCWH

tRR

40 Data Sheet A17813EE2V0DS00

µPD800232

(4) LBU Write to ERTEC 400 with Common Read/Write line (LBU_RDY_N active low)

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-7: LBU Write to ERTEC 400 with Common Read/Write line

Table 2-9: LBU Write to ERTEC 400 with Common Read/Write line

Parameter Symbol Condition MIN. MAX. Unit

Write signal asserted to chip select

setup time tWCS -2-ns

Address valid to chip select asserted

setup time tACS -0-ns

Chip select asserted to ready enabled

delay tCRE - 5 12 ns

Chip select asserted to data valid delay tCDV - - 40 ns

Ready active pulse width tRAP -1723ns

Write signal deasserted to chip select

deasserted hold time tCWH -0-ns

Address hold time after chip select deas-

serted tCAH -0-ns

Ready asserted to chip select deas-

serted delay tRTC -0-ns

Data valid/enabled to chip select deas-

serted hold time tCDH -0-ns

Write recove ry time tWR -25-ns

LBU_CS_R_N/

LBU_CS_M_N

LBU_WR_N

LBU_AB(20:0)/

LBU_SEG(1:0)/

LBU_BE(1:0)_N

LBU_RDY_N

LBU_DB(15:0)

tWCS

tACS

tCRE

tCDV

tRTC

tRAP

tWR

tCWH

tCAH

tCDH

Data Sheet A17813EE2V0DS00

µPD800232

2.4.4 SPI timing specifications

Remarks: 1. Please note, that different serial clock frequency ranges for SPI slave and master

modes are given in Table 2-4.

2. Timing diagrams are shown for TI-f ormat only. Other transfer f ormats can be configured,

however the AC-timing parameters (setup/hold times, delays) remain in principle

unchanged.

3. Not every external SPI device, that is connected to ERTEC 400, requires usage of all

available SPI signals.

(1) SPI interface configured to slave mode

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-8: SPI Timing in Slave Mode (TI-format Example)

Table 2-10: SPI Timing Specifications (slav e mode)

Parameter Symbol Condition MIN. MAX. Unit

SSPRXD setup time tSSPRXDS -20-ns

SSPRXD hold time tSSPRXDH -60-ns

SFRMIN setup time tSFRMINS -40-ns

SFRMIN hold time tSFRMINH -20-ns

SSPTXD delay tSSPTXDD - - 40 ns

SSPOE delay tSSPOED - - 40 ns

42 Data Sheet A17813EE2V0DS00

µPD800232

(2) SPI interface configured to master mode

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-9: SPI Timing in Master Mode (TI-format Example)

Table 2-11: SPI Timing Specifications (master mode)

Parameter Symbol Condition MIN. MAX. Unit

SSPRXD setup time tSSPRXDS - 12.4 - ns

SSPRXD hold time tSSPRXDH -0-ns

SFRMOUT delay tSFRMOUTD --0.70.4ns

SSPTXD delay tSSPTXDD --0.80.4ns

SSPOE delay tSSPOED -0.22.3ns

SSPCTLOE delay tSSPCTLOED -0.12.3ns

Data Sheet A17813EE2V0DS00

µPD800232

2.4.5 Power-up sequence

Figure 2-10: Power-Up Sequence Timing Diagram

VDD

RESET_N

CLKP_A

min. 35 µs

Unstable min. 2 µs

44 Data Sheet A17813EE2V0DS00

µPD800232

2.4.6 Reset timing

Figure 2-11: Reset Timing Diagram

CLKP_A

(12.5 MHz)

CLK_50

(internal signal)

~8196 TCLKP_A ~16 TCLK_50

CLK_100/CLK_ARM

(internal signal)

RESET_N

XRES_ERTEC/

XRES_CNTRL

(internal signal)

CLK_PCI

RESET_N

RES_PCI_N

Data Sheet A17813EE2V0DS00

µPD800232

3. Package Drawing

Figure 3-1: Package Drawing

304-PIN PLASTIC FBGA (19x19)

SwB

SwA ZD

INDEX MARK

BDF

CEG

HKM

JLN

PTV

RUW

11 12

1314

15 16

17 18

19 20

21 22

xbAB

y1 S

ITEM DIMENSIONS

19.00 0.10

1.13

0.20

1.480.10

0.80

0.35 0.06

(UNIT:mm)

0.08

0.10

0.20

1.10

P304F1-80-HN2

b0.50 0.05

0.10

46 Data Sheet A17813EE2V0DS00

µPD800232

4. Recommended Soldering Conditions

Solder this product under the following recommended conditions.

For details of the recommended soldering conditions, refer to the information document

Semiconductor Device Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended please consult NEC.

•for µPD800232F1-014-HN2-A (lead-free device)

Note: The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been

opened. After that, prebaking is necessary at 125 °C for 10 to 72 hours.

Table 4-1: Soldering Conditions for Lead-free Device

Soldering Method Soldering Condition Symbol of Recommended Soldering

Condition

Infrared reflow

Package peak temperature: 260°C,

Time: 60 seconds max. (220°C min.),

Number of times: 3 max.,

Number of days: 7 Note

IR60-107-3

Data Sheet A17813EE2V0DS00

µPD800232

48 Data Sheet A17 813 EE 2V0 DS00

µPD800232

All other product, brand, or trade names used in this publication are the trademarks

or registered trademarks of their respective trademark owners.

Product specifications are subject to change without notice. To ensure that you have the latest

product data, please contact your local NEC Electronics sales office.

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between VIL (MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

Data Sheet A17813EE2V0DS00

µPD800232

The information in this document is current as of November, 2009. The information is subject

to change without notice. For actual design-in, refer to the latest publications of NEC Electronics

data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics

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NEC Electronics sales representative for availability and additional information.

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(Note)

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(2) "NEC Electronics products" means any product developed or manufactured by or for

NEC Electronics (as defined above).

50 Data Sheet A17 813 EE 2V0 DS00

µPD800232

ona

orma

Some information contained in this document may vary from country to country. Before using any

NEC product in your application, please contact the NEC ofﬁce in your country to obtain a list of

authorized representatives and distributors. They will verify:

• Device availability

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In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also

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