MM74HC125, MM74HC126 — 3-STATE Quad Buffers
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0
February 2008
MM74HC125, MM74HC126
3-STATE Quad Buffers
Features
■
Typical propagation delay: 13ns
■
Wide operating voltage range: 2V–6V
■
Low input current: 1µA maximum
■
Low quiescent current: 80µA maximum (74HC)
■
Fanout of 15 LS-TTL loads
General Description
The MM74HC125 and MM74HC126 are general pur-
pose 3-STATE high speed non-inverting buffers utilizing
advanced silicon-gate CMOS technology. They have
high drive current outputs which enable high speed oper-
ation even when driving large bus capacitances. These
circuits possess the low power dissipation of CMOS
circuitry, yet have speeds comparable to low power
Schottky TTL circuits. Both circuits are capable of driving
up to 15 low power Schottky inputs.
The MM74HC125 require the 3-STATE control input C to
be taken high to put the output into the high impedance
condition, whereas the MM74HC126 require the control
input to be low to put the output into high impedance.
All inputs are protected from damage due to static
discharge by diodes to V
CC
and ground.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
MM74HC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
MM74HC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
MM74HC125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC126M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
MM74HC126SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC126MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
MM74HC126N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 2
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View (MM74HC125) Top View (MM74HC126)
Truth Tables
MM74HC125 MM74HC126
Inputs Output
ACY
HLH
LLL
XHZ
Inputs Output
ACY
HHH
LHL
XLZ
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 3
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5 to +7.0V
V
IN
DC Input Voltage –1.5 to V
CC
+1.5V
V
OUT
DC Output Voltage –0.5 to V
CC
+0.5V
I
IK
, I
OK
Clamp Diode Current ±20mA
I
OUT
DC Output Current, per pin 35mA
I
CC
DC V
CC
or GND Current, per pin ±70mA
T
STG
Storage Temperature Range –65°C to +150°C
P
D
Power Dissipation
Note 2 600mW
S.O. Package only 500mW
T
L
Lead Temperature (Soldering 10 seconds) 260°C
Symbol Parameter Min. Max. Units
V
CC
Supply Voltage 2 6 V
V
IN
, V
OUT
DC Input or Output Voltage 0 V
CC
V
T
A
Operating Temperature Range –40 +85 °C
t
r
, t
f
Input Rise or Fall Times
V
CC
=
2.0V 1000 ns
V
CC
=
4.5V 500 ns
V
CC
=
6.0V 400 ns
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 4
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
DC Electrical Characteristics
(3)
Note:
3. For a power supply of 5V ±10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V
respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current (I
IN
, I
CC
, and I
OZ
) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
Symbol Parameter Conditions V
CC
(V)
T
A
=
25°C
T
A
=
–40°C
to 85°C
T
A
=
–40°C
to 125°C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH
Level Input
Voltage
2.0 1.5 1.5 1.5 V
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
IL
Maximum LOW
Level Input
Voltage
2.0 0.5 0.5 0.5 V
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
V
OH
Minimum HIGH
Level Output
Voltage
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
2.0 2.0 1.9 1.9 1.9 V
4.5 4.5 4.4 4.4 4.4
6.0 6.0 5.9 5.9 5.9
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
6.0mA
4.5 4.2 3.98 3.84 3.7
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
7.8mA
6.0 5.7 5.48 5.34 5.2
V
OL
Maximum LOW
Level Output
Voltage
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
2.0 0 0.1 0.1 0.1 V
4.5 0 0.1 0.1 0.1
6.0 0 0.1 0.1 0.1
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
6.0mA
4.5 0.2 0.26 0.33 0.4
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
7.8mA
6.0 0.2 0.26 0.33 0.4
I
OZ
Maximum
3-STATE Output
Leakage Current
V
IN
=
V
IH
or V
IL
,
V
OUT
=
V
CC
or GND,
C
n
=
Disabled
6.0 ±0.5 ±5 ±10 µA
I
IN
Maximum Input
Current
V
IN
=
V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0 µA
I
CC
Maximum
Quiescent
Supply Current
V
IN
=
V
CC
or GND,
I
OUT
=
0µA
6.0 8.0 80 160 µA
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 5
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25°C, C
L
=
45pF, t
r
=
t
f
=
6ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified)
Note:
4. CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
Symbol Parameter Conditions Typ.
Guaranteed
Limit Units
tPHL, tPLH Maximum Propagation Delay Time 13 18 ns
tPZH Maximum Output Enable Time to HIGH
Level
RL = 1kΩ13 25 ns
tPHZ Maximum Output Disable Time from
HIGH Level
RL = 1kΩ, CL = 5pF 17 25 ns
tPZL Maximum Output Enable Time to LOW
Level
RL = 1kΩ18 25 ns
tPLZ Maximum Output Disable Time from
LOW Level
RL = 1kΩ, CL = 5pF 13 25 ns
Symbol Parameter VCC (V) Conditions
TA = 25°C
TA = –40°C
to 85°C
TA = –40°C
to 125°C
UnitsTyp. Guaranteed Limits
tPHL, tPLH Maximum Propagation
Delay Time
2.0 40 100 125 150 ns
4.5 14 20 25 30
6.0 12 17 21 25
tPLH, tPHL Maximum Propagation
Delay Time
2.0 CL = 150pF 35 130 163 195 ns
4.5 14 26 33 39
6.0 12 22 28 39
tPZH, tPZL Maximum Output
Enable Time
2.0 RL = 1kΩ25 125 156 188 ns
4.5 14 25 31 38
6.0 12 21 26 31
tPHZ, tPLZ Maximum Output
Disable Time
2.0 RL = 1kΩ25 125 156 188 ns
4.5 14 25 31 38
6.0 12 21 26 31
tPZL, tPZH Maximum Output
Enable Time
2.0 CL = 150pF,
RL = 1kΩ
35 140 175 210 ns
4.5 15 28 35 42
6.0 13 24 30 36
tTLH, tTHL Maximum Output
Rise and Fall Time
2.0V CL = 50pF 30 60 75 90 ns
4.5V 7 12 15 18
6.0V 6 10 13 15
CIN Input Capacitance 5 10 10 10 pF
COUT Output Capacitance
Outputs
15 20 20 20 pF
CPD Power Dissipation
Capacitance
(per gate)(4)
Enabled 45 pF
Disabled 6
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 6
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 7
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 8
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 9
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
14 8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A)
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30 5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35 2.54
3.81
3.17 8.82
(1.74)
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC125, MM74HC126 Rev. 1.3.0 10
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™
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®
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As used herein:
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which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
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This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
