SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree(1)
DESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
DHigh Slew Rate . . . 10.5 V/µs Typ
DHigh-Gain Bandwidth . . . 5.1 MHz Typ
DSupply Voltage Range 2.5 V to 5.5 V
DRail-to-Rail Output
D360 µV Input Offset Voltage
DLow Distortion Driving 600-Ω
0.005% THD+N
D1 mA Supply Current (Per Channel)
D17 nV/√Hz Input Noise Voltage
D2 pA Input Bias Current
DCharacterized From TA = −55°C to 125°C
DMicropower Shutdown Mode ...I
DD < 1 µA
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description
The TLV277x CMOS operational amplifier family combines high slew rate and bandwidth, rail-to-rail output
swing, high output drive, and excellent dc precision. The device provides 10.5 V/µs of slew rate and 5.1 MHz
of bandwidth while only consuming 1 mA of supply current per channel. This ac performance is much higher
than current competitive CMOS amplifiers. The rail-to-rail output swing and high output drive make these
devices a good choice for driving the analog input or reference of analog-to-digital converters (ADCs) . These
devices also have low distortion while driving a 600-Ω load for use in telecom systems.
These amplifiers have a 360-µV input offset voltage, a 17 nV/√Hz input noise voltage, and a 2-pA input bias
current for measurement, medical, and industrial applications. The TLV277x family is also specified across an
extended temperature range (−55°C to 125°C), making it useful for military and avionics systems.
These devices operate from a 2.5-V to 5.5-V single supply voltage and are characterized at 2.7 V and 5 V. The
single-supply operation and low power consumption make these devices a good solution for portable
applications. The following table lists the packages available.
FAMILY PACKAGE TABLE
DEVICE
NUMBER
OF
PACKAGE
TYPES
SHUTDOWN
UNIVERSAL
EVM BOARD
DEVICE
OF
CHANNELS SOIC TSSOP
SHUTDOWN
EVM BOARD
TLV2770 1 8 — Yes
TLV2771 1 8 — —
See the EVM
TLV2772 2 8 8 — See the EVM
Selection Guide
TLV2773 2 14 — Yes
Selection Guide
(SLOU060)
TLV2774 4 14 14 —
(SLOU060)
TLV2775 4 16 16 Yes
Copyright 2007 Texas Instruments Incorporated
!"#$% !%&% '
%()#&% !"))$% & ( *"+,!&% &$ )"! !%()#
*$!(!&% *$) $ $)# ( $& %)"#$% &%&) -&))&%.
)"!% *)!$%/ $ % %$!$&),. %!,"$ $%/ ( &,,
*&)&#$$)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS†
DEVICE VDD
(V) BW
(MHz) SLEW RATE
(V/µs) IDD (per channel)
(µA) RAIL-TO-RAIL
TLV277X 2.5 to 6 5.1 10.5 1000 O
TLV247X 2.7 to 6 2.8 1.5 600 I/O
TLV245X 2.7 to 6 0.22 0.11 23 I/O
TLV246X 2.7 to 6 6.4 1.6 550 I/O
†All specifications measured at 5 V.
ORDERING INFORMATION†
TAVIOMAX
AT 25°C
(mV) PACKAGE‡ORDERABLE
PART NUMBER TOP SIDE
MARKING
2.5 SOIC (D) Tape and reel TLV2770MDREP§
1.6 SOIC (D) Tape and reel TLV2770AMDREP§
2.5 SOIC (D) Tape and reel TLV2771MDREP§
1.6 SOIC (D) Tape and reel TLV2771AMDREP§
2.5
SOIC (D) Tape and reel TLV2772MDREP§
2.5 TSSOP (PW) Tape and reel TLV2772MPWREP§
1.6
SOIC (D) Tape and reel TLV2772AMDREP 2772AE
1.6 TSSOP (PW) Tape and reel TLV2772AMPWREP§
−55°C to 125°C
2.5 SOIC (D) Tape and reel TLV2773MDREP§
−55°C to 125°C1.6 SOIC (D) Tape and reel TLV2773AMDREP§
2.7
SOIC (D) Tape and reel TLV2774MDREP 2774EP
2.7 TSSOP (PW) Tape and reel TLV2774MPWREP§
2.1
SOIC (D) Tape and reel TLV2774AMDREP 2774AEP
2.1 TSSOP (PW) Tape and reel TLV2774AMPWREP§
2.7
SOIC (D) Tape and reel TLV2775MDREP§
2.7 TSSOP(PW) Tape and reel TLV2775MPWREP§
2.1
SOIC (D) Tape and reel TLV2775AMDREP§
2.1 TSSOP (PW) Tape and reel TLV2775AMPWREP§
†For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/packaging.
§Product Preview
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV277x PACKAGE PINOUTS
NC − No internal connection
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV2772
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD
OUT
NC
TLV2770†
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD
OUT
NC
TLV2771†
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2773†
D PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV2774
D OR PW PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1/2SHDN
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
(TOP VIEW)
TLV2775†
D OR PW PACKAGE
†This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input, see Note 1) −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (any input) ±4 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current (at or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below GND − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
QJC (°C/W) QJA (°C/W, 0 AIR FLOW)
PACKAGE
HIGH K LOW K HIGH K LOW K
D(8) 39.4 42.4 97.1 165.5
D(14) 51.5 53.7 86.2 133.5
D(16) 36.9 38.4 73.1 111.6
PW(8) 65.1 69.4 149.4 230.5
PW(14) 45.8 46.6 111.7 131.4
PW(16) 33.6 35 108.4 147.0
NOTE 4: Thermal resistances are not production tested and are for informational purposes only.
recommended operating conditions
M SUFFIX
UNIT
MIN MAX
UNIT
Supply voltage, VDD 2.5 6 V
Input voltage range, VIGND VDD+ −1.3 V
Common-mode input voltage, VIC GND VDD+ −1.3 V
Operating free-air temperature, TA−55 125 °C
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TJ − Junction Temperature − °C
Time-to-Fail − Hrs
WIREBOND LIFE
vs
JUNCTION TEMPERATURE
80°C, 17M Hrs
100°C, 1.7M Hrs
120°C, 210k Hrs
140°C, 33k Hrs
1k
100k
100M
10k
1M
10M
10080 90 110 120 130 140 150
90°C, 5.2M Hrs
110°C, 580k Hrs
130°C, 82k Hrs
Figure 1. Wirebond Life Estimation
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV277xM TLV277xAM
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
V = 1.35 V,
TLV2770/1/2/3
25°C 0.44 2.5 0.44 1.6
VIO
Input offset voltage
VDD = ±1.35 V,
VIC = 0, VO = 0,
TLV2770/1/2/3
Full range 2.7 1.9
mV
VIO Input offset voltage
DD
V
IC
= 0, V
O
= 0,
RS = 50 Ω
TLV2774/5
25°C 0.8 2.7 0.8 2.1 mV
RS = 50 Ω
TLV2774/5 Full range 3.0 2.4
VIO
Temperature
coefficient of input
VDD = ±1.35 V,
VIC = 0, VO = 0,
25°C
to
2
2
V/°C
αVIO
coefficient of input
offset voltage
DD
V
IC
= 0, V
O
= 0,
R
S
= 50 Ω
to
125°C2 2 µV/°C
VDD = ±1.35 V,
25°C 1 60 1 60
I
IO
Input offset current
VDD = ±1.35 V,
V
IC
= 0, V
O
= 0,
R = 50
TL2770/1/2/3
Full range
125 125 pA
IIO
Input offset current
VIC = 0, VO = 0,
RS = 50 ΩTLV2774/5 Full range 200 200
pA
VDD = ±1.35 V,
25°C 2 60 2 60
I
IB
Input bias current
VDD = ±1.35 V,
V
IC
= 0, V
O
= 0,
R = 50
TLV2770/1/2/3
Full range
350 350 pA
IIB
Input bias current
VIC = 0, VO = 0,
RS = 50 ΩTLV2774/5 Full range 500 500
pA
0
−0.3
0
−0.3
25
°
C
0
to
−0.3
to
0
to
−0.3
to
VICR
Common-mode
CMRR > 60 dB,
RS = 50 Ω
25 C
to
1.4
to
1.7
to
1.4
to
1.7
V
VICR
Common-mode
input voltage range CMRR > 60 dB, RS = 50 Ω
0
−0.3
0
−0.3
V
input voltage range
Full range
0
to
−0.3
to
0
to
−0.3
to
Full range
to
1.4
to
1.7
to
1.4
to
1.7
IOH = −0.675 mA
25°C 2.6 2.6
VOH
High-level output
IOH = −0.675 mA Full range 2.45 2.45
V
VOH
High-level output
voltage
IOH = −2.2 mA
25°C 2.4 2.4 V
voltage
IOH = −2.2 mA Full range 2.1 2.1
VIC = 1.35 V,
IOL = 0.675 mA
25°C 0.1 0.1
VOL
Low-level output
VIC = 1.35 V, IOL = 0.675 mA Full range 0.2 0.2
V
VOL
Low-level output
voltage
VIC = 1.35 V,
IOL = 2.2 mA
25°C 0.21 0.21 V
voltage
VIC = 1.35 V, IOL = 2.2 mA Full range 0.6 0.6
AVD
Large-signal
differential voltage
VIC = 1.35 V,
RL = 10 k
Ω
,
‡25°C 20 380 20 380
V/mV
AVD
differential voltage
amplification
VIC = 1.35 V,
VO = 0.6 V to 2.1 V
RL = 10 kΩ,‡
Full range 13 13 V/mV
ri(d) Differential input
resistance 25°C 1012 1012 Ω
ci(c) Common-mode
input capacitance f = 10 kHz, 25°C 8 8 pF
zoClosed-loop
output impedance f = 100 kHz, AV = 10 25°C 25 25 Ω
CMRR
Common-mode
VIC = VICR (min),
VO = 1.5 V,
25°C 60 84 60 84
dB
CMRR
Common-mode
rejection ratio
VIC = VICR (min),
RS = 50 Ω
VO = 1.5 V,
Full range 60 82 60 82 dB
kSVR
Supply voltage
rejection ratio
VDD = 2.7 V to 5 V,
VIC = VDD/2,
25°C 70 89 70 89
dB
kSVR
rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 5 V,
No load
VIC = VDD/2,
Full range 70 84 70 84 dB
IDD
Supply current
VO = 1.5 V,
No load
25°C 1 2 1 2
mA
I
DD
Supply current
(per channel)
V
O
= 1.5 V,
No load
Full range 2 2
mA
†Full range is −55°C to 125°C for M level part.
‡Referenced to 1.35 V
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV277xM TLV277xAM
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
VO(PP) = 0.8 V,
CL = 100 pF,
25°C5 9 5 9
SR Slew rate at unity gain VO(PP) = 0.8 V
,
RL = 10 kΩCL = 100 pF
,
Full
range 4.7 6 4.7 6 V/µs
Vn
Equivalent input
f = 1 kHz
25°C
21 21
nV/√Hz
Vn
Equivalent input
noise voltage f = 10 kHz 25°C17 17
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz
25°C
0.33 0.33 µV
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C0.86 0.86 µV
InEquivalent input
noise current f = 100 Hz 25°C 0.6 0.6 fA/√Hz
Total harmonic
RL = 600 Ω,
AV = 1 0.0085% 0.0085%
THD + N Total harmonic
distortion plus noise
RL = 600 Ω,
f = 1 kHz
AV = 10 25°C0.025% 0.025%
THD + N
distortion plus noise
f = 1 kHz
AV = 100
25 C
0.12% 0.12%
Gain-bandwidth
product f = 10 kHz,
CL = 100 pF RL = 600 Ω,25°C 4.8 4.8 MHz
ts
Settling time
AV = −1,
Step = 0.85 V to
1.85 V,
0.1%
25°C
0.186 0.186
s
tsSettling time
1.85 V,
RL = 600 Ω,
C
L
= 100 pF 0.01% 25°C3.92 3.92
µs
φmPhase margin at
unity gain R
L
= 600 Ω, C
L
= 100 pF 25°C 46°46°
Gain margin
RL = 600 Ω,
CL = 100 pF
25°C 12 12 dB
†Full range is −55°C to 125°C for M level part.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV277xM TLV277xAM
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
V = 2.5 V,
TLV2770/1/2/3
25°C 0.36 2.5 0.36 1.6
VIO
Input offset voltage
VDD = ±2.5 V,
VIC = 0, VO = 0,
TLV2770/1/2/3 Full range 2.7 1.9
mV
VIO Input offset voltage
V
IC
= 0, V
O
= 0,
RS = 50 Ω
TLV2774/5
25°C 0.8 2.5 0.8 2.1 mV
RS = 50 Ω
TLV2774/5 Full range 2.7 2.4
VIO
Temperature
coefficient of input
VDD = ±2.5 V,
VIC = 0, VO = 0,
25°C
to
2
2
V/°C
αVIO
coefficient of input
offset voltage
V
IC
= 0, V
O
= 0,
R
S
= 50 Ω
to
125°C2 2 µV/°C
VDD =
±
2.5 V,
25°C 1 60 1 60
I
IO
Input offset current
VDD = ±2.5 V,
V
IC
= 0, V
O
= 0, TLV2770/1/2/3
Full range
125 125 pA
IIO
Input offset current
VIC = 0, VO = 0,
RS = 50 ΩTLV2774/5 Full range 200 200
pA
VDD =
±
2.5 V,
25°C 2 60 2 60
I
IB
Input bias current
VDD = ±2.5 V,
V
IC
= 0, V
O
= 0, TLV2770/1/2/3
Full range
350 350 pA
IIB
Input bias current
VIC = 0, VO = 0,
RS = 50 ΩTLV2774/5 Full range 500 500
pA
0
−0.3
0
−0.3
25
°
C
0
to
−0.3
to
0
to
−0.3
to
VICR
Common-mode
CMRR > 60 dB,
RS = 50 Ω
25 C
to
3.7
to
3.8
to
3.7
to
3.8
V
VICR
Common-mode
input voltage range CMRR > 60 dB, RS = 50 Ω
0
−0.3
0
−0.3
V
input voltage range
Full range
0
to
−0.3
to
0
to
−0.3
to
Full range
to
3.7
to
3.8
to
3.7
to
3.8
IOH = −1.3 mA
25°C 4.9 4.9
VOH
High-level output
IOH = −1.3 mA Full range 4.8 4.8
V
VOH
High-level output
voltage
IOH = −4.2 mA
25°C 4.7 4.7 V
voltage
IOH = −4.2 mA Full range 4.4 4.4
VIC = 2.5 V,
IOL = 1.3 mA
25°C 0.1 0.1
VOL
Low-level output
VIC = 2.5 V, IOL = 1.3 mA Full range 0.2 0.2
V
VOL
Low-level output
voltage
VIC = 2.5 V,
IOL = 4.2 mA
25°C 0.21 0.21 V
voltage
VIC = 2.5 V, IOL = 4.2 mA Full range 0.6 0.6
AVD
Large-signal
differential voltage
VIC = 2.5 V,
RL = 10 k
Ω
,
‡25°C 20 450 20 450
V/mV
AVD
differential voltage
amplification
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 10 kΩ,‡
Full range 13 13 V/mV
ri(d) Differential input
resistance 25°C 1012 1012 Ω
ci(c) Common-mode
input capacitance f = 10 kHz, 25°C 8 8 pF
zoClosed-loop
output impedance f = 100 kHz, AV = 10 25°C 20 20 Ω
CMRR
Common-mode
VIC = VICR (min),
VO = 3.7 V,
25°C 60 96 60 96
dB
CMRR
Common-mode
rejection ratio
VIC = VICR (min),
RS = 50 Ω
VO = 3.7 V,
Full range 60 93 60 93 dB
kSVR
Supply voltage
rejection ratio
VDD = 2.7 V to 5 V,
VIC = VDD/2,
25°C 70 89 70 89
dB
kSVR
rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 5 V,
No load
VIC = VDD/2,
Full range 70 84 70 84 dB
IDD
Supply current
VO = 1.5 V,
No load
25°C 1 2 1 2
mA
I
DD
Supply current
(per channel)
V
O
= 1.5 V,
No load
Full range 2 2
mA
†Full range is −55°C to 125°C for M level part.
‡Referenced to 2.5 V
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV277xM TLV2772xAM
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
VO(PP) = 1.5 V,
CL = 100 pF,
25°C5 10.5 5 10.5
SR Slew rate at unity gain VO(PP) = 1.5 V
,
RL = 10 kΩCL = 100 pF
,
Full
range 4.7 6 4.7 6 V/µs
Vn
Equivalent input
f = 1 kHz
25°C
17 17
nV/√Hz
Vn
Equivalent input
noise voltage f = 10 kHz 25°C12 12
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz
25°C
0.33 0.33 µV
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C0.86 0.86 µV
InEquivalent input
noise current f = 100 Hz 25°C 0.6 0.6 fA/√Hz
Total harmonic
RL = 600 Ω,
AV = 1 0.005% 0.005%
THD + N Total harmonic
distortion plus noise
RL = 600 Ω,
f = 1 kHz
AV = 10 25°C0.016% 0.016%
THD + N
distortion plus noise
f = 1 kHz
AV = 100
25 C
0.095% 0.095%
Gain-bandwidth
product f = 10 kHz,
CL = 100 pF RL = 600 Ω,25°C 5.1 5.1 MHz
ts
Settling time
AV = −1,
Step = 1.5 V to
3.5 V,
0.1%
25°C
0.134 0.134
s
tsSettling time
3.5 V,
RL = 600 Ω,
C
L
= 100 pF 0.01% 25°C1.97 1.97
µs
φmPhase margin at unity
gain R
L
= 600 Ω, C
L
= 100 pF 25°C 46°46°
Gain margin
RL = 600 Ω,
CL = 100 pF
25°C 12 12 dB
†Full range is −55°C to 125°C for M level part.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode input voltage
1,2
3,4
VIO Input offset voltage
vs Common-mode input voltage
Distribution
3,4
5,6
IIB/IIO Input bias and input offset currents vs Free-air temperature 7
VOH High-level output voltage vs High-level output current 8,9
VOL Low-level output voltage vs Low-level output current 10,11
VO(PP) Maximum peak-to-peak output voltage vs Frequency 12,13
IOS Short-circuit output current vs Supply voltage
vs Free-air temperature 14
15
VOOutput voltage vs Differential input voltage 16
AVD Large-signal differential voltage amplification and phase margin vs Frequency 17,18
AVD Differential voltage amplification vs Load resistance
vs Free-air temperature 19
20,21
zoOutput impedance vs Frequency 22,23
CMRR Common-mode rejection ratio vs Frequency
vs Free-air temperature 24
25
kSVR Supply-voltage rejection ratio vs Frequency 26,27
IDD Supply current (per channel) vs Supply voltage 28
SR
Slew rate
vs Load capacitance
29
SR Slew rate
vs Load capacitance
vs Free-air temperature
29
30
VOVoltage-follower small-signal pulse response 31,32
VOVoltage-follower large-signal pulse response 33,34
VOInverting small-signal pulse response 35,36
VOInverting large-signal pulse response 37,38
VnEquivalent input noise voltage vs Frequency 39,40
Noise voltage (referred to input) Over a 10 second period 41
THD + N Total harmonic distortion plus noise vs Frequency 42,43
Gain-bandwidth product vs Supply voltage 44
B1Unity-gain bandwidth vs Load capacitance 45
φmPhase margin vs Load capacitance 46
Gain margin vs Load capacitance 47
Amplifier with shutdown pulse turnon/off characteristics 48 − 50
Supply current with shutdown pulse turnon/off characteristics 51 − 53
Shutdown supply current vs Free-air temperature 54
Shutdown forward/reverse isolation vs Frequency 55, 56
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
−2.5
30
20
10
0−2 −1.5 −1 0 0.5
VIO − Input Offset Voltage − mV
−0.5
35
Percentage of Amplifiers − %
25
15
5
1
40 VDD = 2.7 V
RL = 10 kΩ
TA = 25°C
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
1.5 2.52
Figure 3
−2.5
30
20
10
0−2 −1.5 −1 0 0.5
VIO − Input Offset Voltage − mV
−0.5
35
Percentage of Amplifiers − %
25
15
5
1
40 VDD =5 V
RL = 10 kΩ
TA = 25°C
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
1.5 2.52
Figure 4
VDD = 2.7 V
TA = 25°C
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
2
1
0
−1
−2
1.5
0.5
−0.5
−1.5
−1 −0.5 0 0.5 2
VIC − Common-Mode Input Voltage − V
1.51 2.5 3
VIO − Input Offset Voltage − mV
Figure 5
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0
−1
−2
−1 0 0.5
VIC − Common-Mode Input Voltage − V
−0.5
1.5
0.5
−0.5
−1.5
1
2
1.5 2.52 3 3.5 4.54
VDD = 5 V
TA = 25°C
VIO − Input Offset Voltage − mV
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
αVIO − Temperature Coefficient − µV/°C
−6
30
20
10
0−3 0 3 9 126
35
Percentage of Amplifiers − %
25
15
5
VDD = 2.7 V
TA = 25°C to 125°C
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
Figure 7
−6
30
20
10
0−3 0 3 9 12
αVIO − Temperature Coefficient − µV/°C
6
35
Percentage of Amplifiers − %
25
15
5
VDD =5 V
TA = 25°C to 125°C
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
Figure 8
VDD = 5 V
VIC = 0
VO = 0
RS = 50 Ω
INPUT BIAS AND OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0.20
0.10
0
0.15
0.05
−75 −50 −25 0 75
TA − Free-Air Temperature − °C
5025 100 125
IIB and I IO − Input Bias and Input Offset Currents − nA
IIB
IIO
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
2
1
0
2.5
1.5
0.5
0 5 10 15
IOH − High-Level Output Current − mA 2520
VOH− High-Level Output Voltage − V
VDD = 2.7 V
TA = 125°C
TA = −40°C
TA = 25°C
TA = 85°C
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
2
1
001015
IOH − High-Level Output Current − mA
5
3.5
2.5
1.5
0.5
20
4
25 3530 40 45 5550
VDD = 5 V
TA = 25°C
VOH − High-Level Output Voltage − V
4.5
5
TA = −40°C
TA = 85°C
TA = 25°C
TA = 125°C
Figure 11
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
2
1
0
2.5
1.5
0.5
0 5 10 15
IOL − Low-Level Output Current − mA 3020
VOL − Low-Level Output Voltage − V
VDD = 2.7 V
TA = 125°C
25
TA = 85°C
TA = 25°C
TA = −40°C
Figure 12
2
1
0010
IOL − Low-Level Output Current − mA
2.5
1.5
0.5
20
3
30 40 50
VDD = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 125°C
TA = 85°C
TA = −40°C
TA = 25°C
VOL − Low-Level Output Voltage − V
Figure 13
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
3
1
01000
f − Frequency − kHz
5
10000
100
4
RL = 10 kΩ
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
2
VDD = 5 V
1% THD
VDD = 2.7 V
2% THD
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
THD = 5%
RL = 600 Ω
TA = 25°C
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
3
2
1
0
2.5
1.5
0.5
100 f − Frequency − kHz
1000 1000
0
VDD = 5 V
VDD = 2.7 V
5
4
4.5
3.5
− Maximum Peak-to-Peak Output Voltage − V
VO(PP)
Figure 15
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
30
0
−30
−60245
VDD − Supply Voltage − V
3
45
15
−15
−45
6
60
7
VO = VDD /2
VIC = VDD /2
TA = 25°C
IOS − Short-Circuit Output Current − mA
VID = −100 mV
VID = 100 mV
Figure 16
VDD = 5 V
VO = 2.5 V
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
60
20
−20
−60
40
0
−40
−75 −50 −25 0 75
TA − Free-Air Temperature − °C
5025 100 125
IOS − Short-Circuit Output Current − mA
VID = −100 mV
VID = 100 mV
Figure 17
RL = 600 Ω
TA = 25°C
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
4
2
0
5
3
1
−1000 −750 −500 −250 500
VID − Differential Input Voltage − µV
2500 750 1000
VO− Output Voltage − V
VDD = 2.7 V
VDD = 5 V
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
100
60
20
−20
80
40
0
100 f − Frequency − Hz
10k 10M
AVD
Phase
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
− Large-Signal Differential Amplification − dBAVD
m
φ− Phase Margin − degrees
300
180
60
−60
240
120
0
1k 100k 1M
−40 −90
VDD = 2.7 V
RL = 600 Ω
CL = 600 pF
TA = 25°C
Figure 18
300
180
60
−60
240
120
0
−90
100
60
20
−20
80
40
0
−40
100 f − Frequency − Hz
10k 10M
AVD
Phase
VDD = 5 V
RL = 600 Ω
CL = 600 pF
TA = 25°C
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
− Large-Signal Differential Amplification − dBAVD
m
φ− Phase Margin − degrees
1k 100k 1M
Figure 19
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
200
100
010
RL − Load Resistance − kΩ
250
150
50
1 100 10000.1
TA = 25°C
− Differential Voltage Amplification − V/mVAVD
VDD = 2.7 V
VDD = 5 V
Figure 21
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1000
10
0.1
100
1
− Differential Voltage Amplification − V/mVAVD
TA − Free-Air Temperature − °C
−75 −50 −25 0 755025 100 125
VDD = 2.7 V
VIC = 1.35 V
VO = 0.6 V to 2.1 V
RL = 1 MΩ
RL = 600 Ω
RL = 10 kΩ
Figure 22
−50
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1000
10
0.1
100
1
− Differential Voltage Amplification − V/mVAVD
TA − Free-Air Temperature − °C
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 1 MΩ
RL = 600 Ω
−75 −25 0 755025 100 125
RL = 10 kΩ
Figure 23
OUTPUT IMPEDANCE
vs
FREQUENCY
100
1
0.01
10
0.10
100 1k 10k 100k
f − Frequency − Hz 1M
ZO− Output Impedance −
AV = 100
AV = 10
AV = 1
VDD = 2.7 V
TA = 25°C
Ω
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 24
OUTPUT IMPEDANCE
vs
FREQUENCY
100
1
0.01
10
0.1
f − Frequency − Hz
100 1k 10k 100k 1M
VDD = ±2.5 V
TA = 25°C
Av = 100
− Output Impedance −ZoΩ
Av = 10
Av = 1
Figure 25
VIC = 1.35 V
and 2.5 V
TA = 25°C
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
90
80
60
40
70
50
10 100 1k
f − Frequency − Hz
10k 100k 10M
VDD = 5 V
VDD = 2.7 V
CMRR − Common-Mode Rejection Ratio − dB
1M
Figure 26
−20−40 0 20 806040 100 120
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
110
100
90
80
105
95
85
TA − Free-Air Temperature − °C
CMRR − Common-Mode Rejection Ratio − dB
120
115
VDD = 5 V
VDD = 2.7 V
140
Figure 27
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
120
60
0
10 100 1k 10k
f − Frequency − Hz 10M
kSVR− Supply-Voltage Rejection Ratio − dB
kSVR−
VDD = 2.7 V
TA = 25°C
100k 1M
kSVR+
100
40
80
20
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
120
80
40
0
100
60
20
10 100 1 k 10 k 10 M
f − Frequency − Hz 1 M100 k
kSVR − Supply Voltage Rejection Ratio − dB
kSVR+
kSVR−
VDD = 5 V
TA = 25°C
Figure 29
SUPPLY CURRENT (PER CHANNEL)
vs
SUPPLY VOLTAGE
1.2
0.8
0.4
0
1
0.6
0.2
2.5 3 3.5 4
VDD − Supply Voltage − V 74.5
IDD − Supply Current (Per Channel) − mA
TA = 0°C
1.6
1.4
5 5.5 6 6.5
TA = 125°C
TA = 85°C
TA = 25°C
TA = −40°C
Figure 30
SLEW RATE
vs
LOAD CAPACITANCE
1k
CL − Load Capacitance − pF
100 10k 100k10
VDD = 5 V
AV = −1
TA = 25°C
SR+
12
8
4
0
10
6
2
16
14
SR − Slew Rate − V/µs
SR−
Figure 31
−50−75 −25 0 755025 100 125
SLEW RATE
vs
FREE-AIR TEMPERATURE
14
12
10
8
13
11
9
TA − Free-Air Temperature − °C
VDD = 2.7 V
RL = 10 kΩ
CL = 100 pF
AV = 1
SR − Slew Rate − µs
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
t − Time − µs
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
40
0
20
−20
VO− Output Voltage − mV
80
60
0 1.510.5 2 2.5 3.53 4 4.5 5
100
−40
−60
Figure 33
t − Time − µs
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
40
0
20
−20
VO− Output Voltage − mV
80
60
0 1.510.5 2 2.5 3.53 4 4.5 5
100
−40
−60
Figure 34
t − Time − µs
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
1.5
0.5
1
0
VO− Output Voltage − V
2.5
2
0 1.510.5 2 2.5 3.53 4 4.5 5
3
−0.5
−1
Figure 35
t − Time − µs
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
3
1
2
0
VO− Output Voltage − V
5
4
0 1.510.5 2 2.5 3.53 4 4.5 5
6
−1
−2
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
t − Time − µs
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
INVERTING SMALL-SIGNAL
PULSE RESPONSE
40
0
20
−20
VO− Output Voltage − mV
80
60
0 1.510.5 2 2.5 3.53 4 4.5 5
100
−40
−60
Figure 37
t − Time − µs
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
INVERTING SMALL-SIGNAL
PULSE RESPONSE
40
0
20
−20
VO− Output Voltage − mV
80
60
0 1.510.5 2 2.5 3.53 4 4.5 5
100
−40
−60
Figure 38
t − Time − µs
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
INVERTING LARGE-SIGNAL
PULSE RESPONSE
1.5
0.5
1
0
VO− Output Voltage − V
2.5
2
0 1.510.5 2 2.5 3.53 4 4.5 5
3
−0.5
−1
Figure 39
t − Time − µs
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
INVERTING LARGE-SIGNAL
PULSE RESPONSE
2.5
1.5
2
1
VO− Output Voltage − V
3.5
3
0 1.510.5 2 2.5 3.53 4 4.5 5
4
0.5
1
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 40
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
120
80
40
0100 10k
f − Frequency − Hz
140
100
60
20
1k
160
10
VDD = 2.7 V
RS = 20 Ω
TA = 25°C
− Input Noise Voltage −VnnV/ Hz
Figure 41
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100
f − Frequency − Hz
1k 10k10
VDD = 5 V
RS = 20 Ω
TA = 25°C
120
80
40
0
100
60
20
140
− Input Noise Voltage −nV Hz
Vn
t − Time − s
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
NOISE VOLTAGE
OVER A 10 SECOND PERIOD
012345678910
Noise Voltage − nV
300
100
−100
−300
200
GND
−200
Figure 42
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 43
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10
0.1
0.001
1
0.01
f − Frequency − Hz
10 100 1k 10k 100k
VDD = 2.7 V
RL = 600 Ω
TA = 25°C
THD+N − Total Harmonic Distortion Plus Noise − %
Av = 100
Av = 10
Av = 1
Figure 44
10
0.1
0.001
1
0.01
f − Frequency − Hz
10 100 1k 10k 100k
VDD = 5 V
RL = 600 Ω
TA = 25°C
THD+N − Total Harmonic Distortion Plus Noise − %
Av = 100
Av = 10
Av = 1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
Figure 45
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
5.2
4.8
4.4
4
5
4.6
4.2
2 2.5 3 3.5 5
VDD − Supply Voltage − V
4.54 5.5 6
Gain-Bandwidth Product − MHz
RL = 600 Ω
CL = 100 pF
f = 10 kHz
TA = 25°C
Figure 46
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
4
2
01k
CL − Load Capacitance − pF
5
3
1
100 10k 100k10
Unity-Gain Bandwidth − MHz
Rnull = 0
Rnull = 20
Rnull = 50
Rnull = 100
VDD = 5 V
RL = 600 Ω
TA = 25°C
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 47
60
40
20
0
50
30
10
10 CL − Load Capacitance − pF
1k
VDD = 5 V
RL = 600 Ω
TA = 25°C
m
φ− Phase Margin − degrees
100 10k 100K
PHASE MARGIN
vs
LOAD CAPACITANCE
90
70
80
Rnull = 0
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
Figure 48
15
25
35
40
20
30
10 CL − Load Capacitance − pF
1k
VDD = 5 V
RL = 600 Ω
TA = 25°C
Gain Margin − dB
100 10k 100K
GAIN MARGIN
vs
LOAD CAPACITANCE
0
10
5
Rnull = 0
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
Figure 49
VDD = 5 V
AV = 5
TA = 25°C
TLV2770
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
0
−4
−8
−12
2
−2
−6
−10
−4 −2 0 2 8
t − Time − µs
641014
Shutdown Signal − V
12
− Output Voltage − V
VO
8
6
5
4
3
2
1
0
−1
47
SHDN = VDD
SHDN = GND
VO
Figure 50
TLV2773
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
8
2
−2
−6
−10
4
0
−4
−8
−2.5 0 2.5 7.5
t − Time − µs
510 15
Shutdown Signal − V
12.5
− Output Voltage − V
VO
8
6
5
4
3
2
1
0
−1
67
SHDN = VDD
VO
Channel 1
VDD = 5 V
AV = 5
TA = 25°C
Channel 1 Switched
Channel 2 SHDN MODE
SHDN = GND
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 51
TLV2775 − CHANNEL 1
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
8
2
−2
−6
−10
4
0
−4
−8
−2.5 0 2.5 7.5
t − Time − µs
510 15
Shutdown Signal − V
12.5
− Output Voltage − V
VO
8
6
5
4
3
2
1
0
−1
67
SHDN = VDD
VO
Channel 1
VDD = 5 V
AV = 5
TA = 25°C
Channel 1/2 Switched
Channel 3/4 SHDN MODE
SHDN = GND
TLV2770
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
0
−4
−8
−12
2
−2
−6
−10
−4 −2 0 4
t − Time − µs
26 14
Shutdown Signal − V
8
24
18
15
12
9
6
3
0
−3
421
Figure 52
IDD − Supply Current − mA
10 12
VDD = 5 V
AV = 5
TA = 25°C
SHDN = GND
SHDN = VDD
IDD
Figure 53
TLV2773
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
−3
−9
−18
0
−6
−12
−15
−5 −2.5 0 5
t − Time − µs
2.5 7.5 15
Shutdown Signal − V
10
70
50
40
30
20
10
0
−3
360
IDD − Supply Current − mA
12.5
VDD = 5 V
AV = 5
TA = 25°C
Channel 1 Switched
Channel 2 SHDN MODE
SHDN = GND
SHDN = VDD
IDD
Figure 54
TLV2775
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
−3
−9
−18
0
−6
−12
−15
−5 −2.5 0 5
t − Time − µs
2.5 7.5 15
Shutdown Signal − V
10
70
50
40
30
20
10
0
−3
360
IDD − Supply Current − mA
12.5
VDD = 5 V
AV = 5
TA = 25°C
Channel 1/2 Switched
Channel 3/4 SHDN MODE
SHDN = GND
SHDN = VDD
IDD
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 55
7
4
2
0
5
3
1
−75 −50 −25 25
TA − Free-Air Temperature − °C
0 50 125
75
6
100
AV = 5
RL = OPEN
SHDN = GND
VDD 5 V
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
VDD 2.7 V
DD
I Shutdown Supply Current − −Aµ
Figure 56
TLV2770
SHUTDOWN FORWARD ISOLATION
vs
FREQUENCY
140
20
−20
40
0
f − Frequency − Hz
10 102103104106
Shutdown Forward Isolation − dB
SHDN MODE
AV = 1
VDD = 2.7 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
VI(PP) = 2.7 V
105
100
120
80
60
VI(PP) = 0.1 V
Figure 57
TLV2770
SHUTDOWN REVERSE ISOLATION
vs
FREQUENCY
140
20
−20
40
0
f − Frequency − Hz
10 102103104106
Shutdown Reverse Isolation − dB
SHDN MODE
AV = 1
VDD = 2.7 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
VI(PP) = 2.7 V
105
100
120
80
60 VI(PP) = 0.1 V
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
_
+
Rnull
RLCL
Figure 58
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier (See
Figure 59). A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
_
+
Figure 59. Driving a Capacitive Load
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input of fset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 60. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 61).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)sR1C1Ǔ
Figure 61. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
Figure 62. Two Pole Low Pass Sallen Key Filter
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
using the TLV2772 as an accelerometer interface
The schematic (see Figure 63) shows the ACH04-08-05 interfaced to the TLV1544 10-bit analog-to-digital
converter (ADC).
The ACH04-08-05 is a shock sensor designed to convert mechanical acceleration into electrical signals. The
sensor contains three piezoelectric sensing elements oriented to simultaneously measure acceleration in three
orthogonal, linear axes (x, y, z). The operating frequency is 0.5 Hz to 5 kHz. The output is buffered with an
internal JFET and has a typical output voltage of 1.80 mV/g for the x and y axis and 1.35 mV/g for the z axis.
Amplification and frequency shaping of the shock sensor output is done by the TLV2772 rail-to-rail operational
amplifier. The TLV2772 is ideal for this application as it offers high input impedance, good slew rate, and
excellent dc precision. The rail-to-rail output swing and high output drive are perfect for driving the analog input
of the TLV1544 ADC.
_
+
1 Axis ACH04−08−05
Shock Sensor
3 V
1.23 V
R1
100 kΩ
C1
0.22 µF
R2
1 MΩ
R3
10 kΩ
1.23 V C2
2.2 nF
R4
100 kΩ
3 V R5
1 kΩ
C3
0.22 µF
1/2
TLV2772
Signal Conditioning
Output to
TLV1544 (ADC)
R6
2.2 kΩ
1.23 V
3 V
TLV431
C
RA
4
81
2
3
Voltage Reference
Figure 63. Accelerometer Interface Schematic
The sensor signal must be amplified and frequency-shaped to provide a signal the ADC can properly convert
into the digital domain. Figure 63 shows the topology used in this application for one axis of the sensor. This
system is powered from a single 3-V supply. Configuring the TLV431 with a 2.2-kΩ resistor produces a reference
voltage of 1.23 V. This voltage is used to bias the operational amplifier and the internal JFETs in the shock
sensor.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain calculation
Since the TLV2772 is capable of rail-to-rail output using a 3-V supply, VO = 0 (min) to 3 V (max). With no signal
from the sensor, nominal VO = reference voltage = 1.23 V. Therefore, the maximum negative swing from nominal
is 0 V − 1.23 V = −1.23 V and the maximum positive swing is 3 V − 1.23 V = 1.77 V. By modeling the shock sensor
as a low impedance voltage source with output of 2.25 mV/g (max) in the x and y axis and 1.70 mV/g (max) in
the z axis, the gain of the circuit is calculated by equation 1.
Gain +Output Swing
Sensor Signal Acceleration (1)
To avoid saturation of the operational amplifier , the gain calculations are based on the maximum negative swing
of −1.23 V and the maximum sensor output of 2.25 mV/g (x and y axis) and 1.70 mV/g (z axis).
Gain (x, y) +*1.23 V
2.25 mVńg *50 g +10.9 (2)
Gain (z) +–1.23 V
1.70 mVńg –50 g +14.5 (3)
and
By selecting R3 = 10 kΩ and R4 = 100 kΩ, in the x and y channels, a gain of 11 is realized. By selecting
R3 = 7.5 kΩ and R4 = 100 kΩ, in the z channel, a gain of 14.3 is realized. The schematic shows the configuration
for either the x or y axis.
bandwidth calculation
To calculate the component values for the frequency shaping characteristics of the signal conditioning circuit,
1 Hz and 500 Hz are selected as the minimum required 3-dB bandwidth.
To minimize the value of the input capacitor (C1) required to set the lower cutoff frequency requires a large value
resistor for R2. A 1-MΩ resistor is used in this example. To set the lower cutoff frequency, the required capacitor
value for C1 is:
C1 +1
2pfLOW R2+0.159 µF(4)
Using a value of 0.22 µF, a more common value of capacitor, the lower cutoff frequency is 0.724 Hz.
To minimize the phase shift in the feedback loop caused by the input capacitance of the TLV2772, it is best to
minimize the value of the feedback resistor R4. However, to reduce the required capacitance in the feedback
loop a large value for R4 is required. Therefore, a compromise for the value of R4 must be made. In this circuit,
a value of 100 kΩ has been selected. To set the upper cutoff frequency, the required capacitor value for C2 is:
C2 +1
2pfHIGH R4+3.18 µF(5)
Using a 2.2-nF capacitor, the upper cutoff frequency is 724 Hz.
R5 and C3 also cause the signal response to roll off. Therefore, it is beneficial to design this roll-off point to begin
at the upper cutoff frequency. Assuming a value of 1 kΩ for R5, the value for C3 is calculated to be
0.22 µF.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance o f the TLV277x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the input
of the amplifier.
DSurface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 64 and is calculated by the following formula:
PD+ǒTMAX *TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV277x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 64. Maximum Power Dissipation vs Free-Air Temperature
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
shutdown function
Three members of the TLV277x family (TLV2770/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.8 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care must
be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the
operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2. Therefore,
when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal must be pulled to VDD−
(not GND) to disable the operational amplifier.
The amplifier output with a shutdown pulse is shown in Figures 48, 49, and 50. The amplifier is powered with
a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and
turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform.
The times for the single, dual, and quad are listed in the data tables. The bump on the rising edge of the TLV2770
output waveform is due to the start-up circuit on the bias generator. For the dual and quad (TLV2773/5), this
bump is attributed to the bias generator’s start-up circuit as well as the crosstalk between the other channel(s),
which are in shutdown.
Figures 55 and 56 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is
powered b y ±1.35-V su p p l i e s a nd c o n f i g u r e d a s a v o l t a g e f o llower (AV = 1). The isolation performance is plotted
across frequency for both 0.1 VPP and 2.7 VPP input signals. During normal operation, the amplifier would not
be able to handle a 2.7-VPP input signal with a supply voltage of ±1.35 V since it exceeds the common-mode
input voltage range (VICR). However, this curve illustrates that the amplifier remains in shutdown even under
a worst case scenario.
SGLS317A − O C TOBER 2005 − REVISED SEPTEMBER 2007
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 65 are
generated using the TLV2772 typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−+
−
+
−+
−
+−
VDD+
rp
IN− 2
IN+ 1
GND
rd1
11
j1 j2
10
rss iss
3
12
rd2
ve
54 de
dp
vc
dc
4
C1
53
r2 6
9
egnd
vb
fb
C2
gcm ga vlim
8
5ro1
ro2
hlim
90 dlp
91
dln
92
vlnvlp
99
7
css
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
*
* connections: noninverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt TLV2772 1 2 3 4 5
*c1 11 12 2.8868E-12
c2 6 7 10.000E−12
css 10 99 2.6302E−12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
15.513E6 −1E3 1E3 16E6 −16E6
ga 6 0 11 12 188.50E−6
gcm 0 6 10 99 9.4472E−9
iss 3 10 dc 145.50E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
j2 12 1 10 jx2
r2 6 9 100.00E3
rd1 4 11 5.3052E3
rd2 4 12 5.3052E3
ro1 8 5 17.140
ro2 7 99 17.140
rp 3 4 4.5455E3
rss 10 99 1.3746E6
vb 9 0 dc 0
vc 3 53 dc .82001
ve 54 4 dc .82001
vlim 7 8 dc 0
vlp 91 0 dc 47
vln 0 92 dc 47
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 PJF(Is=2.2500E−12 Beta=244.20E−6
+ Vto=−.99765)
.model jx2 PJF(Is=1.7500E−12 Beta=244.20E−6
+ Vto=−1.002350)
.ends
*$
Figure 65. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2772AMDREP ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2774AMDREP ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2774MDREP ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06607-02XE ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06607-03YE ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06607-04YE ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2772A-EP, TLV2774-EP, TLV2774A-EP, TLV277X-EP, TLV277XA-EP :
•Catalog: TLV2772A,TLV2774,TLV2774A,TLV277X,TLV277XA
•Automotive: TLV2772A-Q1
•Military: TLV2772AM
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2772AMDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2774AMDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2774MDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2772AMDREP SOIC D 8 2500 367.0 367.0 35.0
TLV2774AMDREP SOIC D 14 2500 333.2 345.9 28.6
TLV2774MDREP SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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