74LCX244MTCX_E4 - Fairchild - Datasheet.Technology

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

74LCX244 Rev. 1.12.1

February 2009

74LCX244

Low Voltage Buffer/Line Driver with 5V Tolerant

Inputs and Outputs

Features

■5V tolerant inputs and outputs

■2.3V to 3.6V VCC specifications provided

■6.5ns tPD max. (VCC = 3.3V), 10µA ICC max.

■Power down high impedance inputs and outputs

■Supports live insertion/withdrawal(1)

■±24mA output drive (VCC = 3.0V)

■Latch-up performance exceeds 500mA

■ESD performance:

– Human body model > 2000V

– Machine model > 200V

■Leadless DQFN package

Note:

1. To ensure the high-impedance state during power up

or down, OE should be tied to VCC through a pull-up

resistor: the minimum value or the resistor is

determined by the current-sourcing capability of the

driver.

General Description

The LCX244 contains eight non-inverting buffers with

3-STATE outputs. The device may be employed as a

memory address driver, clock driver and bus-oriented

transmitter/receiver. The LCX244 is designed for low

voltage (2.5V or 3.3V) VCC applications with capability of

interfacing to a 5V signal environment.

The LCX244 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Information

Note:

2. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCX244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LCX244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX244BQX(2) MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),

JEDEC MO-241, 2.5 x 4.5mm

74LCX244MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LCX244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

■Implements proprietary noise/EMI reduction circuitry

74LCX244 Rev. 1.12.1 2

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Connection Diagram

Pin Assignments for SOIC, SOP, SSOP, and TSSOP

Pad Assignments for DQFN

(Top Through View)

Pin Description

Logic Diagram

Truth Tables

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Pin Names Description

OE1, OE23-STATE Output Enable Inputs

I0–I7Inputs

O0–O7Outputs

Inputs Outputs

OE1In(Pins 12, 14, 16, 18)

LL L

LH H

HX Z

Inputs Outputs

OE2In(Pins 3, 5, 7, 9)

LL L

LH H

HX Z

74LCX244 Rev. 1.12.1 3

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Note:

3. IO Absolute Maximum Rating must be observed.

Recommended Operating Conditions(4)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

4. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

VCC Supply Voltage –0.5V to +7.0V

VIDC Input Voltage –0.5V to +7.0V

VODC Output Voltage

Output in 3-STATE –0.5V to +7.0V

Output in HIGH or LOW State(3) –0.5V to VCC + 0.5V

IIK DC Input Diode Current, VI < GND –50mA

IOK DC Output Diode Current

VO < GND –50mA

VO > VCC +50mA

IODC Output Source/Sink Current ±50mA

ICC DC Supply Current per Supply Pin ±100mA

IGND DC Ground Current per Ground Pin ±100mA

TSTG Storage Temperature –65°C to +150°C

Symbol Parameter Min. Max. Units

VCC Supply Voltage

Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 0 5.5 V

VOOutput Voltage

3-STATE 0 5.5 V

HIGH or LOW State 0 VCC

IOH / IOL Output Current

VCC = 3.0V–3.6V ±24 mA

VCC = 2.7V–3.0V ±12

VCC = 2.3V–2.7V ±8

TAFree-Air Operating Temperature –40 85 °C

Δt / ΔV Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns / V

74LCX244 Rev. 1.12.1 4

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

DC Electrical Characteristics

Note:

5. Outputs disabled or 3-STATE only.

AC Electrical Characteristics

Note:

6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate

outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-

LOW (tOSHL) or LOW-to-HIGH (tOSLH).

Symbol Parameter VCC (V) Conditions

TA = –40°C to +85°C

UnitsMin. Max.

VIH HIGH Level Input Voltage 2.3–2.7 1.7 V

2.7–3.6 2.0

VIL LOW Level Input Voltage 2.3–2.7 0.7 V

2.7–3.6 0.8

VOH HIGH Level Output Voltage 2.3–3.6 IOH = –100µA VCC – 0.2 V

2.3 IOH = –8mA 1.8

2.7 IOH = –12mA 2.2

3.0 IOH = –18mA 2.4

IOH = –24mA 2.2

VOL LOW Level Output Voltage 2.3–3.6 IOL = 100µA 0.2 V

2.3 IOL = 8mA 0.6

2.7 IOL = 12mA 0.4

3.0 IOL = 16mA 0.4

IOL = 24mA 0.55

IIInput Leakage Current 2.3–3.6 0 ≤ VI ≤ 5.5V ±5.0 µA

IOZ 3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V,

VI = VIH or VIL

±5.0 µA

IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA

ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA

3.6V ≤ VI, VO ≤ 5.5V(5) ±10

ΔICC Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA

Symbol Parameter

TA = –40°C to +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V,

CL = 50pF

VCC = 2.7V,

CL = 50pF

VCC = 2.5V ± 0.2V,

CL = 30pF

Min. Max. Min. Max. Min. Max.

tPHL, tPLH Propagation Delay,

Data to Output

1.5 6.5 1.5 7.5 1.5 7.8 ns

tPZL, tPZH Output Enable Time 1.5 8.0 1.5 9.0 1.5 10.0 ns

tPLZ, tPHZ Output Disable Time 1.5 7.0 1.5 8.0 1.5 8.4 ns

tOSHL, tOSLH Output to Output Skew(6) 1.0 ns

74LCX244 Rev. 1.12.1 5

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Dynamic Switching Characteristics

Capacitance

Symbol Parameter VCC (V) Conditions

TA = 25°C

UnitTypical

VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6

VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7.0 pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8.0 pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25.0 pF

74LCX244 Rev. 1.12.1 6

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

AC Loading and Waveforms (Generic for LCX Family)

Figure 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH, tPHZ GND

Symbol

VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

Vmi 1.5V 1.5V VCC / 2

Vmo 1.5V 1.5V VCC / 2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH – 0.3V VOH – 0.3V VOH – 0.15V

74LCX244 Rev. 1.12.1 7

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Schematic Diagram (Generic for LCX Family)

74LCX244 Rev. 1.12.1 8

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Tape and Reel Specification

Tape Format for DQFN

Tape Dimension inches (millimeters)

Reel Dimensions inches (millimeters)

Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status

BQX Leader (Start End) 125 (typ.) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ.) Empty Sealed

Tape SizeABCDNW1W2

12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)

74LCX244 Rev. 1.12.1 9

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions

Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

0.10 C

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

PIN ONE

INDICATOR

0.25

110

BCA

20 11

X 45°

8°

0°

SEATING PLANE

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

LAND PATTERN RECOMMENDATION

F) DRAWING FILENAME: MKT-M20BREV3

0.65

1.27

2.25

9.50

13.00

12.60

11.43

7.60

7.40

10.65

10.00

0.51

0.35 1.27

2.65 MAX

0.30

0.10

0.33

0.20

0.75

0.25

(R0.10)

1.27

0.40

(1.40)

0.25

D) CONFORMS TO ASME Y14.5M-1994

74LCX244 Rev. 1.12.1 10

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

74LCX244 Rev. 1.12.1 11

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

74LCX244 Rev. 1.12.1 12

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

74LCX244 Rev. 1.12.1 13

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

74LCX244 Rev. 1.12.1 14

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Rev. I38

74LCX244 — Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs