2−17
Table 2−14. Miscellaneous Terminals
TERMINAL
NAME PDV/
PPM
NO.
GHK/
ZHK
NO.
I/O DESCRIPTION
BPCCE 44 N5 I
Bus/power clock control management terminal. When this terminal is tied high and the
PCI2050B device is placed in the D3 power state, it enables the PCI2050B device to place the
secondary bus in the B2 power state. The PCI2050Bdevice disables the secondary clocks and
drives them to 0. When tied low, placing the PCI2050B device in the D3 power state has no
effect on the secondary bus clocks.
CONFIG66 125 L18 I
Configure 6 6 MHz operation. This input-only terminal is used to specify if the PCI2050B device
is capable of running at 66 MHz. If this terminal is tied high, then device can be run at 66 MHz.
If this terminal is tied low, then the PCI2050B device can only function under the 33-MHz PCI
configuration.
GPIO3/HS_SWITCH
GPIO2
GPIO1
GPIO0
24
25
27
28
K1
K2
K5
K6
IGeneral-purpose I/O terminals
GPIO3 is HS_SWITCH in cPCI mode.
HS_SWITCH provides the status of the ejector handle switch to the cPCI logic.
HS_ENUM 127 L15 O Hot-swap ENUM
HS_LED 128 L14 O Hot-swap LED output
MS0 155 E17 I Mode select 0
MS1 106 T19 I Mode select 1
P_M66ENA 102 W16 I
Primary interface 66 MHz enable. This input-only signal designates the primary interface bus
speed. This terminal must be pulled low for 33-MHz operation on the primary bus. In this case,
S_M66ENA signal will be driven low by the PCI2050B device, forcing the secondary bus to
run at 33 MHz. For 66-MHz operation, this terminal must be pulled high.
S_M66ENA 153 E18 I/O
Secondary 66 MHz enable. This signal designates the secondary bus speed. If the
P_M66ENA is driven low, then this signal is driven low by the PCI2050B device, forcing
secondary bus to run at 33 MHz. If the primary bus is running at 66 MHz (P_M66ENA is high),
then S_M66ENA is an input and must be externally pulled high for the secondary bus to
operate a t 6 6 MHz or pulled low for secondary bus to operate at 33 MHz. Note that S_M66ENA
is an open drained output.
Table 2−15. Power Supply Terminals
TERMINAL
NAME PDV/PPM NO. GHK NO.
GND
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
A7, A12, A14, B10, C5,
C15, D19, E7, E9, F13,
F18, G3, H15, J2, J14, L6,
M5, M19, N17, P5, R8,
R10, R14, R19, U1, U5, U9,
U12, V6, V14
Device ground terminals
VCC
1, 26, 34, 40, 51, 53, 56, 62,
69, 75, 81, 91, 97, 103, 105,
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
208
A3, A9, A13, A16, C8, C14,
D2, E11, E19, F6, F7, M15,
G17, H18, K3, K15, M2, N3,
N15, P7, P8, P15, T2, T18,
U13, V11, V16, W4, W8,
W10, W15
Power-supply terminal for core logic (3.3 V)
P_VCCP(1) 124 L19 Primary bus-signaling environment supply. P_VCCP is used in
protection circuitry on primary bus I/O signals.
S_VCCP(1) 135 J17 Secondary bus-signaling environment supply. S_VCCP is used in
protection circuitry on secondary bus I/O signals.
NOTE 1: TI recommends that P_VCCP and S_VCCP be powered up first before applying power to VCC.