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For small orders, phone 1-800-835-8769.
General Description
The MAX5120/MAX5121 are low-power, 12-bit, voltage-
output digital-to-analog converters (DACs) with an inter-
nal precision bandgap reference and an output amplifier.
The MAX5120 operates on a +5V supply with an internal
amplifier reference of +2.5V and is capable of a +4.095V
full-scale output range. The MAX5121, operating on +3V,
delivers its +2.0475V full-scale output with an internal
precision reference of +1.25V. If necessary, the user can
override the internal, <10ppm/°C voltage reference with
an external reference. Both devices draw only 500µA of
supply current, which reduces to 3µA in power-down
mode. In addition, their power-up reset feature allows for
a user-selectable initial output state of either 0V or mid-
scale and minimizes output voltage glitches during
power-up.
The serial interface is compatible with SPI™, QSPI™
and MICROWIRE™, which makes the MAX5120/
MAX5121 suitable for cascading multiple devices. Each
DAC has a double-buffered input organized as an input
register followed by a DAC register. A 16-bit shift regis-
ter loads data into the input register. The DAC register
may be updated independently or simultaneously with
the input register.
Both devices are available in a 16-pin QSOP package
and are specified for the extended industrial (-40°C to
+85°C) temperature range. For pin-compatible 14-bit
upgrades, see the MAX5170/MAX5172 data sheet;
for pin-compatible 13-bit versions, see the MAX5130/
MAX5131 data sheet.
________________________Applications
Industrial Process Controls
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Motion Control
µP-Controlled Systems
Features
♦Single-Supply Operation
+5V (MAX5120)
+3V (MAX5121)
♦Full-Scale Output Range
+4.095V (MAX5120)
+2.0475V (MAX5121)
♦Built-In 10ppm/°C (max) Precision Bandgap
Reference
+2.5V (MAX5120)
+1.25V (MAX5121)
♦Adjustable Output Offset
♦SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial
Interface
♦Pin-Programmable Shutdown Mode and Power-
Up Reset (0V or Midscale Output Voltage)
♦Buffered Output Capable of Driving 5kΩ100pF
or 4–20mA Loads
♦Space-Saving 16-Pin QSOP Package
♦Pin-Compatible 13-Bit Upgrades Available
(MAX5130/MAX5131)
♦Pin-Compatible 14-Bit Upgrades Available
(MAX5170/MAX5172)
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OS VDD
REFADJ
REF
AGND
PD
UPO
DOUT
DGND
TOP VIEW
MAX5120
MAX5121
QSOP
OUT
RSTVAL
CS
PDL
CLR
DIN
SCLK
19-1428; Rev 0; 2/99
PART
MAX5120AEEE
MAX5120BEEE -40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-
PACKAGE
16 QSOP
16 QSOP
Pin Configuration Ordering Information
INL
(LSB)
±0.5
±1
MAX5121AEEE
MAX5121BEEE ±1
-40°C to +85°C
-40°C to +85°C 16 QSOP
16 QSOP ±2
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX5120 (+5V)
(VDD = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND...............................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (VDD + 0.3V)
OUT to AGND.............................................-0.3V to (VDD + 0.3V)
OS to AGND ...................................(AGND - 4V) to (VDD + 0.3V)
REF, REFADJ to AGND..............................-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
QSOP (derate 8.00mW/°C above +70°C).....................667mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
VIN = 0 or VDD
MAX5120A
REFADJ = VDD
4.5V ≤VDD ≤5.5V
MAX5120B
MAX5120B
MAX5120A
MAX5120A
Code = FFF hex, TA= +25°C
TA= +25°C
CONDITIONS
pF8CIN
Input Capacitance µA-1 0.001 1IIN
Input Leakage Current mV200VHYS
Input Hysteresis V0.8VIL
Input Low Voltage V3VIH
Input High Voltage
µA3.3 7REFADJ Current
ppm/°C
10
TCVREF 3
Output Voltage Temperature
Coefficient
V2.5VREF
Output Voltage
-0.5 0.5 Bits12NResolution
µV/V20 250PSRRPower-Supply Rejection Ratio
ppm/°C
10 30
TCVFS 310
Full-Scale Temperature
Coefficient (Note 3)
V4.0458 4.095 4.1442VFS
Full-Scale Voltage
LSB-1 1DNLDifferential Nonlinearity mV-10 10VOS
Offset Error (Note 2) -3 -0.2 3 mVGEGain Error
UNITSMIN TYP MAXSYMBOLPARAMETER
ISINK = 2mA
ISOURCE = 2mA V0.13 0.4VOL
Output Low Voltage VVDD - 0.5VOH
Output High Voltage
MAX5120B LSB
-1 1
INLIntegral Nonlinearity (Note 1)
0 ≤IOUT ≤100µA (sourcing) µV/µA0.1 1VOUT/IOUT
Reference External Load Regulation mA4Reference Short-Circuit Current
STATIC PERFORMANCE
REFERENCE
DIGITAL INPUT
DIGITAL OUTPUTS
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX5120 (+5V) (continued)
(VDD = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
To ±0.5LSB, VSTEP = 4V
CS = VDD, fSCLK = 100kHz,
VSCLK = 5Vp-p
CONDITIONS
µA320ISHDN
Power-Supply Current in Shutdown µA500 600IDD
Power-Supply Current (Note 5) V4.5 5.5VDD
Power-Supply Voltage (Note 5)
nV-s5Digital Feedthrough
ms2Time Required to Exit Shutdown kΩ83 121ROS
OS Input Resistance
µs20Output Settling Time V0 to VDD
Output Voltage Swing (Note 4)
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS—MAX5121 (+3V)
(VDD = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX5121A
REFADJ = VDD
2.7V ≤VDD ≤3.3V
MAX5121B
MAX5121B
MAX5121A
MAX5121A
Data = FFF hex, TA= +25°C
TA= +25°C
CONDITIONS
mV200VHYS
Input Hysteresis V0.8VIL
Input Low Voltage V2.2VIH
Input High Voltage
µA3.3 7REFADJ Current mA4Reference Short-Circuit Current
ppm/°C
10
TCVREF
MAX5121B
3
0 ≤IOUT ≤100µA (sourcing)
Output Voltage Temperature
Coefficient
V1.25VREF
Output Voltage
-1 1
µV/µA0.1 1
Bits12NResolution
µV/V20 250PSRRPower-Supply Rejection Ratio
ppm/°C
10 30
TCVFS
LSB
310
VOUT/IOUT
Full-Scale Temperature
Coefficient (Note 3)
V2.0229 2.0475 2.0721VFS
Full-Scale Voltage
LSB-1 1DNLDifferential Nonlinearity mV-10 10VOS
Offset Error (Note 2) -5 -0.2 5
Reference External Load Regulation
mVGEGain Error
UNITSMIN TYP MAXSYMBOLPARAMETER
-2 2
INLIntegral Nonlinearity (Note 1)
V/µs0.6SRVoltage Output Slew Rate
DYNAMIC PERFORMANCE
POWER REQUIREMENTS
STATIC PERFORMANCE
REFERENCE
DIGITAL INPUT
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX5121 (+3V) (continued)
(VDD = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
To ±0.5LSB, VSTEP = 2V
CS = VDD, fSCLK = 100kHz,
VSCLK = 3Vp-p
CONDITIONS
µA320ISHDN
Power-Supply Current in Shutdown µA500 600IDD
Power-Supply Current (Note 5) V2.7 3.6VDD
Power-Supply Voltage (Note 5)
nV-s5Digital Feedthrough
ms2Time Required to Exit Shutdown kΩ83 121ROS
OS Input Resistance
µs20Output Settling Time V0 to VDD
Output Voltage Swing (Note 4)
UNITSMIN TYP MAXSYMBOLPARAMETER
ISINK = 2mA V0.13 0.4VOL
Output Low Voltage ISOURCE = 2mA VVDD - 0.5VOH
Output High Voltage
VIN = 0 or VDD µA-1 0.001 1IIN
Input Leakage Current pF8CIN
Input Capacitance
V/µs0.6SRVoltage Output Slew Rate
TIMING CHARACTERISTICS—MAX5120 (+5V)
(VDD = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ns40tCSS
CS Fall to SCLK Rise Setup Time ns40tCL
SCLK Pulse Width Low
CONDITIONS ns100tCP
SCLK Clock Period ns40tCH
SCLK Pulse Width High
ns0tCSH
SCLK Rise to CS Rise Hold Time
ns10tCS0
SCLK Rise to CS Fall Delay Time
ns40tDS
SDI Setup Time ns0tDH
SDI Hold Time
UNITSMIN TYP MAXSYMBOLPARAMETER
ns100tCSW
CS Pulse Width High ns40tCS1
CS Rise to SCLK Rise Hold Time
CLOAD = 200pF ns80tDO1
SCLK Rise to DOUT Valid
Propagation Delay Time
CLOAD = 200pF ns80tDO2
SCLK Fall to DOUT Valid
Propagation Delay Time
DIGITAL OUTPUTS
POWER REQUIREMENTS
DYNAMIC PERFORMANCE
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 5
Note 1: Accuracy is guaranteed as shown in the following table:
Note 2: Offset is measured at the code closest to 10mV.
Note 3: The temperature coefficient is determined by the “box” method in which the maximum ∆VOUT over the temperature range is
divided by ∆T.
Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points.
Note 5: RLOAD = ∞and digital inputs are at either VDD or DGND.
TIMING CHARACTERISTICS—MAX5121 (+3V)
(VDD = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ns60tCSS
CS Fall to SCLK Rise Setup Time
ns150
ns
CLOAD = 200pF
75
tCSW
tCL
SCLK Pulse Width Low
CONDITIONS ns150tCP
SCLK Clock Period ns75tCH
SCLK Pulse Width High
ns0tCSH
SCLK Rise to CS Rise Hold Time
CS Pulse Width High ns75tCS1
CS Rise to SCLK Rise Hold Time
CLOAD = 200pF ns200tDO1
SCLK Rise to DOUT Valid
Propagation Delay Time
ns200tDO2
SCLK Fall to DOUT Valid
Propagation Delay Time
ns10tCS0
SCLK Rise to CS Fall Delay Time
ns60tDS
SDI Setup Time ns0tDH
SDI Hold Time
UNITSMIN TYP MAXSYMBOLPARAMETER
1052034095
4095
Accuracy Guaranteed
To Code:From Code:
VDD
(V)
Typical Operating Characteristics
(VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL= 5kΩ, CL= 100pF, OS = AGND, TA = +25°C, unless otherwise noted.)
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0 1000 2000 3000 4000 5000
MAX5120
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
MAX5120/21 toc01
DIGITAL INPUT CODE
INL (LSB)
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0 1000 2000 3000 4000 5000
MAX5120
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
MAX5120/21 toc02
DIGITAL INPUT CODE
DNL (LSB)
2.490
2.495
2.500
2.505
2.510
-60 -20 20 60-40 0 40 80 100
MAX5120
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5120/21 toc03
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL= 5kΩ, CL= 100pF, OS = AGND, TA = +25°C, unless otherwise noted.)
200
250
300
350
400
450
500
-60 -20-40 0 20406080100
MAX5120
SUPPLY CURRENT vs. TEMPERATURE
MAX5120/21 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
(CODE = AAA HEX)
(CODE = 000 HEX)
250
300
400
350
450
500
4.0 4.5 5.0 5.5
(CODE = AAA HEX)
(CODE = 000 HEX)
6.0
MAX5120
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5120/21 toc05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-60 -20-40 0 20406080100
MAX5120
SHUTDOWN CURRENT vs. TEMPERATURE
MAX5120/21 toc06
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
4.093
4.094
4.095
4.096
4.097
4.098
4.099
-60 -20-40 0 20406080100
MAX5120
FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5120/21 toc07
TEMPERATURE (°C)
FULL-SCALE OUTPUT (V)
RL = 5kΩ
CL = 100pF
CS
5V/div
OUT
1V/div
5µs/div
MAX5120
DYNAMIC RESPONSE FALL TIME
MAX5120/21-10
0.1 1 10 100
MAX5120
FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5120/21 toc08
RL (kΩ)
FULL-SCALE ERROR (LSB)
0.50
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
CS
5V/div
OUT
1V/div
5µs/div
MAX5120
DYNAMIC RESPONSE RISE TIME
MAX5120/21-09
SCLK
2V/div
OUT
1mV/div
AC COUPLED
2µs/div
MAX5120
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5120/21-11
CS
2V/div
OUT
100mV/div
AC COUPLED
5µs/div
MAX5120
MAJOR CARRY TRANSITION
MAX5120/21-12
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________
7
-0.3
-0.1
-0.2
0.1
0
0.2
0.3
0 20001000 3000 4000 5000
MAX5121
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5120/21 toc-13
DIGITAL INPUT CODE
INL (LSB)
-0.25
-0.15
0.05
-0.05
0.15
0.25
200010000 3000 4000 5000
MAX5121
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5120/21 toc-14
DIGITAL INPUT CODE
DNL (LSB)
1.240
1.242
1.246
1.244
1.248
1.250
-60 -20 0-40 20 40 60 80 100
MAX5121
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5120/21 toc-15
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
100
150
300
250
200
350
400
-60 -20 0-40 20 40 60 80 100
MAX5121
SUPPLY CURRENT vs. TEMPERATURE
MAX5120/21 toc-16
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
CODE = AAA HEX
CODE = 000 HEX
2.036
2.038
2.042
2.040
2.044
2.046
-60 -20 0-40 20 40 60 80 100
MAX5121
FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5120/21 toc-19
TEMPERATURE (°C)
FULL-SCALE OUTPUT (V)
RL = 5kΩ
CL = 100pF
250
300
275
350
325
375
400
2.5 2.9 3.12.7 3.3 3.5 3.7
MAX5121
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5120/21 toc-17
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
CODE = AAA HEX
CODE = 000 HEX
0
0.2
0.6
0.4
0.8
1.0
-60 -20 0-40 20 40 60 80 100
MAX5121
SHUTDOWN CURRENT vs. TEMPERATURE
MAX5120/21 toc-18
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
CS
2V/div
OUT
500mV/div
2µs/div
MAX5121
DYNAMIC RESPONSE RISE TIME
MAX5120/21-21
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL= 5kΩ, CL= 100pF, OS = AGND, TA = +25°C, unless otherwise noted.)
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL= 5kΩ, CL= 100pF, OS = AGND, TA = +25°C, unless otherwise noted.)
CS
2V/div
OUT
500mV/div
2µs/div
MAX5121
DYNAMIC RESPONSE FALL TIME
MAX5120/21-22
SCLK
2V/div
OUT
500µV/div
AC COUPLED
2µs/div
MAX5121
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5120/21-23
CS
2V/div
OUT
100mV/div
AC COUPLED
5µs/div
MAX5121
MAJOR CARRY TRANSITION
MAX5120/21-24
Pin Description
PIN
Offset Adjust (Analog Input)OS1
FUNCTIONNAME
Analog Output Voltage. High impedance if part is in shutdown.OUT2
Power-Down Lockout (Digital Input)
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).
PDL
4
Reset Value Input (Digital Input)
1: Tie to VDD to select midscale as the output reset value.
0: Tie to DGND to select 0V as the output reset value.
RSTVAL3
Active-Low Chip-Select Input (Digital Input)
CS
6
Serial Clock InputSCLK8 Serial Data Input. Data is clocked in on the rising edge of SCLK.DIN7
Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.
CLR
5
Serial Data OutputDOUT10
Power-Down Input (Digital Input). Pulling PD high when PDL = VDD places the IC into shutdown with a
maximum shutdown current of 20µA.
PD12
User-Programmable Output (Digital Output)UPO11
Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5120) or +1.25V (MAX5121) nominal output, externally adjustable at REFADJ. In external reference
mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF.
REF14
Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.VDD
16
Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDD when using an
external reference.
REFADJ15
Analog GroundAGND13
Digital GroundDGND9
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
_______________________________________________________________________________________ 9
_______________Detailed Description
The MAX5120/MAX5121 12-bit, voltage-output DACs
are easily configured with a 3-wire serial interface. They
include a 16-bit data-in/data-out shift register and have
a double-buffered input consisting of an input register
and a DAC register. In addition, these devices employ
precision bandgap references and trimmed internal
resistors to produce a gain of 1.6384V/V, maximizing
the output voltage swing (Figure 1). The MAX5120/
MAX5121 output amplifier’s offset-adjust pin allows for
a DC shift in the DAC outputs. The full-scale output volt-
age is +4.095V for the MAX5120 and +2.0475V for the
MAX5121. These DACs are designed with an inverted
R-2R ladder network (Figure 2) that produces a weight-
ed output voltage proportional to the digital input code.
Internal Reference
Both the MAX5120 and MAX5121 use an on-board pre-
cision bandgap reference to generate an output volt-
age of +2.5V (MAX5120) or +1.25V (MAX5121). With a
low temperature coefficient of only 10ppm/°C (max),
the REF pin can source up to 100µA and may become
unstable with capacitive loads exceeding 100pF.
REFADJ can be used for minor adjustments (1%) to the
reference voltage. Use the circuits shown in Figure 3a
MAX5120
MAX5121
SR
CONTROL 16-BIT
SHIFT REGISTER
DECODE
CONTROL
INPUT
REGISTER
BANDGAP
REFERENCE REFERENCE
BUFFER
DAC
REGISTER DAC
2X
(1X)
DOUT
UPO
OUT
OS
R
0.6384R
GAIN = 1.6384X
4k
1.25V
AGND DGNDVDD
DIN SCLKCS
2.5V, (1.25V)
LOGIC
OUTPUT
CLR
PDL
RSTVAL
PD
12
REFADJ REF
( ) FOR MAX5121 ONLY
Figure 1. Simplified Functional Diagram
OUT
OS
R
0.6384R
SHOWN FOR ALL 1s ON DAC
*INTERNAL 2.5V (MAX5120) AND 1.25V (MAX5121)
OR EXTERNAL REFERENCE.
D0 D9 D10 D11
2R 2R 2R 2R 2R
RRR
REF*
AGND
Figure 2. Simplified Inverted R-2R DAC Structure
MAX5120/MAX5121
(MAX5120) and Figure 3b (MAX5121) to achieve these
adjustments. Connect a 33nF capacitor from REFADJ
to AGND to establish low-noise operation of the DAC.
Larger capacitor values may be used, but will result in
increased start-up delay. The time constant (τ) for the
start-up delay is determined by the REFADJ input
impedance of 4kΩand CREFADJ:
τ= 4kΩ·CREFADJ
External Reference
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
VDD. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper oper-
ation, do not exceed the input voltage range limits of
0V to (VDD - 1.4V) for VREF.
Determine the output voltage using the following equa-
tion (REFADJ = VDD; OS = AGND):
VOUT = [VREF ·(NB / 4096)] ·1.6384V/V
where NB is the numeric value of the MAX5120/
MAX5121 input code (0 to 4095), VREF is the external
reference voltage, and 1.6384V/V is the gain of the
internal output amplifier. The REF pin has a minimum
input resistance of 40kΩand is code-dependent.
Output Amplifier
The output amplifier of the MAX5120/MAX5121
employs a trimmed resistor-divider to set a gain of
+1.6384V/V and minimize the gain error. With its on-
board laser-trimmed +1.25V reference and the output
buffer gain, the MAX5121 achieves a full-scale output
of +2.0475V, while the MAX5120 provides a +4.095V
full-scale output with a +2.5V reference.
The output amplifier has a typical slew rate of 0.6V/µs
and settles to ±0.5LSB within 20µs, with a load of 5kΩ
in parallel with 100pF. Loads less than 1kΩmay result
in degraded performance.
The OS pin may be used to adjust the output offset volt-
age. For instance, to achieve a +1V offset, apply
-1.566V (Offset = -[Output Buffer Gain - 1] ·VOS) to OS
to produce an output voltage range from +1V to (1V +
VREF ·1.6384V/V). Note that the DAC’s output range is
still limited by the maximum output voltage specifica-
tion.
Power-Down Mode
The MAX5120/MAX5121 feature software- and hard-
ware-programmable (PD pin) shutdown modes that
reduce the typical supply current to 3µA. To enter soft-
ware shutdown mode, program the control sequence
for the DAC as shown in Table 1.
In shutdown mode, the amplifier output becomes high
impedance and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5120/MAX5121 to recall the output state prior to
entering shutdown when returning to normal operation
mode. To exit shutdown mode, load both input and
DAC registers simultaneously or update the DAC regis-
ter from the input register. When returning from shut-
down mode, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
10 ______________________________________________________________________________________
REFADJ
+5V
90k
100k 400k
33nF
MAX5120
REFADJ
+3V
15k
100k 400k
33nF
MAX5121
Figure 3a. MAX5120 Reference Adjust Circuit Figure 3b. MAX5121 Reference Adjust Circuit
Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low tran-
sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
Power-Down Input (PD)
Pulling PD high places the MAX5120/MAX5121 in shut-
down mode. Pulling PD low will not return the MAX5120/
MAX5121 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the seri-
al interface are required to exit power-down.
Serial-Interface Configuration
(SPI/QSPI/MICROWIRE/PIC16/PIC17)
The MAX5120/MAX5121 3-wire serial interface is com-
patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2-byte-
long serial input word contains three control bits, 12 data
bits in MSB-first format and one sub-bit, which is always
zero (Table 2).
The MAX5120/MAX5121’s digital inputs are double
buffered, which allows the user to:
•Load the input register without updating the DAC
register;
•Update the DAC register with data from the input
register;
•Update the input and DAC registers concurrently.
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 11
Load input register; DAC register unchanged.12-Bit DAC Data0 0
01
0
Update DAC register from input register; exit shutdown.XXXXXXXXXXXX0 1
11
0 Simultaneously load input and DAC registers; exit shutdown.12-Bit DAC Data0
UPO goes low (default).XXXXXXXXXXXX1 0
00
1
Mode 1; DOUT clocked out on SCLK’s rising edge.1XXXXXXXXXXX1 1
11
0 UPO goes high.XXXXXXXXXXXX1
No operation.XXXXXXXXXXXX0
16-BIT SERIAL WORD
Shutdown DAC (provided PDL = 1)
XXXXXXXXXXXX1
Mode 0; DOUT clocked out on SCLK’s falling edge (default).00XXXXXXXXXX1 1 1
C1 C0C2 FUNCTION
Table 1. Serial-Interface Programming Commands
X
= Don’t care
*
S0 is a sub-bit and is always zero.
DIN
SCLK
CS
MOSI
SCK
I/O
SPI/QSPI
PORT
(PIC16/PIC17)
SS
VDD
CPOL = 0, CPHA = 0
CHE = 1, CKP = 0, SMP = 0,
SSPM3–SSPMO = 0001
( ): PIC16/PIC17 ONLY
MAX5120
MAX5121
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
DIN
SCLK
CS
SK
SO
I/O
MICROWIRE
PORT
MAX5120
MAX5121
Figure 5. MICROWIRE Interface Connections
D11 ............... D0 S0*
0
0
0
0
0
0
0
0
0
MAX5120/MAX5121
The 16-bit input word may be sent in two 1-byte pack-
ets (SPI-, MICROWIRE- and PIC16/PIC17-compatible),
with CS low during this period. The control bits C2, C1,
and C0 (Table 1) determine:
•The clock edge on which DOUT is to be clocked out
via the serial interface;
•The state of the user-programmable logic output;
•The configuration of the device after shutdown.
The general timing diagram in Figure 6 illustrates how
data is acquired. CS must be low for the part to receive
data. With CS low, data at DIN is clocked into the regis-
ter on the rising edge of SCLK. When CS transitions
high, data is latched into the input and/or DAC registers,
depending on the setting of the three control bits C2,
C1, and C0. The maximum serial clock frequency guar-
anteed for proper operation is 10MHz for the MAX5120
and 6.6MHz for the MAX5121. Figure 7 depicts a more
detailed timing diagram of the serial interface.
Table 2. Serial Data Format
PIC16 with SSP Module and
PIC17 Interface
The MAX5120/MAX5121 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial port
(SSP) module. To establish SPI communication connect
the controller as shown in Figure 4 and configure the
PIC16/PIC17 as system master by initializing its syn-
chronous serial port control register (SSPCON) and
synchronous serial port status register (SSPSTAT) to
the bit patterns shown in Tables 3 and 4.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be transmitted synchronously and received simulta-
neously. Two consecutive 8-bit writings (Figure 6) are
necessary to feed the DAC with three control bits and
12 data bits plus one sub-bit. DIN data transitions on
the serial clock’s falling edge and is clocked into the
DAC on SCLK’s rising edge. The first 8 bits on DIN con-
tain the 3 control bits (C2, C1, and C0) and the first five
data bits (D11–D7). The second 8-bit word contains the
remaining bits (D6–D0), and the sub-bit S0.
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
12 ______________________________________________________________________________________
Control Bits MSB .... Data Bits ..... LSB
MSB ............................................................................... LSB
⇐ 16 BITS OF SERIAL DATA ⇒
D11................................D0C2, C1, C0
CS
SCLK
DIN
COMMAND
EXECUTED
9
816
1
C1
C2 S0
C0 D11 D10 D9 D8 D5 D4 D3 D2 D1 D0D7 D6
Figure 6. Serial-Interface Timing
SCLK
DIN
DOUT
tCS0 tCSS
tCL
tCH
tCP
tCSW
tCS1
tCSH
tDS tDO1 tDO2 tDH
CS
Figure 7. Detailed Serial-Interface Timing
S0
Sub-Bit
Serial Data Output
The contents of the internal shift register are output
serially on DOUT, which allows for daisy-chaining (see
Applications Information
) of multiple devices as well as
data readback. The MAX5120/MAX5121 may be pro-
grammed to shift data out on DOUT on the serial
clock’s rising edge (Mode 1) or falling edge (Mode 0).
The latter is the default during power-up and provides a
lag of 16 clock cycles, maintaining SPI, QSPI,
MICROWIRE, and PIC16/PIC17 compatibility. In Mode
1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
User-Programmable Output (UPO)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1),
thereby reducing the number of microcontroller I/O
ports required. During power-down, this output will
retain the last digital state before shutdown. With CLR
pulled low, UPO will reset to the default state after wake
up.
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 13
Table 3. Detailed SSPCON Register Contents
Receive Overflow Detection BitXSSPOV BIT6
BIT7
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.0CKP BIT4
BIT5
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI as serial-
port pins.
1SSPEN
0SSPM2 BIT2
BIT3
1SSPM0 BIT0
BIT1
CONTROL BIT
0SSPM1
Write Collision Detection BitXWCOL
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
MAX5120/MAX5121
SETTINGS
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects fCLK = fOSC / 16.
0SSPM3
X
= Don’t care
Table 4. Detailed SSPSTAT Register Contents
X
= Don’t care
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
1CKE BIT6
Buffer Full Status Bit
BIT7
Update Address
Read/Write Bit Information
Stop BitXP BIT4
BIT5 Data Address BitXD/A
XR/W BIT2
BIT3
XBF BIT0
BIT1
CONTROL BIT
XUA
SPI Data Input Sample Phase. Input data is sampled at the mid-
dle of the data output time.
0SMP
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPSTAT)
MAX5120/MAX5121
SETTINGS
Start BitXS
MAX5120/MAX5121
__________Applications Information
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
single step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than 1LSB, the
DAC guarantees no missing codes and is monotonic.
Offset Error
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Gain Error
Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
14 ______________________________________________________________________________________
0
2
1
4
3
7
6
5
000 010001 011 100 101 110
AT STEP
011 (1/2 LSB )
AT STEP
001 (1/4 LSB )
111
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
Figure 8a. Integral Nonlinearity Figure 8b. Differential Nonlinearity
0
2
1
4
3
6
5
000 010001 011 100 101
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1 LSB
1 LSB
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
0
2
1
3
000 010001 011
ACTUAL
DIAGRAM
IDEAL DIAGRAM
ACTUAL
OFFSET
POINT OFFSET ERROR
(+1 1/4 LSB)
IDEAL OFFSET
POINT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
Figure 8c. Offset Error Figure 8d. Gain Error
0
5
4
6
7
000 101100 110 111
IDEAL DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
IDEAL FULL-SCALE OUTPUT
ACTUAL
FULL-SCALE
OUTPUT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Unipolar Output
Figure 9 shows the MAX5120/MAX5121 setup for
unipolar, Rail-to-Rail®operation with a gain of
1.6384V/V. With its +2.5V internal reference, the
MAX5120 can generate a unipolar output range of 0V
to +4.095V. The MAX5121 produces a range of 0V to
+2.0475V with its on-board +1.25V reference. Table 5
lists example codes for unipolar output voltages. An off-
set to the output voltage can be achieved by simply
connecting the appropriate voltage to the OS pin, as
shown in Figure 10.
Bipolar Output
The MAX5120/MAX5121 can be configured for unity-
gain bipolar operation (OS = OUT) using the circuit
shown in Figure 11. The output voltage VOUT is thereby
given by the following equation:
VOUT = VREF ·[ {G ·(NB / 4096)} - 1]
where NB is the numeric value of the DAC’s binary
input code, VREF is the voltage of the internal (or exter-
nal) precision reference, and G is the overall gain. The
application circuit in Figure 11 uses a low-cost opera-
tional amplifier (MAX4162) external to the MAX5120/
MAX5121 in a unity-gain configuration. This provides
an overall circuit gain of 2V/V. Table 6 lists example
codes for bipolar output voltages.
Reset (RSTVAL) and Clear (
CLR
) Functions
The MAX5120/MAX5121 DACs offer a clear pin (CLR)
that resets the output to a certain value, depending
upon how RSTVAL is set. RSTVAL = DGND sets the
output to 0, and RSTVAL = VDD sets the output to mid-
scale when CLR is pulled low.
The CLR pin has a minimum input resistance of 40kΩin
series with a diode to the supply voltage (VDD). If the
digital voltage is higher than the supply voltage for the
part, a small input current may flow, but this current will
be limited to (VCLR - VDD - 0.5V) / 40kΩ.
Note: Clearing the DAC will also cause the part to exit
software shutdown (PD = 0).
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 15
MAX5120
MAX5121
DAC
GAIN = 1.638V/V
REF
OUT
OS
DGNDAGND
+5V/+3V
VDD R
0.6384R
Figure 9. Unipolar Output Circuit (OS = AGND) Using Internal
(1.25V/2.5V) or External Reference. With external reference,
pull REFADJ to VDD.
MAX5120
MAX5121
DAC
AGND DGND
REF REFADJ
OUT
OS VOS
+5V/+3V
VDD R
0.6384R
Figure 10. Circuit for Adding Offset to the DAC’s Output
AGNDDGND
R
MAX5120
MAX5121
DAC
REF OS
OUT
50k 50k
V-
V+
VDD
VOUT
+5V/+3V
0.6384R
MAX4162
Figure 11. Unity-Gain Bipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to VDD.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
TO OTHER
SERIAL DEVICES
MAX5120
MAX5121
DIN
SCLK
CS
MAX5120
MAX5121 MAX5120
MAX5121
DINDOUT DOUT DOUT
SCLK
CS
I II III
DIN
SCLK
CS
Figure 12. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
MAX5120/MAX5121
Daisy-Chaining Devices
Any number of MAX5120/MAX5121s can be daisy-
chained simply by connecting the serial data output pin
(DOUT) of one device to the digital input pin (DIN) of
the following device in the chain (Figure 12).
Another configuration allows several MAX5120/
MAX5121 DACs to share one common DIN signal line
(Figure 13). In this configuration, the data bus is com-
mon to all devices; data is not shifted through a daisy-
chain. However, more I/O lines are required in this
configuration, because each IC needs a dedicated CS
line.
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
16 ______________________________________________________________________________________
+VREF (2049 / 4096) ·1.6384
1000 0000 0001 +2.049V
+4.0950V +1.0245V
+2.0475V
+VREF (2047 / 4096) ·1.6384
0111 1111 1111 +2.047V
+2.048V +1.0235V
+1.024V +VREF (2048 / 4096) ·1.6384
1000 0000 0000
0V0000 0000 0000 0V
+1mV 0V
+0.5mV
+VREF (4095 / 4096) ·1.6384
1111 1111 1111
ANALOG OUTPUT
+VREF (1 / 4096) ·1.6384
0000 0000 0001
INTERNAL REFERENCE
MSB LSB MAX5120 MAX5121 EXTERNAL REFERENCE
VREF ·[ {2 · (2049 / 4096)} - 1]
1000 0000 0001 +1.2207mV
+2.49878V +610.35µV
+1.24939V
MSB LSB
VREF ·[ {2 · (2047 / 4096)} - 1]
0111 1111 1111 -1.2207µV
0V -610.35µV
0V
MAX5120
VREF ·[ {2 · (2048 / 4096)} - 1]
1000 0000 0000
MAX5121
-VREF
0000 0000 0000 -2.5V
-2.49878V -1.25V
-1.24939V
EXTERNAL REFERENCE
VREF ·[ {2 · (4095 / 4096)} - 1]
1111 1111 1111
ANALOG OUTPUT
VREF ·[ {2 · (14096)} - 1]
0000 0000 0001
INTERNAL REFERENCE
Table 5. Unipolar Code Table (Gain = 1.6384V/V)
Table 6. Bipolar Code Table for Figure 11
0
SUB-BIT
S0
0
0
0
0
0
DAC CONTENTS
0
SUB-BIT
SO
0
0
0
0
0
DAC CONTENTS
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 17
TO OTHER
SERIAL DEVICES
MAX5120
MAX5121
DIN
SCLK
CS
MAX5120
MAX5121
DIN
SCLK
CS
MAX5120
MAX5121
DIN
I II III
SCLK
CS
DIN
SCLK
CS1
CS2
CS3
Figure 13. Multiple Devices Share One Common Digital Input (DIN)
DAC OUT
MAX5120
MAX5121
10k
26k
OS
REF R
0.6384R
VDD
DGNDAGND
+5V/+3V
AC
REFERENCE
INPUT
500mVp-p
MAX495
+5V/+3V
Figure 14. External Reference with AC Components
Using an External Reference
with AC Components
The MAX5120/MAX5121 have multiplying capabilities
within the reference input voltage range specifications.
Figure 14 shows a technique for applying a sinusoidal
input to REF, where the AC signal is offset before being
applied to the reference input.
Power-Supply and Bypassing
Considerations
On power-up, the input and DAC registers are cleared
to either zero (RSTVAL = DGND) or midscale (RSTVAL
= VDD). Bypass the power supply with a 4.7µF capaci-
tor in parallel with a 0.1µF capacitor to AGND. Minimize
lead lengths to reduce lead inductance.
Layout Considerations
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. If noise becomes an
issue, shielding may be required.
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
18 ______________________________________________________________________________________
Package Information
___________________Chip Information
TRANSISTOR COUNT: 3308
SUBSTRATE CONNECTED TO AGND.
QSOP.EPS
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________
19
NOTES
MAX5120/MAX5121
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
NOTES