Freescale Semiconductor, Inc. Order this document by MC68160A/D MC68160A Freescale Semiconductor, Inc... Enhanced Ethernet Transceiver The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE-T Twisted Pair (TP) Interface media connections through external isolation transformers. It encodes NRZ data to Manchester data and supplies the signals which are required for data communication via 10BASE-T or AUI interfaces. The MC68160A gluelessly interface to the Ethernet controller contained in the MC68360 Quad Integrated Communications Controller (QUICC) device. The MC68160A also interfaces easily to most other industry-standard IEEE 802.3 LAN controllers. Prior to twisted pair data reception, Smart Squelch circuitry qualifies input signals for correct amplitude, pulse width, and sequence requirements. * ENHANCED ETHERNET INTERFACE TRANSCEIVER SEMICONDUCTOR TECHNICAL DATA Automatic Twisted Pair Wiring Polarity Fault Detection and Correction Option * Automatic Port Selection Option with Status Output * Driver Pre-emphasis for Twisted Pair Output Data * Crystal Controlled Clock Oscillator or External Clock Generator Option * Digital Phase-Locked-Loop (DPLL) Timing Recovery and Data Decoding * Standby Mode with Reduced Power Consumption * Twisted Pair Signal Quality Error (Heartbeat) Test Option * Diagnostic Local Loop Back Option * Transmit, Receive and Collision Detection Status Output * Full-Duplex Operation Option on Twisted Pair Port * Twisted Pair Jabber Detection and Status Output * Link Integrity Testing and Status Output 52 1 FB SUFFIX PLASTIC PACKAGE CASE 848D (LQFP-52) ORDERING INFORMATION Device MC68160AFB The sale and use of this product is licensed under technology covered by one or more Digital Equipment Corporation patents. Operating Temperature Range Package TA = 0 to + 70C LQFP Rev 1 For More Information On This Pro Go to: www.freescale.com Freescale Semiconductor, Inc. MC68160A Figure 1. 10Base-T Interface Block Diagram RX RCLK Manchester Decoder Data Receiver Mux ARX+ MFILT Freescale Semiconductor, Inc... CLSN TXLED Pulse Conditioner Noise Reject Filter Mux ARX- Pulse Conditioner Noise Reject Filter Collision Detect Mux Pulse Conditioner Manchester Encoder X1 X2 ATX+ Mux 20 MHz Osc Receiver Mux /2 TCLK ACX+ ACX- ATX- TENA TX CS0 CS1 CS2 TPEN APORT TPAPCE TPSQEL TPFULDL LOOP Carrier Detect Jabber Control Driver Pre-emphasis Control Link Pulse Control Mode Select TPJABB TPTX+ TPTX- TPLIL AUI INTERFACE SIA INTERFACE RXLED RENA CLLED Twisted Pair Polarity Error Control Collision Detector Control Receiver Squelch Squelch Test Circuit TPSQEL TPRX- TPRX+ TPPLR This device contains 20,000 active transistors. For More Information On This Pro Go to: www.freescale.com ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Enhanced Ethernet Serial Transceiver Table 1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Controller Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and Frequency Multiplier Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Indicator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 5 5 6 6 Table 2. Controller Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Controller Independent Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Freescale Semiconductor, Inc... Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supply DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TTL/CMOS Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Twisted Pair Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AUI Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External Clock Input (X1) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Phase Locked Loop Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (Fujitsu Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (Fujitsu Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (National Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (National Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Transmit Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Transmit Jabber Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Transmit Signal Quality Error Test Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Receive Link Integrity Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Collision Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Full Duplex Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Transmit Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 14 14 15 15 16 16 18 20 20 21 21 23 23 24 24 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 26 26 26 26 26 26 26 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Selection of Crystal and External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Filter and Transformer Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Transformer Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 3 27 27 27 27 Freescale Semiconductor, Inc. MC68160A Table 1. Pin Function Descriptiont Pin(s) Symbol Type Name/Function Freescale Semiconductor, Inc... CONTROLLER INTERFACE 1 RENA O TTL/CMO Receive Enable Output: Indication of the presence of network activity, synchronous to RCLK. In the standby mode, RENA is driven to the high impedance state. 2 RX O TTL/CMOS Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation, 100 ms should be allowed before attempting to read data processed by the MC68160A, B and C. This delay is needed to insure that the receive phase locked loop is properly synchronized with incoming data. In the standby mode, RX is driven to the high impedance state. 48 TCLK O TTL/CMOS Transmit Clock Output CMOS/TTL Output: TCLK provides a symmetrical clock signal at 10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to the high impedance state. 49 TENA I TTL 50 RCLK O TTL/CMOS Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high impedance state. 51 CLSN O TTL/CMOS Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and ACX- terminals which meet threshold and pulse width requirements. In the TP mode, indicates simultaneous transmit and receive activity, a heartbeat (SQE Test) signal was generated, or the jabber timer has expired. In the standby mode, CLSN is driven to the high impedance state. 52 TX I TTL Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to be Manchester encoded. In the standby mode, TX is driven to the high impedance state. 21 22 ACX- ACX+ I AUI Differential Collision Inputs: These inputs are connected to a pair of internally biased line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the line activity. Signals at ACX+/- have no effect on data path functions. 23 24 ARX- ARX+ I AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the line activity, and a data receiver with no offset for Manchester Data reception. 25 26 ATX- ATX+ O AUI Differential Transmit Outputs : This line pair is intended to operate into terminated transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is previously asserted, Manchester encoded data is outputted at ATX+/-. When operating into a 78 terminated transmission line, signaling meets the required output levels and skew for IEEE-802.3 drop cables. When the 10BASE-T port is automatically or manually selected, the AUI outputs are driven to a low power standby state in which the outputs deliver a balanced high state voltage. Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission on the active port. An internal pull-down resistor is provided so that the input is low under no connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at the conclusion of a reset operation, it must first be deasserted and then reasserted before data transmission can occur. In the standby mode, TENA is driven to the high impedance state. AUI INTERFACE TWISTED PAIR INTERFACE 31 32 TPRX- TPRX+ I Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with Smart Squelch capability which only allows differential receive data to pass as long as the input amplitude is greater than a minimum signal threshold level and a specific pulse sequence is received. This assures a good signal to noise ratio while the signal pair is active by preventing crosstalk and impulse noise conditions from activating the receive function. 36 37 TPTX- TPTX+ O Twisted Pair Differential Transmitter Outputs: These lines have pre-distortion drive capability and are intended to drive terminated twisted pair transmission lines. When the AUI port is manually selected, the 10BASE-T outputs are driven to a low power standby state in which the outputs deliver a balanced high state voltage. However, when the AUI port is automatically selected, the 10BASE-T outputs remain active. NOTE: The sense of the controller interface pins will change, depending on the controller selected. For More Information On This Pro Go to: www.freescale.com ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Table 1. Pin Function Description (continued) Pin(s) Symbol Type Name/Function OSCILLATOR AND FREQUENCY MULTIPLIER 12 MFILT C Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be attached to this pin. 16 X1 I/C CMOS Oscillator Inverter Input and Crystal Connection Point: When connected for crystal oscillator operation, the frequency of the clock which appears at TCLK is half that of the crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an external 20 MHz CMOS compatible clock generator. 17 X2 O/C CMOS Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by an external CMOS Clock generator. 3 4 5 CS0 CS1 CS2 I TTL Mode Select: The logic states applied to these pins select the appropriate interface for the desired IEEE-802.3 controller or enable the standby mode. When the standby mode is selected, the MC68160A power supply current is greatly reduced. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. 6 LOOP I TTL Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be Manchester encoded and then looped back through the Manchester decoder, appearing at the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP) or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI port transmits data from the controller while diagnostic loopback is selected. Likewise, the controller interface receives data neither from the TP nor the AUI receivers while in this mode. The polarity fault detection and link integrity functions are not inhibited by the diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is delivered following each transmission to simulate the twisted pair SQE test. 9 APORT I TTL Automatic Port Selection Enable: When high, MC68160A will automatically select the TP or AUI port based on the presence or absence of valid link beats or frames at the TP receive input. If the AUI port is automatically selected, the MC68160A will continue to produce link pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to resume normal operation. The power consumption is minimized in the circuitry associated with the unselected port. 27 TPSQEL I TTL Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the internal TP collision detect circuitry after each transmit operation to the TP media. This function provides a simulated collision to as much of the MC68160A collision detect circuitry as possible without affecting the attached twisted pair channel. A normal SQE test results in a high logic state at the CLSN controller interface pin which begins 6 to 16-bit times after the last transition of a transmitted signal and continues for 5 to 15-bit times. (When the AUI port is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to the controller via the MC68160A ACX+/- receive inputs) 28 TPFULDL I TTL Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit and receive operation on the twisted pair port without an indicated collision. This pin is not to be asserted with LOOP as a test mode is enabled that disrupts normal operation. 29 TPAPCE I TTL Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is indicated on TPPLR. 46 TPEN I/O TTL (TTL/CMOS) Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is manually selected, the MC68160A will not produce link pulses for the TP port. Freescale Semiconductor, Inc... MODE SELECT If APORT is high, TPEN is an output which will indicate which port has been automatically selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink 10 mA in the low output state and source 10 mA in the high output state. (See Pin 9 Description.) Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to resume normal operation. The power consumption is minimized in the circuitry associated with the unselected port. In the standby mode, this pin is driven to the high impedance state. ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 5 Freescale Semiconductor, Inc. MC68160A Table 1. Pin Function Description (continued) Pin(s) Symbol Type Name/Function Freescale Semiconductor, Inc... STATUS INDICATOR 40 TXLED O TTL/CMOS Transmit Status LED Driver Output: This pin indicates the transmit status of the currently selected TP or AUI port. When there is no transmit activity detected, an internal pull-up takes this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50% duty cycle. In the standby mode, this output is driven to the high impedance state. 41 RXLED O TTL/CMOS Receive Status LED Driver Output: This pin indicates the receive status of the currently selected TP or AUI port. When there is no receive activity detected, an internal pull-up takes this pin to its normal off (high) state. When receive activity is detected, the LED driver turns on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50% duty cycle. In the standby mode, this output is driven to the high impedance state. 42 CLLED O TTL/CMOS Collision Status LED Driver Output: This pin indicates the collision status of the currently selected TP or AUI port. When there is no collision activity detected, an internal pull-up takes this pin to its normal off (high) state. When collision activity is detected, the LED driver turns on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50% duty cycle. In the standby mode, this output is driven to the high impedance state. 43 TPLIL O TTL/CMOS Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port is selected. In the standby mode, this output is also driven to the high impedance state. 44 TPPLR O TTL/CMOS Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the Twisted Pair Receiver Inputs (TPRX+, TPRX-) are reversed, TPPLR will be driven to the low logic state to indicate the fault. TPPLR remains low when the MC68160A, AB and AC has automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this output will be driven to the high logic state. When the AUI mode is selected this output is driven to the high impedance state. In the standby mode, this output is also driven to the high impedance state. 45 TPJABB O TTL/CMOS Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the TPTX+/- outputs. (Jabber condition also causes CLLED to be driven alternately to the high and low output levels). TPJABB is driven to the low output state when no jabber condition is present. When the AUI mode is selected this output is driven to the high impedance state. In the standby mode, this output is also driven to the high impedance state. POWER SUPPLY AND GROUND 10 VDDDIV Frequency Divider Supply Pin 11 13 VDDFM GNDFM Frequency Multiplier Supply and Ground Pins 14 15 GNDVCO VDDVCO Voltage Controlled Oscillator Ground and Supply Pins 20 GNDSUB Substrate Ground Pin 7 8 18 19 VDDDIG GNDDIG VDDDIG GNDDIG Digital Supply and Ground Pins 30 33 VDDANA GNDANA Analog Supply and Ground Pins 34 35 38 39 GNDPWR VDDPWR VDDPWR GNDPWR Power Supply and Ground Pins 47 GNDCTL Controller Interface Ground Pin NOTE: Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC. For More Information On This Pro Go to: www.freescale.com ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Freescale Semiconductor, Inc... Table 2. Controller Interface Selection Motorola Transceiver MC68160A (EEST) Motorola Controller2 MC68360 (QUICC) Intel4 Controllers 82586, 82590, 82593, 82596 Fujitsu4 Controllers 86950 (Etherstar) 86960 (NICE) National4 Controllers 8390, 83C690, 83932B (SONIC) CS0 CS1 CS2 1 1 0 0 1 0 1 0 0 0 0 0 Pin Pin Sense Pin Sense Pin Sense Pin Sense TCLK TCLK High TXC Low TCKN Low TXC High TX TX High TXD High TXD High TXD High TENA TENA High RTS Low TEN High TXE High RCLK RCLK High RXC Low RCN Low RXC High RX RX High RXD High RXD High RXD High RENA RENA High CRS Low XCD High CRS High CLSN CLSN High CDT Low XCOL Low COL High LOOP1 N.A. High LPBK Low LBC High LPBK High NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used. 2. The Motorola controller interface contained in the MC68360 (QUICC) is compatible with the AMD 7990 (LANCE) and 79C900 (ILACC) controllers. 3. The pin sense is shown from the perspective of the identified controller pin. 4. Supported only by MC68160A. Table 3. Controller Independent Mode Selection Pin Standby Mode Reserved Reserved Reserved CS0 CS1 CS2 1 1 1 0 1 1 1 0 1 0 0 1 NOTE: In standby mode, the MC68160A consumes less power supply current than in any other mode. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. When the standby mode is deasserted, an internal reset pulse of approximately 6.0 s duration is generated. Following a period of operation in the standby mode, the time required to insure stable data reception is approximately 100 ms. Figure 2. Applications Block Diagram ATX+ ATX+ ATX- ATX- ARX+ TCLK ARX- TX ARX+ Pulse Transformers ARX- ACX+ ACX+ ACX- ACX- TPTX+ TPTX+ DB-15 Connector TENA LAN Controller RCLK MC68160A RX RENA CLSN TPTX- TPRX+ TPRX- Filters and Pulse Transformers ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com TPTX- TPRX+ RJ-45 Connector TPRX- 7 Freescale Semiconductor, Inc. MC68160A ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Characteristic Symbol Min Max Unit Storage Temperature Range Tstg - 65 150 C Power Supply Voltage Range Analog Digital VDDA VDDD - - 7.0 7.0 V V - 0.5 VDD + 0.5 V - 0.5 6.0 - 6.0 6.0 Voltage on any TTL compatible input pin with respect to Ground Voltage on TPRX, ARX, or ACX input pins with respect to Ground Differential Voltage on TPRX, ARX, or ACX Input Pins Freescale Semiconductor, Inc... NOTE: VDIFF V Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. Functional operation of the device is not implied at these or any other conditions in excess of those indicated in the operation sections of this data sheet. Exposure to Absolute Maximum Ratings conditions for extended periods can adversely affect device reliability. RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Min Max Unit VDD 4.75 5.25 V Power Supply Ripple (20 kHz to 100 kHz) - - 50 mV Power Supply Impulse Noise (Either Polarity) - - 100 mV TA 0 70 C ARX/ACX Input Differential Rise and Fall Time (see Figure 39) t260 2.0 10 ns ARX Pair Idle Time after Transmission (see Figure 39) t265 8.0 - s Power Supply Voltage Range Ambient Operating Temperature Range ESD Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500 capacitance - 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 V Human Body Model. DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges.) Characteristic Symbol Test Conditions Min Typ Max Unit - - - - 4.4 V IDD - Standby Mode - - 145 - 200 5.0 mA POWER SUPPLY Undervoltage Shutdown Threshold Power Supply Current For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A DC ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 5.0 V 5%. Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.) Characteristic Symbol Test Conditions Min Max - 2.0 0.8 - - 10 - - - +200 - 20 10 - 3.0 1.0 - 0 V < VI < VDD - 100 IOL = 4.0 mA IOL = 10 mA - - 0.45 0.45 IOH = - 500 A IOH = - 10 mA IOH = - 4.0 mA 3.9 3.9 2.4 - - - Unit TTL COMPATIBLE INPUTS TTL Compatible Input Voltage Low State High State - VIL(TTL) VIH(TTL) Input Current TTL Compatible Input Pins (Note 1) Input Current TENA TTL Compatible Input Pin: with Pull-Down Resistor IIH IIL with Pull-Down Resistor removed in Standby Mode 0 V < VI < VDD IIH IIL IIH & IIL V A CMOS COMPATIBLE INPUTS Freescale Semiconductor, Inc... CMOS Compatible Input Voltage Low State High State Input Current (Pin X1) - VIL(CMOS) VIH(CMOS) IIH & IIL V A TTL/CMOS COMPATIBLE OUTPUTS TTL/CMOS Compatible Output Voltage Low State (Note 2) Low State (Note 3) VOL TTL/CMOS Compatible Output Voltage High State (Note 4) High State (Note 5) High State (Note 2) VOH Three State Output Leakage Current IOZ 0 V VOZ VDD - 10 A Symbol Test Conditions Min Max Unit VITP VITPSQ VBCMTP - 1.5 4.3 V Note 10 270 390 mV Note 9 1.8 3.2 V - 1000 - - 2.5 - k 2.2 1.56 2.8 1.98 Characteristic V V TWISTED PAIR RECEIVER INPUTS Input Voltage Range (DC + AC) Differential Input Squelch Threshold Voltage Common Mode Bias Generator Voltage Common Mode Input Resistance Differential Input Resistance RCMTP RDIFFTP TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage Pre-Emphasis Level Signal Level Common Mode Output Voltage Range Common Mode Output Voltage in Standby Mode Note 7 V VODFTPP VODFTPS VOCMTP Note 6 0 4.0 V VOCMTPSB IOH = -100 A VDD - 1.0 VDD V NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). 4. TPPLR, TPLIL, CLLED, TXLED and RXLED. 5. TPJABB and TPEN (In Output Mode). 6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/- pins of the device. 7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/- pins of the device. 8. Measured directly on the TPTX+/- pins of the device. 9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/- pins of the device. 10. The Common Mode Input Voltage is between 1.8 V and 3.2 V. ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 9 Freescale Semiconductor, Inc. MC68160A DC ELECTRICAL CHARACTERISTICS (continued) (TA = 25C, VCC = 5.0 V 5%. Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.) Characteristic Symbol Test Conditions Min Max Unit Differential Output Voltage IDLE Mode Open Circuit VODFTPI VODFTPO Note 6 Note 8 - - 50 5.25 mV V Differential Output Impedance TRANSMISSION Mode IDLE Mode RODFTPT RODFTPI 12 8.0 28 29 Common Mode Output Impedance TRANSMISSION Mode IDLE Mode ROCMTPT ROCMTPI 3.0 1.0 7.0 10 Freescale Semiconductor, Inc... TWISTED PAIR TRANSMITTER OUTPUTS Note 8 Note 8 NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). 4. TPPLR, TPLIL, CLLED, TXLED and RXLED. 5. TPJABB and TPEN (In Output Mode). 6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/- pins of the device. 7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/- pins of the device. 8. Measured directly on the TPTX+/- pins of the device. 9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/- pins of the device. 10. The Common Mode Input Voltage is between 1.8 V and 3.2 V. DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges.) Characteristic Symbol Test Conditions Min Max Unit AUI RECEIVER INPUTS Input Voltage Range (DC + AC) VIA - 1.0 4.2 V Differential Mode Input Voltage Range VIDFA - 318 1315 mV Differential Input Squelch Threshold Voltage VIASQ - - 275 -175 mV Common Mode Input Resistance RICMA 1.0 V < VICMA < 4.2 V 1.5 - k Differential Input Resistance (ARX, ACX Inputs) RIDFA 1.0 V < VICMA < 4.2 V 318 mV < VIDMA < 1315 mV 5.0 - k 1.0 1.0 VDD - 2.0 4.2 4.2 VDD - 1.2 - 600 40 1315 - 4.0 - 150 AUI TRANSMITTER OUTPUTS Common Mode Output Voltage IDLE Mode ACTIVE Mode STANDBY Mode VOCMIA VOCMAA VOCMSA Figure 6 Differential Output Voltage IDLE Mode ACTIVE Mode VODFIA VODFAA IO = -100 A V Figure 6 Differential Output Load Current IDLE Mode IODFIA Output Short Circuit Current IODSA mV Figure 7 Output Short Circuited to VDD or GND For More Information On This Pro Go to: www.freescale.com mA mA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 3. Test Load B1 Device V1 39 RCM 1.0 k 39 Figure 4. Test Load B2 + VCMD - Device 39 100 39 Figure 5. Test Load B3 39 Device Freescale Semiconductor, Inc... 39 NOTE: RCM 10 k + VCMD - A total of 50 per driver output is required for proper series line termination. This is realized with the 39 external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance. Figure 6. AUI Common Mode Termination Figure 7. AUI Differential Output Short Circuit Current - 39 IO VCM VDIFF IOD 39 + ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 11 Freescale Semiconductor, Inc. MC68160A AC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended temperature and power supply voltage ranges.) Characteristic Symbol Min Max Unit t1 t2 t3 t4 t5 49.995 - - 20 20 50.005 5.0 5.0 30 30 ns t7 - 100 ms TCLK Cycle Time TCLK High Time TCLK Low Time TCLK Rise and Fall Time t10 t11 t12 t13 99 45 45 - 101 55 55 8.0 ns TX Setup Time to TCLK TX Hold Time to TCLK t14 t15 20 0 - - ns TENA Setup Time to TCLK TENA Hold Time to TCLK t16 t17 20 0 - - ns t20 t21 t22 t23 90 42 47 - - - 55 8.0 ns t24 t24.1 10 70 - - ns RCLK Delay from RENA RX Delay from RENA t25 t26 - - 650 600 ns RENA Deassertion Delay from RCLK (See Figure 12) t27 10 30 ns EXTERNAL CLOCK INPUT (X1) Cycle Time (Note 1) (See Figure 8) Fall Time Rise Time Low Time High Time RECEIVE PHASE-LOCKED-LOOP SWITCHING Stabilization Time Freescale Semiconductor, Inc... CONTROLLER TRANSMIT SWITCHING (MOTOROLA MODE) CONTROLLER RECEIVE SWITCHING RCLK Cycle Time RCLK High Time RCLK Low Time RCLK Rise and Fall Time RX Hold Time from RCLK RX Set-Up Time to RCLK NOTES: 1. To meet IEEE-802.3 specifications. 2. Load on specified output is 20 pF to ground, unless otherwise noted. 3. = Rising Edge Figure 8. X1 Input Voltage Levels for Timing Measurements t1 t2 4.0V 1.5V 0V 3.6V 1.5V t5 3.6V 1.5V 0.4V 0.4V t4 t3 For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 9. Receive Phase-Locked-Loop Switching CS0 D CS1 D CS2 1.5V TPRX t7 1.5V RENA Freescale Semiconductor, Inc... NOTE: CS0 * CS1 * CS2 is the logical AND operation and refers to the pins not at Logic 1. Figure 10. Transmit Timing (Motorola Mode) t13 t11 1.5V 1.5V 3V t13 0.8V 3V 1.5V 1.5V 1.5V 1.5V TCLK t10 t16 t17 t12 1.5V 1.5V TENA t14 t15 TX 1.5V 1.5V Figure 11. Receive Timing (Motorola Start of Frame) 1.5V t23 RENA t23 t22 t21 t25 1.5V 3V 0.8V RCLK t26 RX 3V 1.5V 0.8V t24.1 1.5V t24 1.5V 1.5V 1.5V t20 1.5V OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 13 Freescale Semiconductor, Inc. MC68160A Figure 12. Receive Timing (Motorola End of Frame) RENA 1.5V t27 1.5V RCLK RX Last Bit Freescale Semiconductor, Inc... CONTROLLER TRANSMIT SWITCHING (Intel Mode - Support by MC68160A Only) Characteristic Symbol Min Max Unit TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time t40 t41 t42 99 40 - 101 - 5.0 ns TXD Setup Time to TXC TXD Hold Time to TXC t43 t44 20 0 - - ns RTS Setup Time to TXC RTS Hold Time to TXC t45 t46 20 0 - - ns t80 t81 t82 t83 90 45 40 - - 55 - 5.0 ns t85 t85.1 t86 50 35 12 - - 30 ns CONTROLLER RECEIVE SWITCHING RXC Cycle Time RXC High Time RXC Low Time RXC Rise and Fall Time RXD Hold Time from RXC RXD Set-Up Time to RXC CRS Delay from RXC NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. = Rising Edge = Falling Edge Figure 13. Transmit Timing (Intel) t42 TXC 3V t42 0.8V t41 3V 1.5V 1.5V 1.5V 1.5V t41 t45 RTS 1.5V 1.5V t40 t46 1.5V 1.5V t43 t43 t44 TXD 1.5V 1.5V 1 0 0 0 1.5V 1 For More Information On This Pro Go to: www.freescale.com Last Bit 1/0 OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 14. Receive Timing (Intel) CRS 1.5V t81 t82 1.5V 1.5V t85.1 t85 t86 t80 1.5V 1.5V .8V 3V RXC t83 3V t83 RXD Freescale Semiconductor, Inc... 1.5V 1.5V CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode - Supported by MC68160A Only) Symbol Min Max Unit TCKN Cycle Time TCKN High and Low Time TCKN Rise and Fall Time t90 t91 t92 99 45 - 101 55 8.0 ns TXD Setup Time to TCKN TXD Hold Time to TCKN t93 t94 20 0 - - ns TEN Setup Time to TCKN TEN Hold Time to TCKN t95 t96 20 0 - - ns t100 t101 t102 t103 90 40 45 - - - 55 8.0 ns t104 t104.1 t105 50 35 - - - 600 ns t106 0 - ns Characteristic CONTROLLER RECEIVE SWITCHING RCKN Cycle Time RCKN High Time RCKN Low Time RCKN Rise and Fall Time RXD Hold Time from RCKN RXD Set-Up Time RCLK RCKN Delay from XCD XCD Deassertion Delay from RCKN (See Figure 17) NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. = Rising Edge = Falling Edge Figure 15. Transmit Timing (Fujitsu) t91 t90 TCKN 1.5V 1.5V 1.5V 1.5V t95 t91 3V 0.8V t92 0.8V t92 1.5V 1.5V t96 1.5V TEN t93 1.5V t94 1.5V TXD OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 15 Freescale Semiconductor, Inc. MC68160A Figure 16. Receive Timing (Fujitsu Start of Frame) 1.5V XCD t105 t101 1.5V 1.5V 1.5V t104.1 t102 Freescale Semiconductor, Inc... RXD 1.5V t100 3V 0.8V RCKN t104 t103 1.5V 1.5V t103 1.5V Figure 17. Receive Timing (Fujitsu End of Frame) XCD 1.5V t106 1.5V RCKN RXD CONTROLLER TRANSMIT SWITCHING (National Mode - Supported by MC68160A Only) Characteristic Symbol Min Max Unit TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time t110 t111 t112 99 45 - 101 55 8.0 ns TXD Setup Time to TXC TXD Hold Time to TXC t113 t114 20 0 - - ns TXE Setup Time to TXC TXE Hold Time to TXC t115 t116 20 0 - - ns t120 t121 t122 t123 90 40 40 - - - 60 8.0 ns t124 t124.1 t125 50 35 - - - 600 ns CRS Deassertion Delay from RXC t126 0 15 ns RXC continuing beyond CRS t127 5.0 - cycles CONTROLLER RECEIVE SWITCHING RXC Cycle Time RXC Low Time RXC High Time RXC Rise and Fall Time RXD Hold Time from RXC RXD Set-Up Time from RXC RXC Delay from CRS NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. = Rising Edge = Falling Edge For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 18. Transmit Timing (National) t111 1.5V t110 1.5V 1.5V 3V 0.8V 0.8V 1.5V TXC t116 t111 t112 t115 t112 1.5V 1.5V TXE t113 Freescale Semiconductor, Inc... 1.5V t114 1.5V TXD Figure 19. Receive Timing (National) 1.5V 1.5V CRS t125 t126 t122 t127 t120 RXC 1.5V 1.5V t121 3V 0.8V t123 t123 1.5V 1.5V 1.5V t124.1 t124 1.5V RXD ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 17 Freescale Semiconductor, Inc. MC68160A TP TRANSMIT SWITCHING Symbol Min Typ Max Unit VOCMTP - - 50 mVrms TX to TPTX Steady State Propagation Delay (Note 2) (See Figure 24) Bit Duration Center-to-Center Half-Bit Cell Duration Center-to-Boundary t130 t131 t132 - 98 48 - - - 200 102 52 ns TENA Assert to RENA Assert Delay (Note 7) (See Figure 24) t133 - - 400 ns Internal Loopback Delay from TX to RX (Note 7) (See Figure 24) t134 - - 650 ns TPTX End of Packet Hold Time from last positive TPTX Signal Edge to +585 mV Differential Output Level (Note 5) (See Figure 25) t135 250 - 400 ns TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25) t136 - 45-58 - ns RENA Deassert Delay from TENA Deassert when Receiver is inactive Motorola Mode Fujitsu Mode National Mode Intel Mode (Note 4) (See Figure 26) t137 t137 t137 t138 250 250 250 250 - - - - 450 450 450 450 TPTX Data-to-Link Test Pulse (Note 2) (See Figure 27) TPTX Link Test Pulse Width (Note 2) TPTX Link Test Pulse Decay-to-Idle Condition (Note 1) TPTX Link Test Pulse to next Link Test Pulse (Note 2) t139 t140 t141 t142 8.0 80 80 8.0 - - - - 24 240 240 24 Characteristic Freescale Semiconductor, Inc... TPTX Common Mode AC Output Voltage (Note 3) NOTES: 1. 2. 3. 4. 5. 6. 7. ns ms ns ns ms Measured differentially across the output of Test Load A which is connected directly to the TPTX+/- pins of the device. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/- pins of the device. Measured across the output of Test Load C which is connected directly to the TPTX+/- pins of the device. Same as t137 except the logic states for TENA and RENA are inverted. Measured across the output of Test Load B shown in Figure 21. Measured at the +/-90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.) Load on specified output is 20 pF to ground. Figure 20. Test Load A Figure 21. Test Load B 100H 1.0H 39 39 100pF 39 100pF 1.0H 100 VOUT Device Figure 22. Test Load C 100 39 Figure 23. Test Load D 200H 200H 39 Vout 39 47.5 39 47.5 39 100 49.9 NOTE: VOUT VCM A total of 50 per driver output is required for proper series line termination. This is realized with the 39 external resistors shown in Figures 20 to 23, together with the internal driver output resistance. For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 24. TPTX Transmit Timing (Start of Frame) Switching X1 1.5V TCLK TENA 1.5V 1 TX 1.5V 0 1 0 0 1 1 t133 1.5V RENA t134 1.5V Freescale Semiconductor, Inc... RX TPTX +/- Differential (Logic Levels) 1 1 0 1 0 1 0 0 0 0 t130 TPTX +/- Differential (Pre-Emphasis) 1 0 1 t131 0V 1 0 1 0 1 1 t132 1 1 Figure 25. TPTX Transmit Timing (End of Frame) Switching t136 90% t135 90% +585mV +585mV TPTX +/- Differential Figure 26. RENA Deassert Delay from TENA t137 TENA 1.5V RENA 1.5V OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 19 Freescale Semiconductor, Inc. MC68160A Figure 27. TPTX+/- Link Pulse Timing t142 t141 t140 t139 585mV 585mV 585mV Freescale Semiconductor, Inc... 50mV TP TRANSMIT JABBER SWITCHING Characteristic Symbol Min Max Max Length of Transmission before Assertion of TPJABB to indicate Jabber Condition CLSN to indicate Jabber Condition t160 t161 20 20 60 60 Time from End of Jabber Condition to Deassertion: of TPJABB of CLSN t162 t163 500 500 750 750 CLSN (Signal Quality Error Test) (See Figure 29) A Assertion ti ffrom llastt positive iti TPTX edge d Deassertion from last positive ositive TPTX edge Pulse Width t170 t171 t172 0.6 0 6 - 0.5 1.6 1 6 3.1 1.5 TPSQEL Disable Delay Time (See Figure 29) t173 - 40 Unit ms ms TP TRANSMIT SIGNAL QUALITY ERROR TEST SWITCHING NOTE: s ns The load attached to the specified output is a 20 pF capacitor connected to ground, unless otherwise noted. Figure 28. TPJABB Switching TPTX (Differential) 585mV -585mV t160 t162 1.5V 1.5V TPJABB t161 t163 1.5V 1.5V CLSN For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 29. TPTX SQE (CLSN) Timing (End of Frame) TPTX+/- 2V 1.5V TPSQEL t173 t171 t170 t172 1.5V 1.5V Freescale Semiconductor, Inc... CLSN TP RECEIVE SWITCHING Symbol Min Max Unit VIDFSTP 0 |264| mV Positive or Negative Differential Input Pulse Width for Conditional Receive Unsquelch (See Figure 31) t180 20 30 ns TPRX to RCLK Bit Loss at start of packet (See Figure 32) t181 - 10 Bits TPRX to RCLK Steady State Propagation Delay (See Figure 32) t182 - 400 ns TPRX to RX Start Up Delay (See Figure 32) t183 - 1.5 s TPRX held high from last valid positive transition (See Figure 33) t186 230 - ns RENA Deassertion Delay from last valid positive transition of TPRX Pair (See Figure 33) t187 - 350 ns Required Pulse Width Range to be recognized as a Link Pulse (Note 2) t200 50 200 ns Last TPRX activity to high state TPLIL Output (Receive Link Loss Timeout Interval) t201 100 150 ms t202 t203 3.0 100 7.0 150 Characteristic Differential Input Voltage Range Unconditional Squelch (Note 1) (1.8 V < Input Common Mode Voltage < 3.2 V) TP RECEIVE LINK INTEGRITY SWITCHING Receive Link Beat Separation Minimum Range (Note 3) Maximum Range (Note 4) NOTES: 1. 2. 3. 4. ms Measured with Test Load H attached to the receive pins. Measured at the receive pins. Link beats closer in time to this range of values are considered noise, and are rejected. Link beats further apart in time than this range of values are not considered consecutive, and are rejected. Figure 30. Test Load H 1.0H Figure 31. TPRX Input Switching 200H +330mV t180 100 100pF 100pF Line 0mV TPRX 1.0H -330mV OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com t180 21 Freescale Semiconductor, Inc. MC68160A Figure 32. TPRX Receive Timing (Start of Frame) Bit n 0 1 TPRX+/- 0V -300mV Bit n+1 1 Bit n+2 0 Bit n+3 1 Bit n+4 1 0V t182 RENA Freescale Semiconductor, Inc... t183 t181 1.5V 1.5V RCLK RX Bit n Bit n+1 Bit n+2 Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair t186 +300mV +300mV 0V TPRX+/- t187 RENA 1.5V Figure 34. TP Receive Link Integrity Switching t202/t203 t200 300mV TPRX 300mV t201 50% TPLIL For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A TP COLLISION SWITCHING Characteristic Symbol Min Max Unit Time from collision (TPRX activity caused assertion of RENA followed by assertion of TENA) to assertion of CLSN Time from end of collision (Deassertion of TENA with uninterrupted TPRX pair activity) to deassertion of CLSN t210 - 300 ns t211 350 900 TPFULDL assert to collision detect disable (See Figure 36) TPFULDL deassert to collision detect enable t220 t221 - - 50 50 ns TPFULDL assert to data loop back disable (See Figure 37) TPFULDL deassert to data loop back enable t222 t223 - - 350 150 ns TP FULL DUPLEX SWITCHING NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. Freescale Semiconductor, Inc... Figure 35. TPTX Collision Timing RENA 1.5V 1.5V TENA t211 t210 1.5V 1.5V CLSN Figure 36. TPTX Full Duplex Timing TPFULDL 1.5V 1.5V t220 t221 CLSN 1.5V 1.5V Figure 37. TPTX Full Duplex Timing TPFULDL 1.5V RENA 1.5V t223 t222 1.5V 1.5V OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 23 Freescale Semiconductor, Inc. MC68160A AUI TRANSMIT SWITCHING Symbol Min Typ Max Unit TCLK to ATX Pair Steady State Propagation Delay t240 - - 100 ns Output Differential Rise and Fall Times (Measured directly at device pins) t241 1.0 - 5.0 ns ATX Bit Cell Duration center-to-center (Measured directly at device pins) t242 - 99.5-100.5 - ns ATX Half-Bit Cell Duration center-to-boundary (Measured directly at device pins) t243 - 49.5-50.5 - ns ATX Pair Held at Positive Differential at start of Idle (Measured through transformer) t244 200 - - ns Characteristic NOTE: Load on specified output is a shunt 27 H inductor and 83 resistor. Freescale Semiconductor, Inc... Figure 38. ATX Transmit Timings TCLK 1.5V TENA TX 1 0 1 0 0 1 1 t241 t240 t241 90% ATX+/- Differential (Logic Levels) 0V 1 0 1 0 0 1 10% 10% t242 t244 90% 0V 1 70% t243 AUI RECEIVE SWITCHING Characteristic Symbol Min Max Unit ARX/ACX Differential Input Voltage Range - 318 1315 mV ARX/ACX Differential Input Pulse Width to: Initiate Data Reception Inhibit Data Reception t261 t262 30 - - 18 RENA Assertion Delay RENA Deassertion Delay t266 t267 - - 100 450 ns ns Squelching Characteristics The receive data pairs and the collision pairs should have the following squelch characteristics: 1. The squelch circuits are on at idle (with input voltage at approximately 0 V differential). 2. If an input is in squelch, pulse is rejected if the peak differential voltage is more positive than -175 mV, regardless of pulse width. 3. A pulse is considered valid if its peak differential voltage is more negative than -300 mV and its width, measured at -285 mV, is > 25 ns. 4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair. 5. If a positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on. Figure 39. ARX/ACX Timing +175mV ARX+/- ACX+/- Differential Input Voltage -175mV t261/ t262 For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Figure 40. ARX/ACX Timing Bit Q ARX+/-/ ACX+/- Differential Input Voltage Bit U Bit V Bit W Bit X Bit Y t260 t260 t261 Bit Z +300mV -40mV 90% 1 -275mV -300mV 0 1 0 0 10% 90% 1 10% 0V 1 Freescale Semiconductor, Inc... t266 t267 1.5V 1.5V RENA/CLSN RCLK RX Bit Q Bit U Bit V Bit U Bit X Bit Y Bit Z FUNCTIONAL DESCRIPTION Introduction The MC68160A was designed to perform the physical connection to the Ethernet media. This is done through two separate media dependent interfaces and a SIA interface. The media dependent interfaces are the Attachment Unit Interface(AUI) and the 10BASE-T Twisted Pair(TP) port. The MC68160A's SIA interface is compatible with most industry controllers and selected by three mode control pins. Chip status is supported indicated by the condition of 6 status indicator pins. All but one are open collector outputs. If the EEST isn't receiving data, the controller may initiate transmission. NRZ data from the communications controller SIA interface is encoded by the MC68160A into Manchester Code in preparation for transmission on the media. The data is then applied to either the AUI or TP port. If the data was transmitted using the 10BASE-T port, this data is also looped back to the receive data interface SIA pins connected to the controller. This allows detection of a collision condition in the event that another station on the media attempted transmission at the same time. After the entire data frame has been transmitted, the EEST must force the media idle signal. The idle signal frees the media for other stations that have deferred transmission. If no other transmissions are required the link enters an idle state. During this idle state the 10BASE-T transmitter issues idle pulses which communicates to the receiver connected to the other side that the link is valid. If the transmitter connected at the other end begins transmission, the EEST will assert a receive enable signal, and forward the received data to the controller. Upon reception of data at the 10BASE-T port, the data is screened for proper sequence and pulse width requirements. If the preamble of the received frame meets the requirements, the PLL locks onto the 64-bit preamble and begins to decode the Manchester Code to NRZ code. This code is then presented to the communications controller at the receive data pins at the SIA interface. If data is received at the AUI port, it is sent directly to the communications controller via the SIA interface. Data Transmission To have properly encoded transmit data, the com- munications controller must be synchronized to TCLK. Transmission to the 10BASE-T or AUI media occurs when TENA is asserted and data is applied to the TX pin. Finally, to signify transmission, the TXLED in will cycle on and off at a 100 ms period. Data transmission for EEST is accomplished either over the 10BASE-T port or the AUI port. Both connections to the media are made with industry standard media interface components. The 10BASE-T interface requires a filter and transformer, the AUI interface requires only a transformer. The filter for the 10BASE-T transmit circuit will have to be chosen for each application. OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 25 Freescale Semiconductor, Inc. MC68160A Freescale Semiconductor, Inc... If after approximately 40 ms after a TP or AUI transmission has begun, the EEST is still transmitting, the TPJABB pin will assert to signify a jabber condition. Also, the CLLED pin will transition high and low alternately with a 100 ms period. The transmit circuitry is, however, unaffected by the jabber condition, so the communications controller has the responsibility of monitoring and stopping transmission. When transmission is complete, the transmit circuitry will begin the end of transmit and decay to idle responses necessary to meet requirements of the 802.3 standard for the TP and AUI port. Data Reception Other than the case of being in Loop Back mode, data reception to the RX pin of the EEST is initiated by signaling at the RX+/- or AUI ARX+/- pins. If at the TP port, the data is screened for validity by checking for sequence and pulse width requirements, then passed to the decode and receive circuitry. The RENA pin asserts and the data and corresponding clock is passed to the communications controller. After the frame has been transmitted, the MC68160A detects the ending transmission and negates RENA. If at the AUI port, the data is checked for proper pulse width requirements before being passed to the decode circuitry. If the data pulses are longer than at least 20 ns, RENA gets asserted and the frame is decoded to RX with and accompanying RCLK output. Collision Collision is the occurrence of simultaneous transmit activity by two or more stations on the network. In the event of collision, the data transfer paths are unaffected. If the MC68160A is in the twisted pair mode, collision is detect by simultaneous receive and transmit activity. If in the AUI mode, collision is detected by activity on the ACX+/- pins. In either case, if collision is detected, the CLSN pin will assert to notify the communications controller. Jabber The EEST has a jabber timer to detect the jabber condition. In the event that the transmitting station continues to transmit beyond the allowable transmit time, a jabber timer (40 ms) will expire and assert the TPJABB pin to alert the communications controller of the situation. The TPJABB pin can source or sink up to 10 mA, and so, is capable of driving a status LED. In the AUI mode, the pin is driven to high impedance since the transceiver connected to the AUI port must alert the communications controller of the jabber condition. Full Duplex A feature unique to the MC68160A is the Full Duplex mode. In this mode the EEST is capable of transmitting and receiving simultaneously. Collision conditions are not announced and internal loop back is disabled. The remainder of the EEST functionality remains unchanged from the non-Full Duplex mode. Full Duplex mode is enabled by asserting the TPFULDL pin. Auto Port Selection If the APORT pin is asserted, the MC68160A will automatically select the TP or AUI port depending on the presence of valid link beats or frames at the TP RX+/- pins. If the AUI port is automatically selected by another transmitting station or by setting TPEN low, the TP transmit port of the EEST continues to transmit link beats to keep the link active. Auto Polarity Selection If the RX+ and the RX- wires happen to get reversed, the MC68160A has the ability to automatically reverse the pins internally so that the received data is valid. In addition, an open collector status pin (TPPLR) is driven low to indicate the fault. In the AUI or reset mode this pin presents a high impedance. Loop Back Mode To test the transmit and receive circuitry without disturbing the connected network, the EEST has a Loop Back mode. Loop Back mode routes transmit data and clock to the receive data and clock pins using as much of the transmit and receive circuitry as possible. This gives a test of the MC68160A Manchester encode and decode function. LOOP must not be asserted when TPFULDL pin is asserted. This causes the MC68160A to enter a test mode. This test mode is used during final test and is not intended to be entered under normal operation (see Application Notes section). For More Information On This Pro Go to: www.freescale.com OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A APPLICATIONS INFORMATION Selection of Crystal and External Components Accuracy of frequency and stability over temperature are the main determinants of crystal choice. Specifications for a suitable crystal are tabulated below. AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA AAAAAAAAAAAAA AAAAA Part # FEE Fil-Mag 78Z1120B-01, 78Z1122B/D-01, 78Z1122 F-01 Valor a o Electronics ec o cs PT3877, 38 , FL1012, 0 , FL1066 066 Frequency 20.000 MHz Pulse Engineering PE-65434, PE65424, PE65433 Mode Fundamental TOKO PM01-00, PM02-00, PM05-00 Tolerance 100 ppm Stability 100 ppm Aging 5 ppm/yr Shunt Capacitance 7.0 pF Load Capacitance 18-20 pF 25 Series Fundamental Resistance (ESR) Freescale Semiconductor, Inc... Vendor 500 W Drive Level X1 A suitable crystal is the MTRON HC49 MP-1, 20.000 MHz crystal. 20 pF for C4 and C5 have been shown to work reliably. X2 1 2 C5 C4 PLL Filter Components The filter components at Pin 12 were chosen to assure adequate pull-range but with a emphasis on stability. It is not foreseeable that a design would need to change the components, but for the sake of completeness, relevant values are provided here. + 24 MHz and, Volt * sec 100 mA and the Phase Detector Gain p 2 rad VCO Gain + filter impedance function is; (jw ) 1C6) Z(jw) [ jw * C5 * (jw ) 1C5) (for C6 uu C5) 10BASE-T Filter and Transformer Choice The MC68160A differential outputs are low impedance voltage sources. Therefore, external series resistors must be used in order to match the characteristic impedance of twisted pair. Since the output resistance of each leg of the transmitter is about 10 , a 39 resistor is used in series as shown in the applications schematic. So the impedance presented from the source to the isolation transformer is then very nearly 100 . The following is a list of some 10BASE-T filter module vendors and their products. AUI Transformer Choice Like the 10BASE-T outputs, the AUI differential outputs are low impedance sources and capable of meeting the IEEE 802.3 waveform requirements when a coupling transformer is used. Some AUI transformer vendors and their products are provided below. Vendor Part # Coilcraft LAX-ET304 FEE Fil-Mag 23Z90, 23Z91/ 23Z92 Valor Electronics LT6032, LT6033 Pulse Engineering PE64502, PE6103 TOKO Q30ALQ8-1AA3, Q30ALQ9-1AA3 Application Notes: Resetting the MC68160A after power up. In some applications, after initial power up, the MC68160A may not be able to transmit or receive data. This is usually caused by the LOOP and TPFULDL control lines being active at the same time. This is an illegal condition during normal operation, it places the MC68160A into the production test mode. To exit the test mode and return to normal: Set LOOP low, TPFULDL high and TPSQEL low. Then, while keeping TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This will put the MC68160A into test mode but also resets the MC68160A. After 500 ms lower LOOP to get out of the test mode. TPFULDL may then be de-asserted if desired. The MC68160A is now ready for operation. A hardware implementation of this fix would be to place a pull down resistor on the TPSQEL pin. Even if test mode is entered by accident, this ensures that zero's will be written to the test register. The hardware implementation will solve the problem if the test mode is entered because of noise on the TPSQEL pin. If the controller is toggling the MC68160A lines while it is booting up, the reset procedure must be followed. OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 27 For More Information On This Pro Go to: www.freescale.com 0.1 F 0.1 F GNDDIG VDDDIG LOOP CS2 CS1 CS0 RX RENA C6 C5 R 12 3900pF 15 14 C3 20pF VCC 16 17 X1 20MHz 1 1 0 0 1 1 CS1 1 0 0 0 0 CS2 C4 20pF Standby Low Current Mode 2. Decoupling capacitors should be placed as close to supply pins as possible. VDD 18 19 Motorola MC68360, AMD 7990 & 79C900 Intel 82586, 82590, 82593, 82596 Fujitsu MB86950, MB86960 National 8390, 83C690, 83932B 802.3 Communication Controller 43 44 45 MC68160AFB 46 47 48 51 50 49 52 CLSN Communications Controller Selection 1 0 1 0 CS0 TPAPCE TPSQEL TPFULDL 0.039 F 300 8 7 6 5 4 3 2 1 9 APORT VCC 10 VDDDIV 11 VDDFM 12 MFILT 13 GNDFM VDD AutoPort En APOR 1. For Suitable Crystal (X1) see applications text on previous page. 10 F VDD 10 F VCC Power Supply Bypassing +5.0V AMD (7990/79C900) Intel (825** -86/90/93/96) Fujitsu (869** -50/60) National (8390/83C90/83932B) Receive Enable Receive Data LoopBack X2 RENA RX LOOP VDDDIG MC68360 GNDDIG Collision Int Receive Clock TX 20 GNDSUB CLSN RCLK TENA RCLK X1 LED6 R 33 330 21 ACX- 22 23 41 40 42 R8 330 LED5 24 C2 0.1 F C1 27 28 29 30 31 32 33 34 35 36 37 38 39 R7 39 R6 39 R5 39 R4 39 VDD VCC R 13 330 R 11 330 VDD LED2 LED3 VDD R 15 10 K TPSQEL TPFULDL TPAPCE VDDANA TPRX- TPRX+ GNDANA GNDPWR VDDPWR TPTX- TPTX+ VDDPWR 0.1 F 25 26 R9 330 LED4 GNDPWR TXLED COMMUNICATIONS CONTROLLER TCLK VDDVCO TPJABB ARX- TP Enable Transmit Clock Transmit Enable Transmit Data ARX+ CLLED ATX- RXLED ATX+ TPEN TCLK TENA TX TPEN GNDCTL GNDVCO TPLIL TPPLR ACX+ R3 100 R2 39 39 R1 R 14 330 LED1 1 7 8 6 4 5 3 2 1 8 7 5 4 3 6 11 14 9 10 12 13 15 16 IIIIII IIIIII IIIIII 2 Coilcraft (LAX-ET30*) Pulse Engineering (PE-64***) Valor (LT600*/LT603*) TOKO (Q30ALQ*-1AA3) CTP3 0.01F CTP2 0.01F 11 10 9 13 12 14 16 15 AUI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +12V RJ45 3 RD + 6 RD - 1 TD + 2 TD - Valor (PT3877, PT3882, FL1012, FL1066) TOKO (PM01, PM02, PM05) Pulse Engineering (PE-65433, PE-65434, PE-65424) Figure 41. AUI XFMR Figure 41. Typical Application Diagram IIIIII IIIIII IIIIII (Example of PE-65424) Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68160A OROLA ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848D-03 (LQFP-52) ISSUE C 4X 4X TIPS 0.20 (0.008) H L-M N 52 CL 40 1 AB 39 3X VIEW -M- VIEW Y B V B1 V1 J 13 27 26 CCC EEEE EEEE CCC U 0.13 (0.005) -N- A1 BASE METAL F PLATING 14 G AB Y -L- Freescale Semiconductor, Inc... -X- X=L, M, N 0.20 (0.008) T L-M N M D T L-M S N S SECTION AB-AB S1 ROTATED 90_ CLOCKWISE A S 4X C 2 0.10 (0.004) T -H- -T- SEATING PLANE 4X 3 VIEW AA 0.05 (0.002) NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). S W 1 2XR R1 0.25 (0.010) C2 GAGE PLANE K C1 E Z VIEW AA OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ 29 Freescale Semiconductor, Inc. MC68160A Freescale Semiconductor, Inc... NOTES For More Information On This Pro Go to: www.freescale.com ANALOG IC DEVICE DATA Freescale Semiconductor, Inc. MC68160A Freescale Semiconductor, Inc... NOTES OROLA ANALOG IC DEVICEFor DATA More Information On This Pro Go to: www.freescale.com 31 Freescale Semiconductor, Inc. MC68160A How to Reach Us: RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. Home Page: www.freescale.com For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. For More Information On This Pro Go to: www.freescale.com MC68160A/D OROLA ANALOG IC DEVICE DATA