K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
1
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No
0.0
0.1
0.11
1.0
2.0
2.01
Remark
Advance
Preliminary
Final
Final
Final
History
Initial draft
Revise
- Speed bin change
Commercial: 70/85ns to 70/85/100ns
Industrial: 85/100ns to 70/85/100ns
- DC Characteristics change
ICC: 5mA at read/write to 4mA at read
ICC1: 5mA to 6mA
ICC2: 50mA to 45mA
ISB: 0.5mA to 0.3mA
ISB1: 10µA to 15µA for commercial parts
Errata correction
Finalize
Revise
- Add K6T4016V3C-TB55 product
Revise
- Improved VOH(output high voltage) from 2.2V to 2.4V.
Draft Date
January 13, 1998
June 12, 1998
August 13, 1998
November 16, 1998
June 26, 2001
October 15, 2001
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
2
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T4016V3C and K6T4016U3C families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fami-
lies support various operating temperature ranges and have
various package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
FEATURES
• Process Technology: TFT
• Organization: 256K x16
• Power Supply Voltage
K6T4016V3C Family: 3.0~3.6V
K6T4016U3C Family: 2.7~3.3V
• Low Data Retention Voltage: 2V(Min)
• Three State Outputs
• Package Type: 44-TSOP2-400F/R
PIN DESCRIPTION
Name Function Name Function
CS Chip Select Input Vcc Power
OE Output Enable Input Vss Ground
WE Write Enable Input LB Lower Byte (I/O1~8)
A0~A17 Address Inputs UB Upper Byte (I/O9~16)
I/O1~I/O16 Data Input/Output NC No Connection
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family Operating Temperature Vcc Range Speed(ns) Power Dissipation PKG Type
Standby
(ISB1, Max) Operating
(ICC2, Max)
K6T4016V3C-B Commercial(0~70°C) 3.0~3.6V 551)/701)/85/100 15µA
45mA 44-TSOP2-400F/R
K6T4016U3C-B 2.7~3.3V 701)/85/100
K6T4016V3C-F Industrial(-40~85°C) 3.0~3.6V 20µA
K6T4016U3C-F 2.7~3.3V
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
44-TSOP2
Forward 44-TSOP2
Reverse
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A13 A12
A11 A12
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
A5 A6 A7 A8 A9 A11A10
A0
A1
A2
A3
A4
A13
A14
A15
WE
OE
UB
CS
I/O1~I/O8
A16
Data
cont
Data
cont
Data
cont
LB
I/O9~I/O16
Vcc
Vss
A17
A12
Precharge circuit.
Memory array
1024 rows
256×16 columns
I/O Circuit
Column select
Control
logic
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
3
PRODUCT LIST
Commercial Temperature Product(0~70°C) Industrial Temperature Products(-40~85°C)
Part Name Function Part Name Function
K6T4016V3C-TB55
K6T4016V3C-TB70
K6T4016V3C-TB85
K6T4016V3C-TB10
K6T4016V3C-RB70
K6T4016V3C-RB85
K6T4016V3C-RB10
K6T4016U3C-TB70
K6T4016U3C-TB85
K6T4016U3C-TB10
K6T4016U3C-RB70
K6T4016U3C-RB85
K6T4016U3C-RB10
44-TSOP2-F, 55ns, 3.3V, LL
44-TSOP2-F, 70ns, 3.3V, LL
44-TSOP2-F, 85ns, 3.3V, LL
44-TSOP2-F, 100ns, 3.3V, LL
44-TSOP2-R, 70ns, 3.3V, LL
44-TSOP2-R, 85ns, 3.3V, LL
44-TSOP2-R, 100ns, 3.3V, LL
44-TSOP2-F, 70ns, 3.0V, LL
44-TSOP2-F, 85ns, 3.0V, LL
44-TSOP2-F, 100ns, 3.0V, LL
44-TSOP2-R, 70ns, 3.0V, LL
44-TSOP2-R, 85ns, 3.0V, LL
44-TSOP2-R, 100ns, 3.0V, LL
K6T4016V3C-TF70
K6T4016V3C-TF85
K6T4016V3C-TF10
K6T4016V3C-RF70
K6T4016V3C-RF85
K6T4016V3C-RF10
K6T4016U3C-TF70
K6T4016U3C-TF85
K6T4016U3C-TF10
K6T4016U3C-RF70
K6T4016U3C-RF85
K6T4016U3C-RF10
44-TSOP2-F, 70ns, 3.3V, LL
44-TSOP2-F, 85ns, 3.3V, LL
44-TSOP2-F, 100ns, 3.3V, LL
44-TSOP2-R, 70ns, 3.3V, LL
44-TSOP2-R, 85ns, 3.3V, LL
44-TSOP2-R, 100ns, 3.3V, LL
44-TSOP2-F, 70ns, 3.0V, LL
44-TSOP2-F, 85ns, 3.0V, LL
44-TSOP2-F, 100ns, 3.0V, LL
44-TSOP2-R, 70ns, 3.0V, LL
44-TSOP2-R, 85ns, 3.0V, LL
44-TSOP2-R, 100ns, 3.0V, LL
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V-
Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V-
Power Dissipation PD1.0 W-
Storage temperature TSTG -65 to 150 °C-
Operating Temperature TA0 to 70 °CK6T4016V3C-B, K6T4016U3C-B
-40 to 85 °CK6T4016V3C-F, K6T4016U3C-F
FUNCTIONAL DESCRIPTION
1. X means don′t care. (Must be in low or high state)
CS OE WE LB UB I/O1~8 I/O9~16 Mode Power
HX1) X1) X1) X1) High-Z High-Z Deselected Standby
LH H X1) X1) High-Z High-Z Output Disabled Active
LX1) X1) H H High-Z High-Z Output Disabled Active
L L HLHDout High-Z Lower Byte Read Active
L L H H LHigh-Z Dout Upper Byte Read Active
L L HL L Dout Dout Word Read Active
LX1) L L HDin High-Z Lower Byte Write Active
LX1) LHLHigh-Z Din Upper Byte Write Active
LX1) L L L Din Din Word Write Active
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
4
RECOMMENDED DC OPERATING CONDITIONS1)
Note:
1. Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
2. Overshoot: VCC+2.0V in case of pulse width ≤ 30ns
3. Undershoot: -2.0V in case of pulse width ≤ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Product Min Typ Max Unit
Supply voltage Vcc K6T4016V3C Family
K6T4016U3C Family 3.0
2.7 3.3
3.0 3.6
3.3 V
Ground Vss All Family 0 0 0 V
Input high voltage VIH K6T4016V3C, K6T4016U3C Family 2.2 -Vcc+0.32) V
Input low voltage VIL K6T4016V3C, K6T4016U3C Family -0.33) -0.6 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled, not 100% tested
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -8pF
Input/Output capacitance CIO VIO=0V -10 pF
DC AND OPERATING CHARACTERISTICS
1. Industrial product = 20µA
2. Cycle time = 70ns
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIL=Vss to Vcc -1 -1µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 4mA
Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,
VIN≤0.2V or VIN≥Vcc-0.2V - - 6mA
ICC2 Cycle time=Min2), 100% duty, IIO=0mA, CS=VIL,
VIN=VIH or VIL - - 45 mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA
Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 151) µA
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
5
CL1)
1.Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1. Industrial product = 20µA
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS≥Vcc-0.2V 2.0 -3.6 V
Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V -0.5 151) µA
Data retention set-up time tSDR See data retention waveform 0- - ms
Recovery time tRDR 5- -
AC CHARACTERISTICS (K6T4016V3C Family: Vcc=3.0~3.6V, K6T4016U3C Family: Vcc=2.7~3.3V
Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Parameter List Symbol Speed Bins Units
55ns 70ns 85ns 100ns
Min Max Min Max Min Max Min Max
Read
Read cycle time tRC 55 -70 -85 -100 -ns
Address access time tAA -55 -70 -85 -100 ns
Chip select to output tCO -55 -70 -85 -100 ns
Output enable to valid output tOE -25 -35 -40 -50 ns
LB, UB valid to data output tBA -25 -35 -40 -50 ns
Chip select to low-Z output tLZ 10 -10 -10 -10 -ns
Output enable to low-Z output tOLZ 5-5-5-5-ns
LB, UB enable to low-Z output tBLZ 5-5-5-5-ns
Output hold from address change tOH 10 -10 -10 -15 -ns
Chip disable to high-Z output tHZ 020 025 025 030 ns
OE disable to high-Z output tOHZ 020 025 025 030 ns
LB, UB disable to high-Z output tBHZ 020 025 025 030 ns
Write
Write cycle time tWC 55 -70 -85 -100 -ns
Chip select to end of write tCW 45 -60 -70 -80 -ns
Address set-up time tAS 0-0-0-0-ns
Address valid to end of write tAW 45 -60 -70 -80 -ns
Write pulse width tWP 40 -55 -60 -70 -ns
Write recovery time tWR 0-0-0-0-ns
Write to output high-Z tWHZ 020 025 025 030 ns
Data to write time overlap tDW 25 -30 -35 -40 -ns
Data hold from write time tDH 0-0-0-0-ns
End write to output low-Z tOW 5-5-5-5-ns
LB, UB valid to end of write tBW 45 -60 -70 -80 -ns
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
6
Address
Data Out Previous Data Valid Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
tRC
CS
Address
UB, LB
OE
Data out
tAA
tRC
tOH
tOH
tAA
tCO
tBA
tOE
tOLZ
tBLZ
tLZ tOHZ
tBHZ
tHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
7
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
Data Valid
UB, LB
WE
Data in
Data out High-Z High-Z
tWC
tCW(2)
tAW tBW
tWP(1)
tDH
tDW
tWR(4)
tAS(3)
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
Data Undefined
UB, LB
WE
Data in
Data out
tWC
tCW(2) tWR(4)
tAWtBW
tWP(1)
tAS(3) tDHtDW
tWHZ tOW
High-Z High-Z
Data Valid
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
8
Address
CS
Data Valid
UB, LB
WE
Data in
Data out High-Z High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
DATA RETENTION WAVE FORM
CS controlled
VCC
3.0/2.7V1)
2.2V
VDR
CS
GND
Data Retention Mode
CS≥VCC - 0.2V
tSDR tRDR
tAS(3)
1. 3.0V for K6T4016V3C Family, 2.7V for K6T4016U3C Family
K6T4016V3C, K6T4016U3C Family CMOS SRAM
Revision 2.01
October 2001
9
Unit: millimeter(inch)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.002
#1
0.05
#22
#44 #23
0.35±0.10
0.014±0.004 0.80
0.0315
MIN.
0.047
1.20 MAX.
0.741
18.81MAX.
18.41± 0.10
0.725±0.004
11.76±0.20
0.463±0.008
+ 0.10
- 0.05
0.50
+ 0.004
- 0.002
0.15
0.006
0.020
10.16
0.400
0.10
0.004
0~8°
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00±0.10
0.039±0.004
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0.002
#1
0.05
#22
#44 #23
0.35± 0.10
0.014±0.004 0.80
0.0315
MIN.
0.047
1.20MAX.
0.741
18.81MAX.
18.41±0.10
0.725±0.004
11.76±0.20
0.463±0.008
+ 0.10
- 0.05
0.50
+ 0.004
- 0.002
0.15
0.006
0.020
10.16
0.400
0.10
0.004
0~8°
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00±0.10
0.039±0.004
