19-1083; Rev 1; 8/96 MA AALAM +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1tA Power-Down General Description The MAX114/MAX118 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital con- verters (ADCs). They operate from a single +5V supply and use a half-flash technique to achieve a 660ns con- version time (1Msps). A power-down (PWRDN) pin reduces current consumption typically to 1pA. The devices return from power-down mode to normal oper- ating mode in less than 200ns, allowing large supply- current reductions in burst-mode applications (in burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals). Both converters include a track/hold, enabling the ADC to digitize fast analog signals. Microprocessor (uP) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel pP data bus or system input port. The MAX114/MAX118 input/reference configuration enables ratiometric operation. The 4-channel MAX114 is available in a 24-pin DIP or SSOP. The 8-channel MAX118 is available in a 28-pin DIP or SSOP. For +3V applications, refer to the MAX113/MAX117 data sheet. Applications Remote Data Acquisition High-Speed DSP Portable Equipment Communications Systems Features Single +5V Supply Operation @ 4(MAX114) or 8 (MAX118) Analog Input Channels Low Power: 40mW (operating mode) 5pW (power-down mode) Total Unadjusted Error <1LSB Fast Conversion Time: 660ns per Channel @ No External Clock Required Internal Track/Hold 1MHz Full-Power Bandwidth Internally Connected 8th Channel Monitors Reference Voltage (MAX118) Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX114CNG 0S to +70C 24 Narrow Plastic DIP MAX114CAG 0S to +70C 24 SSOP MAX114C/D OCto+70C _Dice* MAX114ENG -40C to +85C 24 Narrow Plastic DIP MAX114EAG -40C to +85C 24 SSOP MAX114MRG -55C to+125C 24 Narrow CERDIP** Ordering Information continued on last page. *Dice are specified at Ta = +25C, DC parameters only. Contact factory for availability. Pin Configurations appear on last page. Functional Diagram *IN7 INS IN4 IN3 IN2 AO Al #2 REF- * MAX118 ONLY REF+ D7 DS D4 4-BIT D3 FLASH D2 ADC D1 (4LSBs) DO TIMING AND CONTROL MAAXIAM MAX114/MAX118 PWRDN | RD cs MODE iNT WRYRDY MAXIM Maxim Integrated Products 1 For free samples & the latest literature: http:/;www.maxim-ic.com, or phone 1-800-998-8800 BLLXVWVILLXVWMAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1LpA Power-Down ABSOLUTE MAXIMUM RATINGS VDD tO GND 0... ceeceeeeeseeesneaeeesneeeeesseeeeeseeeessneaeeeees -0.3V to +7V Digital Input Voltage to GND Digital Output Voltage to GND REF+ to GND REF- to GND... 24-Pin Narrow Plastic DIP (derate 13.33mMW/C above +70C) 24-Pin SSOP (derate 8.00mW/C above +70C) 24-Pin Narrow CERDIP (derate 12.50mW/C above +70C) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to Continuous Power Dissipation (Ta = +70C) | ( ( 0. '3V to (Vpp + 0.3V) ( ( Vop + 0.3V) Vpp + 0.3V) 28-Pin Wide CERDIP Vpp + 0.3V) (derate 16.67mMW/C above +70C) Vpp + 0.3V) Operating Temperature Ranges MAX1 14/MAX118C___ MAX114/MAX118E__ MAX1 1 4/MAX118M__ absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VoD = +5V +5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), Ta = TMIN to TMAX, unless otherwise noted.) 28-Pin Wide Plastic DIP (derate 14.29mW/C above +70C) 28-Pin SSOP (derate 9.52mW/C above +70C) Storage Temperature Range... Lead Temperature (soldering, 10sec) 0C to +70C 40C to +85C 55C to +125C -65C to +150C PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS ACCURACY (Note 1) Resolution N 8 Bits Total Unadjusted Error TUE +1 LSB Differential Nonlinearity DNL No-missing-codes guaranteed +1 LSB Zero-Code Error +1 LSB Full-Scale Error +1 LSB Channel-to-Channel Mismatch +1/4 LSB DYNAMIC PERFORMANCE Signal-to-Noise Plus SINAD MAX11_C/E, fsAMPLE = 1MHz, fin. = 195.8kHz 45 dB Distortion Ratio MAX11_M, fSAMPLE = 740kHz, fin. = 195.7kHz 45 Total Harmonic Distortion THD MAX 1_C/E, fsaMPLE = 1MH2, fin_ = 195.8kHz 80 dB MAX11_M, fSAMPLE = 740KHz, fin = 195.7KHz -50 Spurious-Free Dynamic SFDR MAX11_C/E, fsAMPLE = 1MHz, fin_ = 195.8kHz 50 dB Range MAX11_M, fSAMPLE = 740kHz, fin. = 195.7kHz 50 Input Full-Power Bandwidth VIN_ = 5Vp-p 1 MHz Input Slew Rate, Tracking 3.1 15 Vius ANALOG INPUT Input Voltage Range VIN VREF- VREF+ Vv Input Leakage Current LIN GND < VIN. < VbD +3 HA Input Capacitance CIN_ 32 pF REFERENCE INPUT Reference Resistance RREF 1 2 4 kQ REF+ Input Voltage Range VREF- Vppb Vv REF- Input Voltage Range GND VREF+ Vv 2 MAXIMA+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1tA Power-Down ELECTRICAL CHARACTERISTICS (continued) (Vpp = +5V +5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), Ta = TMIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS LOGIC INPUTS Input High Voltage Vina CS, WR, RD, PWRDN, AO, A1, A2 2.4 Vv MODE 3.5 CS, WR, RD, PWRDN, AO, A1, A2 0.8 Input Low Voltage VINL Vv MODE 1.5 CS, RD, PWRDN, AO, A1, A2 +1 Input High Current lINH WR +3 yA MODE 50 200 Input Low Current INL CS, WR, RD, PWRDN, MODE, AO, A1, A2 +1 yA Input Capacitance (Note 2) CIN CS, WR, RD, PWRDN, MODE, AO, A1, A2 5 8 pF LOGIC OUTPUTS ISINK = 1.6mA, INT, DO-D7 0.4 Output Low Voltage VoL Vv RDY, IsINK = 2.6mA 0.4 Output High Voltage Vou ISOURCE = 360uA, INT, DO-D7 4 Vv Three-State Current ILKG DO-D7, RDY, digital outputs = OV to Vpp +3 HA Note) Capacitance Cout D0-D7, RDY 5 8 pF POWER REQUIREMENTS Supply Voltage Vpb 4.75 5.25 Vv CS=RD=OoOvV, MAX11_C 8 15 Vppb Supply Current IDD PWRDN = Vpp MAXi1_E/M a 30 mA Power-Down Vpp Current CS = RD = Vpp, PWRDN = OV (Note 3) 1 10 yA Power-Supply Rejection PSR Vop = 4.75V to 5.25V, VReF = 4.75V +1/16 +1/4 LSB Note 2: Guaranteed by design. Note 3: Power-down current increases if logic inputs are not driven to GND or Vpp. MAXLAA BLLXVWVILLXVWMAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1LpA Power-Down TIMING CHARACTERISTICS (Vpp = +4.75V, Ta = +25C, unless otherwise noted.) (Note 4) Ta = +25C Ta = TmIN to TMAX PARAMETER SYMBOL CONDITIONS ALL GRADES MAX11_C/E MAX11_M UNITS MIN TYP MAX | MIN MAX MIN MAX Conversion Time t tRD<tinTL, | CL= 20pF 660 ng (WR-RD Mode) CWR | (Note 5) CL = 100pF 685 865 1125 Conversion Time (RD Mode) tcRD 700 875 975 ns Power-Up Time tUP 320 370 520 ns CS to RD, WR Setup Time tess 0 0 0 ns CS to RD, WR Hold Time tosH ns as CL = 50pF, CS to RDY Delay tRDY RL = 5.1kQ to Vop 70 85 100 ns Data-Access Time _ tcRD + tCRD + tCRD + (RD Mode) tACco CL = 100pF (Note 5) 50 65 75 ns RD to INT Delay _ (RD Mode) TINTH CL = 50pF 50 80 85 90 ns Data Hold Time 1DH (Note 6) 60 70 80 ns Minimum Acquisition Time taca (Note 7) 160 185 260 ns WR Pulse Width twR 0.25 10 0.28 =610 0.4 10 Us Delay Between WR and BD Pulses tRD 0.25 0.35 0.45 Us RD Pulse Width tRD < tINTL, (WR-RD Mode) tREAD1 determined by tacct 160 205 240 ns Data-Access Time TRD < tINTL, CL = 100pF (WR-RD Mode) acct | (Note 5) 185 238 278 ns RD to INT Delay trl 150 185 220 ns WR to INT Delay tINTL CL = 50pF 380 500 610 700 ns RD Pulse Width tRD > tINTL, determined by (WR-RD Mode) TREAD2 | taco 6s s 85 ns Data-Access Time TRD > tINTL, CL = 100pF (WR-RD Mode) tacc2 | (Note 5) 80 110 130 ns WR to INT Delay tiHwR | Pipelined mode, CL = 50pF 80 100 120 ns Data-Access Time a. after INT TD Pipelined mode, CL = 100pF 45 60 70 ns Multiplexer Address Hold Time TAH 30 35 40 ns Note 4: Input control signals are specified with tr = tf = 5ns, 10% to 90% of 5V, and timed from a voltage level of 1.6V. Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.8V or 2.4V. Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time. MAXIM+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1tA Power-Down Typical Operating Characteristics (VoD = +5V, Ta = +25C, unless otherwise noted.) CONVERSION TIME EFFECTIVE NUMBER OF BITS vs. Ss vs. AMBIENT TEMPERATURE INPUT FREQUENCY (WR-RD MODE) & 15 3 8.0 3 iA i Mh : a 13 e MN * 2 . is 75 & 12 fe 3 14 Vpp = +4.75V 2 = 5 7.0 5 10 2 2 y G 09 5 N Vpp = +5.25V Bs Zz 08 i = fsampLe = 1MHz S 07 Vpp = +8V Vin = 4.96Vp-p 2 a eo L-LLLW JU 2 60 -20 20 60 100 140 tk 10k 100k 1M TEMPERATURE (C) INPUT FREQUENCY (Hz) AVERAGE POWER CONSUMPTION vs. SAMPLING RATE USING PWRDN SIGNAL-TO-NOISE RATIO 50 8 0 3 _ i Vpp = 4.75 | i = 40 4 -20 t i; - INPUT FREQUENCY =- 195.8ksps z _ Vin = 4.72Vp-p ec | | oc. : A = 30 3s 740 SAMPLE B = FREQUENCY = {MHz S20 LI a SNR = 48.2dB re y 60 1 1 3 Y 10 A | -80 0 oo -100 tk 10k 100k iM 0 100 200 300 400 500 SAMPLING RATE (CONVERSIONS/SEC) FREQUENCY (kHz) TOTAL UNADJUSTED ERROR SUPPLY CURRENT vs. TEMPERATURE vs. POWER-UP TIME (EXCLUDING REFERENCE CURRENT) 6 3 12 i 5 5 10 i = E _ 4 _ 8 3 6 rT 3 Ss 6 2D Oo - > 2 a 4 2D wo 1 2 0 0 75 100 125 150 175 200 225 250 60-20 20 60 100 140 POWER-UP TIME, tup (ns) TEMPERATURE (C) MAXIMA 5 BLLXVWVILLXVWMAX114/MAX118 +5V, 1Msps, 4 & 8-Bit ADCs with 8-Channel, 1A Power-Down Pin Description MAXi14 PIN MAX118 NAME FUNCTION _ 1 IN6 Analog Input Channel 6 _ 2 IN5 Analog Input Channel 5 1 3 IN4 Analog Input Channel 4 2 4 IN3 Analog Input Channel 3 3 5 IN2 Analog Input Channel 2 4 6 IN4 Analog Input Channel 1 5 7 MODE Mode Selection Input. Internally pulled low with a SOpA Current source. MODE = 0 acti- vates read mode; MODE = 1 activates write-read mode (see Digital Interface Section). 6 8 DO Three-State Data Output (LSB) 7,8,9 9, 10, 11 D1, D2, D3 Three-State Data Outputs 10 12 RD Read Input. RD must be low to access data (see Digital Interface section). 1 13 INT Interrupt Output. INT goes low to indicate end of conversion (see Digital interface section). 12 14 GND Ground 13 15 REF- Lower Limit of Reference Span. REF- sets the zero-code voltage. Range is GND < VREF- < VREF+.- 14 16 REF+ Upper Limit of Reference Span. REF+ sets the full-scale input voltage. Range is VREF- < VREF+ < Vpp. Internally hard-wired to IN8 (Table 1). 15 17 WR/RDY Write-Control Input/Ready-Status Output (see Digital Interface section) 16 18 cs Chip-Select Input. CS must be low for the device to recognize WR or RD inputs. 17, 18,19 19, 20, 21 D4, D5, D6 Three-State Data Outputs 20 22 D7 Three-State Data Output (MSB) _ 23 A2 Multiplexer Channel Address Input (MSB) 21 24 Al Multiplexer Channel Address Input 22 25 AO Multiplexer Channel Address Input (LSB) 23 26 PWRDN Power-Down Input. PWRDN reduces supply current when low. 24 27 VpD Positive Supply, +5V _ 28 IN7 Analog Input Channel 7 MAXIM+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1tA Power-Down Detailed Description Converter Operation The MAX114/MAX118 use a half-flash conversion tech- nique (see Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 com- parators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash con- version and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash com- parators to obtain the lower four data bits (LSBs). An internal analog multiplexer enables the devices to read four (MAX114) or eight (MAX118) different analog voltages under microprocessor (uP) control. One of the MAX118s analog channels, IN8, is internally hard- wired and always reads VREF+ when selected. Power-Down Mode In burst-mode or low sample-rate applications, the MAX114/MAX118 can be shut down between conver- sions, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1pA when powered from a single +5V supply. A logic high on PWRDN wakes up the MAX114/MAX118, and the selected analog input enters the track mode. The signal is fully acquired after 360ns (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can be started. If the power-down feature is not required, connect PWRDN to Vpp. For minimum current consumption, keep digital inputs at the supply rails in power-down mode. Refer to the Reference section for information on reduc- ing reference current during power-down. Digital Interface The MAX114/MAX118 have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The AO, Vbp A1, and A2 inputs control channel selection, as shown in Table 1. The address must be valid for a minimum RL=3k i : DATA DATA time, taca, before the next conversion starts. OUTPUTS OUTPUTS 4 T T Table 1. Truth Table for Input Channel AL =3k g T o, T O Selection MAX114 MAX118 = = SELECTED CHANNEL Al AO A2 Atl AO a) HIGH-ZTO VoH b) HIGH-ZTO VoL 4 0 0 4 0 IN3 Figure 1. Load Circuits for Data-Access Time Test 4 4 0 4 4 IN4 _ _ 4 0 0 INS _ _ 4 0 4 IN6 Vpp 1 1 0 IN7 - |/4 4 4 IN8 3k (reads VREF+ if selected) DATA DATA OUTPUTS OUTPUTS L i Read Mode (MODE = 0) 4k 10pF 10pF In read mode, conversions and data access are con- L L trolled by the RD input (Figure 3). The comparator a) VOH TOHIGH-Z b) VoL TOHIGH-Z Figure 2. Load Circuits for Data-Hold Time Test MAXLAA inputs track the analog input voltage for the duration of taca. Initiate a conversion by driving CS and RD low. With pPs that can be forced into a wait state, hold RD low until output data appears. The uP starts the conver- sion, waits, and then reads data with a single read instruction. BLLXVWVILLXVWMAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1LpA Power-Down In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a pP. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the ris- ing edge of CS or RD. Write-Read Mode (MODE = 1) Figures 4 and 5 show the operating sequence for write- read mode. The comparator inputs track the analog input voltage for the duration of taca. The conversion is initiated by a falling edge of WR. When WR returns high, the result of the four-MSBs flash is latched into the output buffers and the conversion of the four-LSBs flash starts. INT goes low, indicating conversion end, and the lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics). A minimum acquisition time (taca) is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sections). Using Internal Delay The p/P waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs DO-D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD. Fastest Conversion: Reading Before Delay Figure 5 shows an external method of controlling the conversion time. The internally generated delay (tiNTL) varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers that contain the conversion result (DO-D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: twR + tRD + tacc1 = 660ns. taca ADDRESS VALID (N + 1) tess tes Figure 4. Write-Read Mode Timing (tap > tinTL) (MODE = 1) PWRDN cs al taca AO-A2 ADDRESS VALID ADDRESS VALID (N+ 1) taH t AH RADY WITH EXTERNAL PULL-UP INT tcro DO-D7 tacco AQ-A2 ADDRESS VALID (N + 1) tcsH {DH Figure 3. Read Mode Timing (MODE = 0) Figure 5. Write-Read Mode Timing (trp < tintL) (MODE = 1) MAXIM+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1tA Power-Down Pipelined Operation Besides the two standard write-read-mode options, pipelined operation can be achieved by connecting WR to RD (Figure 6). With CS low, driving WR and RD. low initiates a conversion and concurrently reads the result of the previous conversion. Analog Considerations Reference Figures 7a, 7b, and 7c show typical reference connec- tions. The voltages at REF+ and REF- set the ADCs analog input range (see Figure 10). The voltage at REF- defines the input that produces an output code of all zeros, and the voltage at REF+ defines the input that produces an output code of all ones. The internal resistance from REF+ to REF- can be as low as 1kQ, and current will flow through it even when the MAX114/MAX118 are shut down. Figure 7d shows how an N-channel MOSFET can be connected to REF- tCSH be a t L -- AQ-A2 F ADDRESS 4 k VALID (N} WN NYE vat IN DO-D7 _ OLDDATA(N- 1) b { NEWDATA(N) Figure 6. Pipelined Mode Timing (WR = RD} (MODE = 1) GND MAXUM VoD MAX114 REF+ MAX118 MAAXLM xc 3.3pF REF- Ake See PWRDN i Vine IN_ Vine INL Vv GND co GND oT = MAXIM = MAXIM +5V Yoo Maxti4 - MAXi 14 + a. MAX118 +5V Vpp MAX118 ATF OF: REF. 4.7uF + O41 pF +2: we, Tv REFS + + ver = = REF- L | _ O4UF = 0.1UF = * CURRENT PATH MUST STILL L L EXIST FROM Vin. TO GND = = = Figure 7a. Power Supply as Reference Figure 7c. Input Not Referenced to GND +5V pp IN Those MAXIM - = MAXI14 MAX118 PWRON * IRML2402 Figure 7b. External Reference, 4.096V Full Scale MAXLAA Figure 7d. An N-channel MOSFET switches off the reference load during power-down BLLXVWVILLXVWMAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1LpA Power-Down to break this current path during power-down. The FET should have an on-resistance of less than 2Q with a 5V gate drive. When REF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a period of time equal to the power-up delay (tuP) plus the N- channel FETs turn-on time. Although REF+ is frequently connected to Vpp, the cir- cuit of Figure 7d uses a low-current, low-dropout, 4.096V voltage reference: the MAX874. Since the MAX874 cannot continuously furnish enough current for the reference resistance, this circuit is intended for applications where the MAX114/MAX118 are normally in standby and are turned on in order to make mea- surements at intervals greater than 65ys. C1 (the capacitor connected to REF+) is slowly charged by the MAX874 during the standby period, and furnishes the reference current during the short measurement period. C1s 3.3uF value ensures a voltage drop of less than 1/2LSB when performing four to eight successive con- versions. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C1. Initial Power-Up When power is first applied, perform a conversion to ini- tialize the MAX114/MAX118. Disregard the output data. Bypassing Use a 4.7pF electrolytic in parallel with a 0.1pF ceramic capacitor to bypass Vpp to GND. Minimize capacitor lead lengths. Bypass the reference inputs with 0.1pF capacitors, as shown in Figures 7a, 7b, and 7c. Analog Inputs Figure 8 shows the equivalent circuit of the MAX114/ MAX118 input. When a conversion starts and WR is low, VIN_ is connected to sixteen 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 32pF input capacitance allows source resis- tance as high as 800Q without setup problems. For larger resistances, the acquisition time (tacq) must be increased. Internal protection diodes, which clamp the analog input to Vpp and GND, allow the channel input pins to swing from GND - 0.3V to Vpp + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed Vpp by more than 50mvV or be lower than GND by 50mvV. If the analog input exceeds 50mV beyond the sup- plies, limit the input current to no more than 2mA, as excessive current will degrade the conversion accuracy of the on channel. Track/Hold The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the min- imum acquisition time, taca. maxim MAX114 MI MAX118 +tto Rov Vinz WA Ho 9 Wo o| Rin : DE L 1o 7 7 Rin Vin 2k Vin. WA 22pF 10pF I MAAXIAA MAX114 MAX118 iH Figure 8. Equivalent Input Circuit 10 Figure 9. RC Network Equivalent Input Model MAXIM+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1tA Power-Down Transfer Function Figure 10 shows the MAX114/MAX118s nominal trans- fer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = (VREF+ - VREF-) / 256. Conversion Rate The maximum sampling rate (fax) for the MAX114/ MAX118 is achieved in write-read mode (tRD < tiNTL), and is calculated as follows: 1 fMax =. twr + tap + trl + taca { 250ns + 250ns + 150ns + 160ns fMax = fMax = 1.23MHz where twR = the write pulse width, tap = the delay between write and read pulses, tRi = RD to INT delay, and taca = minimum acquisition time. Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequencys RMS amplitude to all other ADC output signals. The output spectrum is limit- ed to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADCs resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a per- fect 8-bit ADC can do no better than 50dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 195.8kHz sinusoid at a 1MHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution (or effective number of bits) the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD - 1.76) / 6.02 (see Typical Operating Characteristics). Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency MAXLAA OUTPUT CODE FULL-SCALE atti TRANSITION 11111110 11114101 | ! | I / | \ / | I / Ver. Vj ; / 1193 = B+ TF y 256 I / | 4 | I / I I / I / | ooooo0t | 00000010 ooooo001 Vrs oooooaa0 +++ +}+4 Ve 1 2 3 + S INPUT VOLTAGE (LSBs) FS-1LSB Figure 10. Transfer Function band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: [2 2 2 2 Vo + Ve + V5 +...M THD = 20log| +2 _3 4+ "" N __ \, where V1 is the fundamental RMS amplitude, and Ve through VN are the amplitudes of the 2nd through Nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a ran- dom peak in the ADCs noise floor. See the Signal-to- Noise Ratio graph in Typical Operating Characteristics. 11 BLLXVWVILLXVWMAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1LpA Power-Down __ Ordering Information (continued) Chip Information PART TEMP. RANGE PIN-PACKAGE MAX118CPI 0C to +70C 28 Wide Plastic DIP TRANSISTOR COUNT: 2011 MAX1 18CAI 0C to +70C 28 SSOP MAX1 18C/D 0C to +70C Dice* MAX1 18EPI -40C to +85C 28 Wide Plastic DIP MAX118EAI -40C to +85C 28 SSOP MAX1 18MuJl -55C to + 125C 28 Wide CERDIP** *Dice are specified at Ta = +25C, DC parameters only. Contact factory for availability. Pin Configurations TOP VIEW . Ins Li | [23] 1N7 na 1] 24] Yoo ins [2 | 127] Yoo ws [2| 23] ARON ina [3 | 26| PWRDN In2 [3] 22| AO ins [ay sl 0 Nt La] an axiaa [21] 4 no[s| AXA Fra a mooe [5] MAX114 20] D7 int [al MAX118 a] oo [| i] 08 move [7 | [22] 07 ot [7 ies vo [a | fet] D6 o [a [17] 04 ot [9 | [20] 05 os [| 6] cs 2 fro 19] D4 BD [io] 15] WARDY os [i] les Int Lia] ia] PEF D [12 17] WeRDY ano [ra] 13) Fe mr [ia] rg] rer DIP/SSOP uo [14] 15] ner DIP/SSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1996 Maxim Integrated Products Printed USA MAXUM is a registered trademark of Maxim Integrated Products.