19-4718; Rev 4; 2/11 KIT ATION EVALU E L B A AVAIL 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs The MAX9672/MAX9673/MAX9674 output 12/14/16 voltage references for gamma correction in TFT LCDs and one voltage reference for VCOM. Each gamma reference voltage has its own 10-bit DAC and buffer to ensure a stable voltage. The VCOM reference voltage has its own 10-bit DAC and an amplifier to ensure a stable voltage when critical levels and patterns are displayed. The MAX9672/MAX9673/MAX9674 feature integrated multiple-time programmable (MTP) memory to store gamma and VCOM values on the chip, eliminating the need for external EEPROM. The MAX9672/ MAX9673/MAX9674 support up to 300 write operations to the on-chip nonvolatile memory. The gamma outputs can drive 200mA peak transient current and settle within 1s. The VCOM output can provide 600mA peak transient current and also settles within 1s. The analog supply voltage range extends from 9V to 20V, and the digital supply voltage range extends from 2.7V to 3.6V. Gamma values and the VCOM value are programmed into registers through the I2C interface. Features o DAC Reference Input o 12/14/16-Channel Gamma Correction, 10-Bit Resolution o VCOM Driver o Integrated MTP Memory o Programmable VCOM Limits o 200mA Peak Current on Gamma Channels o 600mA Peak Current on VCOM Channel Ordering Information GAMMA CHANNELS PART MAX9672ETI+ 12 28 TQFN-EP* MAX9673ETI+ 14 28 TQFN-EP* MAX9674ETI+ 16 28 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Note: All devices are specified over the -40C to +85C temperature range. Functional Diagram Applications TFT LCDs REF GMA6 GMA5 GMA4 20 GMA8 REF 21 GMA7 AVDD Pin Configuration TOP VIEW PIN-PACKAGE 19 18 17 16 15 AVDD 10 10 10-BIT DAC GMA1 10 10 10-BIT DAC GMA2 10 10 10-BIT DAC GMA3 10 10 10-BIT DAC GMA4 10 10 10-BIT DAC GMA5 10 10 10-BIT DAC GMA6 10 10-BIT DAC GMA7 10 10-BIT DAC GMA8 10 10-BIT DAC GMA9 GMA9 22 14 GMA3 10 GMA10 23 13 GMA2 10 GMA11 24 12 GMA1 11 GND 10 10 10-BIT DAC GMA10 AVDD 10 10 10-BIT DAC GMA11 AVDD_AMP 10 10 10-BIT DAC GMA12 VCOM_FB 10 10 10-BIT DAC GMA13* 10 10 10-BIT DAC GMA14* 10 10 10-BIT DAC GMA15** 10 10 10-BIT DAC GMA16** 10 10 10-BIT DAC MAX9672 MAX9673 MAX9674 GMA12 25 GMA13* 26 GMA14* 27 10 9 EP + 8 GMA15** 28 10 DAC REGISTERS 7 THIN QFN (5mm x 5mm) EP = EXPOSED PAD, CONNECT EP TO GROUND PLANE. *N.C. FOR THE MAX9672 **N.C. FOR THE MAX9672 AND THE MAX9673 I2C REGISTERS VCOM 6 AGND_AMP 5 DVDD 4 A0 SDA 3 SCL 2 GMA16** 1 MTP MEMORY AVDD_AMP VCOM DVDD SDA SCL A0 GND MAX9672 MAX9673 MAX9674 I2C INTERFACE *NOT AVAILABLE FOR THE MAX9672 **NOT AVAILABLE FOR THE MAX9672 AND THE MAX9673 AGND_AMP VCOM_FB GND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9672/MAX9673/MAX9674 General Description MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs ABSOLUTE MAXIMUM RATINGS Supply Voltages AVDD, REF to GND ............................................-0.3V to +22V AVDD_AMP to AGND_AMP................................-0.3V to +22V AVDD to AVDD_AMP.........................................-0.3V to +0.3V DVDD to GND.......................................................-0.3V to +4V AGND_AMP to GND..........................................-0.1V to +0.1V Outputs GMA1-GMA16 ...................................-0.3V to (VAVDD + 0.3V) VCOM .........................................-0.3V to (VAVDD_AMP + 0.3V) Inputs SDA, SCL..............................................................-0.3V to +6V VCOM_FB...................................-0.3V to (VAVDD_AMP + 0.3V) SDA, SCL..........................................................................20mA GMA1-GMA16................................................................200mA VCOM .............................................................................600mA Continuous Power Dissipation (TA = +70C) 28-Pin TQFN-EP (derate 28.6mW/C above +70C) ........................................................2285.7mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) ...................................... +260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = 18V, VAVDD_AMP = VREF = 18V, VDVDD = 3.3V, VGND = VAGND_AMP = 0, VCOM = VCOM_FB, no load, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 9 20 V 20 V SUPPLIES Analog Supply Voltage Range VAVDD, VAVDD_AMP Analog Supply Voltage Range for Programming MTP VAVDD_MTP 15 Digital Supply Voltage Range VDVDD 2.7 3.6 V Analog Quiescent Current IAVDD 20 35 mA VCOM Quiescent Current IAVDD_AMP 2.7 5.6 mA Digital Quiescent Current IDVDD Guaranteed by total output error During a register mode load event 400 No SCL or SDA transitions 260 Thermal Shutdown Thermal-Shutdown Hysteresis Undervoltage Lockout Threshold UVLO DVDD undervoltage lockout voltage threshold A +160 C 15 C 2.3 REF Input Resistance 600 2.6 384 V k VCOM OUTPUT (VCOM) Resolution RES Integral Nonlinearity Error INL 0.125 1 LSB Differential Nonlinearity Error DNL 0.125 1 LSB Total Output Error VERR Code = 512, VAVDD_AMP = 9V and 20V, TA = +25C +40 mV Total Output-Error Drift VERR Code = 512 15 Output-Voltage Low VOUT TA = +25C, sinking 100mA 0.4 2 10 Bits -40 _______________________________________________________________________________________ V/C 0.85 V 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs (VAVDD = 18V, VAVDD_AMP = VREF = 18V, VDVDD = 3.3V, VGND = VAGND_AMP = 0, VCOM = VCOM_FB, no load, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS Output-Voltage High VOUT TA = +25C, sourcing 100mA Power-Supply Rejection Ratio PSRR To AVDD_AMP, f = 60kHz, REF shorted to VAVDD_AMP 9V VAVDD_AMP 20V MIN TYP MAX VAVDD_AMP VAVDD_AMP - 1.1 - 0.6 40 60 UNITS V dB 90 Output Load Regulation LR Transient -80mA to +80mA, code = 512 0.1 mV/mA Continuous Output Current IO Code = 512 (Note 2) 80 mA 9V VAVDD_AMP 20V 600 mA Short-Circuit Current Slew Rate SR Swing 4VP-P at VCOM, 10% to 90%, RL = 10k, CL = 50pF (Note 3) 100 V/s Program to Output Delay tD From SCL rising edge for ACK bit after programming VCOM to 50% voltage change at output 0.8 s Bandwidth BW RS = 10k, CL = 50pF (Note 3) 60 MHz Noise eN RMS noise voltage (10MHz BW) 375 V DAC OUTPUTS (GMA1-GMA16) Resolution RES Guaranteed monotonic 10 Bits Integral Nonlinearity Error INL 0.125 1 LSB Differential Nonlinearity Error DNL 0.125 1 LSB Total Output Error VERR Code = 512, VAVDD = 9V and 20V, TA = +25C +40 mV Output-Voltage Low VOUT TA = +25C, sinking 10mA 0.28 V Output-Voltage High VOUT TA = +25C, sourcing 10mA Power-Supply Rejection Ratio PSRR To AVDD, f = 60kHz, REF shorted to AVDD 9V VAVDD 20V -40 0.15 VAVDD - 0.38 VAVDD - 0.25 40 60 V dB 90 Load Regulation LR -12mA to +12mA 0.5 mV/mA Short-Circuit Current ISC Outputs to AVDD or GND 200 mA Output Impedance ZO Output resistance when output is disabled 84 k Slew Rate SR Swing 5VP-P at input, 10% to 90% measurement on output 22 V/s Program to Output Delay tD From SCL rising edge for ACK bit after programming gamma to 50% voltage change at output 0.8 s Noise eN RMS noise voltage at any output (10MHz BW) 375 V f = 5MHz, all channels to all channels 80 dB Channel-to-Channel Isolation CXTLK _______________________________________________________________________________________ 3 MAX9672/MAX9673/MAX9674 ELECTRICAL CHARACTERISTICS (continued) MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 18V, VAVDD_AMP = VREF = 18V, VDVDD = 3.3V, VGND = VAGND_AMP = 0, VCOM = VCOM_FB, no load, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (SDA, SCL) Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIH, IIL 0.7 x VDVDD 0.3 x VDVDD VIN = 0V or VDVDD -1 Input Capacitance Power-Down Input Current SDA Output Low Voltage V +0.01 +1 5 IIN VOL VDVDD = 0V, VIN = 2V -10 ISINK = 6mA V A pF +10 A 0.4 V 400 kHz I2C TIMING CHARACTERISTICS (Figure 1) Serial-Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 s Hold Time (REPEATED) START Condition tHD,STA 0.6 s SCL Pulse-Width Low tLOW 1.3 s SCL Pulse-Width High tHIGH 0.6 s Setup Time for a REPEATED START Condition tSU,STA 0.6 s Data Hold Time tHD,DAT 0 Data Setup Time tSU,DAT 100 900 ns ns SDA and SCL Receiving Rise Time tR (Note 4) 20 + 0.1CB 300 ns SDA and SCL Receiving Fall Time tF (Note 4) 20 + 0.1CB 300 ns tF,TX (Note 4) 20 + 0.1CB 250 ns SDA Transmitting Fall Time Setup Time for STOP Condition tSU,STO Bus Capacitance CB Pulse Width of Suppressed Spike tSP Note 1: Note 2: Note 3: Note 4: 4 0.6 0 All devices are 100% production tested at TA = +25C. All temperature limits are guaranteed by design. Thermal pad attached to multilayered board. Exceeding this limit may cause the thermal shutdown to trip. Measured with the VCOM amplifier configured as an inverting unity-gain amplifier (RS = RF = 1k). CB is in pF. _______________________________________________________________________________________ s 400 pF 50 ns 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs OUTPUT OFFSET-VOLTAGE DISTRIBUTION GAMMA LOAD REGULATION 15 10 15 5 5 0 -5 -10 -15 0 -20 -40 -30 -20 -10 0 10 20 30 40 -20 -15 -10 -5 0 5 OUTPUT OFFSET (mV) LOAD CURRENT (mA) VCOM LOAD REGULATION DNL GAMMA 0.25 MAX9672/73/74 toc03 60 40 0.20 0.15 0.10 20 DNL (LSB) LOAD REGULATION (mV) 10 0 -20 10 15 20 MAX9672/73/74 toc04 N (%) 20 MAX9672/73/74 toc02 25 20 LOAD REGULATION (mV) MAX9672/73/74 toc01 30 0.05 0 -0.05 -0.10 -0.15 -40 -0.20 -60 -0.25 -100 -50 0 50 150 0 CODE (UNITS) DNL VCOM GAMMA INL 0.25 MAX9672/73/74 toc05 0.20 0.15 0.10 0 -0.05 0.15 0.10 0.05 0 -0.05 -0.10 -0.10 -0.15 -0.15 -0.20 -0.20 -0.25 -0.25 128 256 384 512 640 768 896 1024 CODE (UNITS) VREF = 10V 0.20 INL (LSB) 0.05 0 128 256 384 512 640 768 896 1024 LOAD CURRENT (mA) 0.25 DNL (LSB) 100 MAX9672 toc06 -150 0 128 256 384 512 640 768 896 1024 CODE (UNITS) _______________________________________________________________________________________ 5 MAX9672/MAX9673/MAX9674 Typical Operating Characteristics (VAVDD = VAVDD_AMP = VREF = 18V, VDVDD = 3.3V, VGND = VAGND_AMP = 0, no load, unless otherwise noted. Typical values are at TA = +25C.) Typical Operating Characteristics (continued) (VAVDD = VAVDD_AMP = VREF = 18V, VDVDD = 3.3V, VGND = VAGND_AMP = 0, no load, unless otherwise noted. Typical values are at TA = +25C.) VCOM INL GAMMA INL 0.20 0.15 0.2 0.10 0.1 INL (LSB) 0 -0.1 0.05 0 -0.05 -0.10 -0.2 -0.15 -0.3 -0.20 -0.4 -0.25 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE (UNITS) CODE (UNITS) VCOM INL GAMMA DNL 0.12 MAX9672/73/74 toc09 0.25 0.20 0.15 0.10 MAX9672 toc10 INL (LSB) MAX9672/73/74 toc08 VREF = 10V 0.3 0.25 MAX9672 toc07 0.4 0.08 0.04 0.05 DNL (LSB) INL (LSB) 0 -0.05 0 -0.04 -0.10 -0.15 -0.08 -0.20 -0.25 0 -0.12 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE (UNITS) CODE (UNITS) VCOM DNL MAX9672 toc11 0.20 VREF = 10V 0.15 0.10 DNL (LSB) MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs 0.05 0 -0.05 -0.10 -0.15 -0.20 0 128 256 384 512 640 768 896 1024 CODE (UNITS) 6 _______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs POWER-SUPPLY REJECTION RATIO vs. FREQUENCY, GAMMA OUTPUTS POWER-SUPPLY REJECTION RATIO vs. FREQUENCY, VCOM OUTPUT -30 -30 PSRR (dB) -50 -60 -60 -70 -70 -80 -80 100k 10M 1M 100k 10M 1M FREQUENCY (Hz) REFERENCE REJECTION RATIO vs. FREQUENCY, GAMMA OUTPUTS REFERENCE REJECTION RATIO vs. FREQUENCY, VCOM OUTPUT VRIPPLE = 200mVP-P CODE = 512 -20 -30 -40 -50 -60 0 MAX9672 toc15 MAX9672 toc14 0 -10 10k FREQUENCY (Hz) REFERENCE REJECTION RATIO (dB) 10k REFERENCE REJECTION RATIO (dB) -40 -50 VRIPPLE = 200mVP-P CODE = 512 -10 -20 -30 -40 -50 -60 -70 -70 -80 -80 100k 10k 10M 1M 100k 10M 1M FREQUENCY (Hz) FREQUENCY (Hz) VCOM PULSE RESPONSE GAMMA PULSE RESPONSE MAX9672/73/74 toc16 10k RISO = 10 CLOAD = 68nF IOUT 250mA/div RISO = 10 CLOAD = 10nF IOUT 50mA/div -2.5V TO +2.5V RISO MAX9672/73/74 toc17 PSRR (dB) -20 -40 VRIPPLE = 200mVP-P CODE = 512 -10 -20 MAX9672 toc13 VRIPPLE = 200mVP-P CODE = 512 -10 0 MAX9672 toc12 0 -2.5V TO +2.5V RISO VCOM DAC GAMMA DAC CLOAD CLOAD VOUT 1V/div VOUT 250mV/div TIME (2s/div) TIME (2s/div) _______________________________________________________________________________________ 7 MAX9672/MAX9673/MAX9674 Typical Operating Characteristics (continued) (VAVDD = VAVDD_AMP = VREF = 18V, VDVDD = 3.3V, VGND = VAGND_AMP = 0, no load, unless otherwise noted. Typical values are at TA = +25C.) 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs MAX9672/MAX9673/MAX9674 Pin Description PIN NAME MAX9673 1, 28 MAX9674 -- -- -- 1 GMA16 2 2 2 SCL I2C-Compatible Serial-Clock Input 3 3 3 SDA I2C-Compatible Serial-Data Input/Output 4 5 6 4 5 6 4 5 6 A0 DVDD AGND_AMP 7 7 7 VCOM 8 8 8 VCOM_FB 9 9 9 AVDD_AMP 10, 21 10, 21 10, 21 AVDD Analog Power Supply. Bypass AVDD with a 0.1F capacitor to GND. 11 11 11 GND Analog Ground 12 12 12 GMA1 Gamma DAC Analog Output 1 13 13 13 GMA2 Gamma DAC Analog Output 2 14 14 14 GMA3 Gamma DAC Analog Output 3 15 15 15 GMA4 Gamma DAC Analog Output 4 16 16 16 GMA5 Gamma DAC Analog Output 5 17 17 17 GMA6 Gamma DAC Analog Output 6 18 18 18 GMA7 Gamma DAC Analog Output 7 19 19 19 GMA8 Gamma DAC Analog Output 8 20 20 20 REF 22 22 22 GMA9 Gamma DAC Analog Output 9 23 23 23 GMA10 Gamma DAC Analog Output 10 24 24 24 GMA11 Gamma DAC Analog Output 11 25 25 25 GMA12 Gamma DAC Analog Output 12 -- 26 26 GMA13 Gamma DAC Analog Output 13 -- 27 27 GMA14 Gamma DAC Analog Output 14 -- -- 28 GMA15 Gamma DAC Analog Output 15 -- -- -- EP N.C. Detailed Description The MAX9672/MAX9673/MAX9674 feature 13/15/17 total programmable reference voltage channels. Each channel has a 10-bit DAC to create the reference voltage. One channel has an amplifier that follows the DAC while all other channels have a buffer after the DAC. The MAX9672/MAX9673/MAX9674 feature integrated 8 FUNCTION MAX9672 1, 26, 27, 28 No Connection. Not internally connected. Gamma DAC Analog Output 16 I2C-Compatible Device Address Bit 0 Digital Power Supply. Bypass DVDD with a 0.1F capacitor to GND. Ground for VCOM Amplifier VCOM Output Feedback for VCOM Amplifier Power Supply for VCOM Amplifier. Bypass AVDD_AMP with a 0.1F capacitor to AGND_AMP. DAC Reference Input Exposed Pad. EP is internally connected to the analog ground and digital ground. EP must be connected to the system's ground. MTP memory to store gamma and VCOM values on the chip, eliminating the need for external EEPROM. The MAX9672/MAX9673/MAX9674 support up to 300 write operations to the on-chip nonvolatile memory. The MAX9672/MAX9673/MAX9674 can provide the gamma, VCOM, and possibly level-shifter reference voltages for an LCD panel that can potentially replace a discrete digital variable resistor (DVR), VCOM amplifier, _______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs 10-Bit DACs The voltage at REF sets the full-scale output of the DACs. Determine the output voltage using the following equation: VOUT = (VREF x CODE)/2N where CODE is the numeric value of the DAC's binary input code and N is the bits of resolution. For the MAX9672/MAX9673/MAX9674, N = 10 and CODE ranges from 0 to 1023. The DAC can never output REF because the maximum value of CODE is always 1 least significant bit (LSB) less than the reference. For example, if VREF = 16V and CODE = 1023, then the output voltage is: VOUT = (16V x 1023)/210 = 15.98438V Gamma Buffers The gamma buffers are guaranteed to source or sink 10mA of DC current within 200mV of the supplies. The source drivers can kick back a great deal of current to the buffer outputs during a horizontal line change or a polarity switch. The DAC output buffers can source/sink 200mA of peak current to reduce the recovery time of the output voltages when critical levels and patterns are displayed. VCOM Amplifier The operational amplifier attached to the VCOM DAC holds the VCOM voltage stable while providing the ability to source and sink 600mA into the backplane of a TFT LCD panel. The operational amplifier can directly drive the capacitive load of the TFT LCD backplane without the need for a series resistor in most cases. The VCOM amplifier has current limiting on its output to protect its bond wires. If the application requires more than 600mA, buffer the output of the VCOM amplifier with a MAX9650, a VCOM power amplifier. The MAX9650 can source or sink 1A of current. Thermal Shutdown The MAX9672/MAX9673/MAX9674 feature thermalshutdown protection with temperature hysteresis. When the die temperature reaches +165C, all of the gamma outputs are disabled. When the die cools down by 15C, the outputs are enabled again. I2C Serial Interface The MAX9672/MAX9673/MAX9674 feature an I 2 C/ SMBusTM-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9672/MAX9673/MAX9674 and the master at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9672/MAX9673/MAX9674 by transmitting the SDA tSU,STA tSU,DAT tHD,DAT tLOW tBUF tHD,STA tSP tSU,STO SCL tHIGH tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. I2C Serial-Interface Timing Diagram SMBus is a trademark of Intel Corp. _______________________________________________________________________________________ 9 MAX9672/MAX9673/MAX9674 gamma buffers, high-voltage linear regulator, and resistor strings. The high-voltage linear regulator can be eliminated because the DAC contains a lowpass filter that reduces horizontal line frequency noise by 50dB. Power sequencing is well controlled since a single chip generates all the various reference voltages needed for the LCD panel. Each part has an I2C interface for programming both the MTP memory and the I2C registers. With the MTP memory and the I 2 C interface, the MAX9672/MAX9673/MAX9674 enable automatic gamma and automatic flicker calibration on a panel-bypanel basis on the production line. Contact your Maxim representative for more details. MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each byte is serially transmitted to the MAX9672/MAX9673/MAX9674 as 8 bits and is followed by an acknowledge clock pulse. A master reading data from the MAX9672/MAX9673/MAX9674 transmit the proper slave address followed by a series of nine SCL pulses. The MAX9672/MAX9673/MAX9674 transmit data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9672/MAX9673/MAX9674 from highvoltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX9672/MAX9673/MAX9674. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9672/MAX9673/MAX9674 use a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. 10 Table 1. Slave Address A0 GND DVDD READ ADDRESS E9h EBh S WRITE ADDRESS E8h EAh Sr P SCL SDA Figure 2. START, STOP, and REPEATED START Conditions CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 3. Acknowledge Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the MAX9672/MAX9673/ MAX9674 to read mode. Set the R/W bit to 0 to configure the MAX9672/MAX9673/MAX9674 to write mode. The address is the first byte of information sent to the MAX9672/MAX9673/MAX9674 after the START condition. The MAX9672/MAX9673/MAX9674 slave address is configured with A0. Table 1 shows the possible addresses for the MAX9672/MAX9673/MAX9674. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9672/MAX9673/MAX9674 use to handshake receipt of each byte of data when in write mode (see Figure 3). The MAX9672/MAX9673/MAX9674 pull down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 S SLAVE ADDRESS 0 W1 W0 X ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 A 0 0 REGISTER ADDRESS A X X ACKNOWLEDGE FROM MAX9672/MAX9673/MAX9674 X D9 D8 DATA BYTE 1 MAX9672/MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/MAX9673/MAX9674 D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE 2 A P 1 WORD R/W M1 M0 AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 4. Writing a Word of Data to the MAX9672/MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/MAX9673/MAX9674 S 0 SLAVE ADDRESS ACKNOWLEDGE FROM MAX9672/MAX9673/MAX9674 A 0 0 REGISTER ADDRESS ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 W1 W0 X D7 D6 D5 D4 D3 D2 D1 D0 A X X X D9 D8 DATA BYTE 1 A DATA BYTE 2 A 1 WORD R/W M1 M0 AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 W1 W0 X D7 D6 D5 D4 D3 D2 D1 D0 X X X D9 D8 DATA BYTE n-1 A DATA BYTE n A P 1 WORD Figure 5. Writing n Bytes of Data to the MAX9672/MAX9673/MAX9674 a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9672/ MAX9673/MAX9674 are in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9672/MAX9673/MAX9674, followed by a STOP condition. Write Data Format A write to the MAX9672/MAX9673/MAX9674 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte of data to configure the internal register address pointer, one word (two bytes) of data or more, and a STOP condition. Figure 4 illustrates the proper frame format for writing one word of data to the MAX9672/MAX9673/MAX9674. Figure 5 illustrates the frame format for writing n-bytes of data to the MAX9672/MAX9673/MAX9674. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9672/ MAX9673/MAX9674. The MAX9672/MAX9673/MAX9674 acknowledge receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9672/MAX9673/MAX9674's internal register address pointer. The MAX9672/MAX9673/ MAX9674's internal address pointer consists of the 6 LSBs of the second byte. The 2 MSBs of the second byte (M1 and M0) are set to 00b when writing to the internal registers. See the Memory section for more details. The pointer tells the MAX9672/MAX9673/ MAX9674 where to write the next byte of data. An acknowledge pulse is sent by the MAX9672/ MAX9673/MAX9674 upon receipt of the address pointer data. The third and fourth bytes sent to the MAX9672/ MAX9673/MAX9674 contain the data that is written to the chosen register and which type of register it writes to, volatile (DAC) or nonvolatile memory (MTP). See the Registers section for more details. An acknowledge pulse ______________________________________________________________________________________ 11 MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs Table 2. Register Map REGISTER ADDRESS REGISTER NAME READ/ WRITE MAX9672 MAX9673 MAX9674 0x00 GMA1 Gamma 1 0x3B0 0x3BA 0x3C2 Read and write 0x01 GMA2 Gamma 2 0x361 0x376 0x386 Read and write 0x02 GMA3 Gamma 3 0x312 0x332 0x34A Read and write 0x03 GMA4 Gamma 4 0x2C4 0x2EE 0x30E Read and write 0x04 GMA5 Gamma 5 0x275 0x2AA 0x2D2 Read and write 0x05 GMA6 Gamma 6 0x226 0x265 0x295 Read and write 0x06 GMA7 Gamma 7 0x1D8 0x221 0x259 Read and write 0x07 GMA8 Gamma 8 0x189 0x1DD 0x21D Read and write 0x08 GMA9 Gamma 9 0x13A 0x199 0x1E1 Read and write 0x09 GMA10 Gamma 10 0x0EC 0x155 0x1A5 Read and write 0x0A GMA11 Gamma 11 0x09D 0x110 0x169 Read and write 0x0B GMA12 Gamma 12 0x04E 0x0CC 0x12C Read and write 0x0C GMA13 Gamma 13 -- 0x088 0X0F0 Read and write 0x0D GMA14 Gamma 14 -- 0x044 0x0B4 Read and write 0x0E GMA15 Gamma 15 -- -- 0x078 Read and write 0x0F GMA16 Gamma 16 -- -- 0x03C Read and write 0x10 Reserved -- -- -- -- -- 0x11 Reserved -- -- -- -- -- 0x12 VCOM Common voltage 0x193 0x193 0x193 Read and write 0x13 Reserved -- -- -- -- -- 0x14 Reserved -- -- -- -- -- 0x15 Reserved -- -- -- -- -- 0x16 Reserved -- -- -- -- -- 0x17 Reserved -- -- -- -- -- 0x18 VCOMMIN Minimum VCOM value 0x10D 0x10D 0x10D Read and write 0x19 VCOMMAX Maximum VCOM value 0x21A 0x21A 0x21A Read and write 0x1D Reserved, DO NOT WRITE -- -- -- -- -- 0x1E Reserved, DO NOT WRITE -- -- -- -- -- from the MAX9672/MAX9673/MAX9674 signals receipt of each data byte. The address pointer autoincrements to the next register address after receiving every other data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition. 12 MTP FACTORY INTIALIZATION VALUE REGISTER DESCRIPTION If data is written into register address 0x1E, the address pointer autoincrements to 0xFF and stays at 0xFF until the master writes a new value into the register address pointer. Read Data Format The master presets the address pointer by first sending the MAX9672/MAX9673/MAX9674's slave address with the R/W bit set to 0 followed by the register address ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs REG GMA1 GMA2 GMA3 GMA4 GMA5 GMA6 GMA7 GMA8 GMA9 GMA10 GMA11 GMA12 GMA13* GMA14* GMA15** GMA16** Reserved Reserved VCOM Reserved Reserved Reserved Reserved Reserved VCOMMIN VCOMMAX Reserved DO NOT WRITE Reserved DO NOT WRITE REG ADDR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 -- -- W1 -- -- -- -- -- W1 W1 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 W0 -- -- W0 -- -- -- -- -- W0 W0 X X X X X X X X X X X X X X X X -- -- X -- -- -- -- -- X X X X X X X X X X X X X X X X X X -- -- X -- -- -- -- -- X X X X X X X X X X X X X X X X X X -- -- X -- -- -- -- -- X X X X X X X X X X X X X X X X X X -- -- X -- -- -- -- -- X X b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 -- -- b9 -- -- -- -- -- b9 b9 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 -- -- b8 -- -- -- -- -- b8 b8 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 -- -- b7 -- -- -- -- -- b7 b7 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 -- -- b6 -- -- -- -- -- b6 b6 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 -- -- b5 -- -- -- -- -- b5 b5 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 -- -- b4 -- -- -- -- -- b4 b4 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 -- -- b3 -- -- -- -- -- b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 -- -- b2 -- -- -- -- -- b2 b2 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 -- -- b1 -- -- -- -- -- b1 b1 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 -- -- b0 -- -- -- -- -- b0 b0 0x1D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0x1E -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- *Reserved for the MAX9672. **Reserved for the MAX9672/MAX9673. with M1 and M0 set to 00 after a START condition. The MAX9672/MAX9673/MAX9674 acknowledge receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9672/ MAX9673/MAX9674 transmit the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after every other read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 0x00. Subsequent reads autoincrement the address pointer until the next STOP condition. Attempting to read from register addresses higher than 0x1E results in repeated reads from a dummy register containing all one data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the ______________________________________________________________________________________ 13 MAX9672/MAX9673/MAX9674 Table 3. Register Description MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs Table 4. Write Control Bits W1 W0 ACTION 0 0 0 1 All MTP registers get updated when the current I2C register has finished updating (end of B0). 1 0 All DAC registers get updated when the current I2C register has finished updating (end of B0). 1 1 No update. No update. Table 5. Memory Write Bits M1 M0 ACTION 0 0 None. 0 1 Only the addressed I2C registers and DAC registers get set to the MTP values. 1 0 All I2C registers and DAC registers get set to the MTP values. 1 1 None. last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 6 and 7 illustrate the frame format for reading data from the MAX9672/MAX9673/MAX9674. Registers Register Map The MAX9672/MAX9673/MAX9674 have a bank of nonvolatile MTP memory and two banks of volatile memory comprised of I2C registers and DAC registers. Each memory location whether in nonvolatile or volatile memory holds a 10-bit word. Two bytes must be read or written through the I2C interface for every 10-bit word. Table 2 shows the register map. The same register address and register name exists in the MTP memory bank, I2C register bank, and the DAC register bank. The write control bits determine which memory location the data is stored into. Register Description Only the 10 LSBs are written to the registers (see Table 3). During a write operation, the write control bits (the 2 MSBs) are stripped from the incoming data stream and are used to determine whether the MTP or DAC registers are updated (see Table 4). VCOM Programmable Range The MAX9672/MAX9673/MAX9674 feature the programmable range for VCOM. VCOMMIN and VCOMMAX registers provide low and high limits for the VCOM DAC register. At the factory, VCOMMIN is set to 0 and VCOMMAX is set to 1023 (default values) to provide the 14 full rail-to-rail programmable range for VCOM. Later, users can define their own limits by programming VCOMMIN and VCOMMAX registers and MTP. VCOM register values are limited to the defined range. This means if the VCOM register accidentally gets programmed with a value higher than VCOMMAX, it automatically gets locked to the VCOMMAX value. The I2C bus does acknowledge and receive the data sent on the bus. However, internally the part recognizes that the value is outside of the range and adjusts it accordingly. The same scenario is true if the value programming VCOM is below VCOMMIN. Memory The MAX9672/MAX9673/MAX9674 include both volatile memory (I2C and DAC) and nonvolatile memory (MTP). It is possible to write to each single DAC memory location from an MTP memory location individually or to write to all at once. This is done with memory write bits (M1, M0) that are the 2 MSBs of the register address byte. Table 5 shows the memory write bits. Set both M1 and M0 to low or high when writing to or reading from the register values through the I2C bus. Volatile Memory The MAX9672/MAX9673/MAX9674 feature a doublebuffered register structure. The volatile (DAC) memory can be updated without updating the output voltage. Figure 8 shows how to program a single DAC. The output voltage is updated after sending the LSB (D0). ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs S SLAVE ADDRESS 0 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 A 0 0 REGISTER ADDRESS R/W MAX9672/MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 A Sr SLAVE ADDRESS 1 A R/W REPEATED START M1 M0 ACKNOWLEDGE FROM MASTER X X X X X NOT ACKNOWLEDGE FROM MASTER X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE 1 A DATA BYTE 2 A P 1 WORD AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 6. Reading One Indexed Word of Data from the MAX9672/MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 S SLAVE ADDRESS 0 A 0 0 REGISTER ADDRESS ACKNOWLEDGE FROM MAX9672/ MAX9673/MAX9674 A Sr SLAVE ADDRESS REPEATED START R/W 1 A R/W M1 M0 ACKNOWLEDGE FROM MASTER X X X X X X D9 D8 DATA BYTE 1 ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER X D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE 2 A X X X X X D9 D8 DATA BYTE n-1 1 WORD NOT ACKNOWLEDGE FROM MASTER D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE n A P 1 WORD AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 7. Reading n Bytes of Indexed Data from the MAX9672/MAX9673/MAX9674 ______________________________________________________________________________________ 15 MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 1 0 X X X X D9 D8 A 0 0 M1 M0 D7 D6 D5 D4 D3 D2 D1 D0 A DAC/VCOM ADDRESS D5 DATA D4 D3 D2 D1 D0 A D2 D1 D0 A P DATA Figure 8. Single DAC Programming S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 0 0 X X X X D9 D8 A 0 0 M1 M0 D7 D6 D5 0 X X D5 0 X X X D4 D3 D2 D1 D0 A D2 D1 D0 A D2 D1 D0 A DATA X D9 D8 A D7 D6 D5 DATA 1 D3 DAC/VCOM ADDRESS DATA 0 D4 D4 D3 DATA X X D9 D8 A DATA D7 D6 D5 D4 D3 P DATA Figure 9. Multiple (or All) DACs Programming It is possible to write to multiple DACs first then update the output voltage of all channels simultaneously, as shown in Figure 9. In this mode, it is possible for the I2C master to write to all registers of the MAX9672/ MAX9673/MAX9674 (Gamma and VCOM) in one communication. In that case, the value programmed on addresses 0x10, 0x11, and 0x13 through 0x17 are meaningless. However, the MAX9672/MAX9673/MAX9674 send an acknowledge bit for each of the 2 bytes on any of these addresses. The control bits (W1, W0) shown in Figure 9 are set in a way that all DACs are programmed to their desired value with no changes to the output voltages until the LSB of the last DAC is received and then all the channels are updated simultaneously. Nonvolatile Memory The MAX9672/MAX9673/MAX9674 are able to write to nonvolatile memory (MTP) of any single DAC/VCOM register in a single or burst I2C transaction. This memory 16 can be written to at least 300 times. Figure 10 shows a single write to a MTP address. The control bits on Figure 10 set in a way that the MTP register is updated at the end of the LSB (D0). Figure 11 shows how to program multiple MTP registers in one communication transition. Similar to programming the volatile memory, the first 2 bytes of data correspond to the DAC/VCOM address specified by the master on the previous byte and the following 2 bytes of data correspond to the next address and so on. In this configuration all the MTP registers are programmed at the same time following the LSB of the last set of data bytes. (The last set of data bytes is different than the previous bytes as it is bits 15 and 14.) If for some reason the master issues a STOP condition before sending the last 2 bytes of the data with appropriate values of bits 15 and 14 (01), then none of the MTP registers are updated. ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 0 1 X X X X D9 D8 A 0 0 M1 M0 D7 D6 D5 D4 D3 D2 D1 D0 A MAX9672/MAX9673/MAX9674 S DAC/VCOM ADDRESS D5 DATA D4 D3 D2 D1 D0 A D2 D1 D0 A P DATA Figure 10. Single MTP Programming S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 0 0 X X X X D9 D8 A 0 0 M1 M0 D7 D6 D5 0 X X D5 1 X X X D4 D3 D2 D1 D0 A D2 D1 D0 A D2 D1 D0 A DATA X D9 D8 A D7 D6 D5 DATA 0 D3 DAC/VCOM ADDRESS DATA 0 D4 D4 D3 DATA X X D9 D8 A DATA D7 D6 D5 D4 D3 P DATA Figure 11. Multiple MTP Programming Programming the MTP registers also updates the DACs/VCOM volatile memory as well as the output voltages. Similar to multiple volatile memory programming, the update only occurs after the LSB of the last byte is received. All the outputs are programmed and updated simultaneously. However, depending on the number of MTP registers, it takes 31ms to 500ms to store the values into the nonvolatile memory. During this time, the MAX9672/MAX9673/MAX9674 are not available on the I2C and any communication from the master should be delayed until the MTP is programmed. Any attempt from the I2C master to talk to the MAX9672/MAX9673/ MAX9674 is not acknowledged. General and Single Acquire Commands It is possible to update all the DAC outputs to the previously stored MTP values with one special command. Set the 2 MSBs (M1 and M0) of the DAC/VCOM address to 10 to set all the DACs and the output voltages to the values of MTP (as shown in Figure 12). The MAX9672/MAX9673/MAX9674 ignore the DAC/VCOM address in this case. It is also possible to update the DAC and output voltage of only one channel from the MTP. Set the 2 MSBs (M1 and M0) of the DAC/VCOM address to 01 (as shown in Figure 13) to move a specific value from MTP into the DAC and output voltage of a single channel. The MAX9672/MAX9673/MAX9674 feature a doublebuffered register structure. It is important to note that updating the volatile (DAC) memory is not the same as updating the output voltage. It is possible to write to multiple DACs first then update the output voltage of all channels simultaneously. ______________________________________________________________________________________ 17 MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 1 0 0 M1 M0 0 0 0 0 0 P A Figure 12. General Acquire Command to Update All Outputs with MTP S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 0 1 M1 M0 D5 D4 D3 D2 D1 D0 A P DAC/VCOM ADDRESS Figure 13. Single Acquire Command to Update One Output with MTP Applications Information Driving the Resistor Ladders with More Current If the gamma buffers cannot provide enough current to drive the ends of the resistor ladders, then attach an additional resistor from the nearest supply. For example, at the very top of the resistor ladder, attach an additional resistor to AVDD. At the very bottom of the resistor ladder, attach an additional resistor to GND. The MAX9672/MAX9673/MAX9674 greatly diminish any noise from AVDD supply through the discrete resistor because the high-frequency noise from AVDD has been attenuated, and the buffers have excellent AC PSRR. See Figure 14. VCOM Operational Amplifier with Feedback Resistors The output (VCOM) and negative input (VCOM_FB) of the operational amplifier would usually be connected together, resulting in a unity-gain configuration. If a higher, closed-loop gain is desired, add feedback resistors as shown in Figure 15. Power-Up and Power-Down Figures 16 and 17 show the proper startup sequence of the MAX9672/MAX9673/MAX9674. The digital supply must be powered up first. The analog supply should not be powered up for at least 250s (typ) after the digital supply has been powered up. During this time, the MTP register values are overwriting the default values in the I2C registers. Once AVDD is above approximately 8V, the output buffers have enough headroom to power up. 18 If REF is powered up after AVDD, then the outputs track REF. If REF is powered up before AVDD, then the outputs track AVDD. For power-down, AVDD and REF must be powered down first to 0V, and then DVDD can safely be powered down. Power Supplies and Bypass Capacitors The MAX9672/MAX9673/MAX9674 operate from a single 9V to 20V analog supply (AVDD) and a 2.7V to 3.6V digital supply (DVDD). Bypass AVDD to GND with 0.1F and 10F capacitors in parallel. Use an extensive ground plane to ensure optimum performance. Bypass DVDD to GND with a 0.1F capacitor. The 0.1F bypass capacitors should be as close as possible to the device. Refer to the MAX9672/MAX9673/MAX9674 evaluation kit for a proven PCB layout. Layout and Grounding Exposed Pad If the MAX9672/MAX9673/MAX9674 are mounted using reflow soldering or wave soldering, the ground via(s) for the exposed pad should have a finished hole size of at least 14 mils to insure adequate wicking of soldering onto the exposed pad. If the MAX9672/MAX9673/ MAX9674 are mounted using the solder mask technique, the via requirement does not apply. In either case, the exposed pad must be connected to both digital and analog grounds through a low thermal resistance path to ensure adequate heat dissipation. Do not route traces under these packages. ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs MAX9672/MAX9673/MAX9674 REF 18V AVDD MTP MEMORY I2C 10 10 10-BIT DAC GMA1 10 10 10-BIT DAC GMA2 10 10 10-BIT DAC GMA3 10 10 10-BIT DAC GMA4 10 10 10-BIT DAC GMA5 10 10 10-BIT DAC GMA6 10 10 10-BIT DAC GMA7 10 10 10-BIT DAC GMA8 10 10-BIT DAC GMA9 10 10 10-BIT DAC GMA10 10 10 10-BIT DAC GMA11 10 10 10-BIT DAC GMA12 10 10 10-BIT DAC GMA13* 10 10 10-BIT DAC GMA14* 10 10 10-BIT DAC GMA15** 10 10 10-BIT DAC GMA16** 10 10 10-BIT DAC 10 DAC REGISTERS REGISTERS SOURCE DRIVER LCD PANEL 18V AVDD_AMP VCOM DVDD SDA SCL A0 GND MAX9672 MAX9673 MAX9674 I2C INTERFACE *NOT AVAILABLE FOR THE MAX9672. **NOT AVAILABLE FOR THE MAX9672/MAX9673. VCOM_FB AGND_AMP GND Figure 14. Typical Application Circuit with Additional Pullup and Pulldown Resistors on GMA1 and GMA16, Respectively ______________________________________________________________________________________ 19 MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs VCOM VCOM_FB Figure 15. VCOM Operational Amplifier with Feedback Resistors VAVDD = 16.0V VDVDD = 3.3V AVDD REF 5V/div 5V/div GMA1 REF GMA6 GMA6 GMA12 DVDD 0V 0V 4ms/div 4ms/div Figure 16. Recommended Power-Up Sequence Figure 17. REF Powered Up After AVDD and DVDD Chip Information PROCESS: BiCMOS 20 ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs REF 18V AVDD MTP MEMORY I2C 10 10 10-BIT DAC GMA1 10 10 10-BIT DAC GMA2 10 10 10-BIT DAC GMA3 10 10 10-BIT DAC GMA4 10 10 10-BIT DAC GMA5 10 10 10-BIT DAC GMA6 10 10 10-BIT DAC GMA7 10 10 10-BIT DAC GMA8 10 10 10-BIT DAC GMA9 10 10 10-BIT DAC GMA10 10 10 10-BIT DAC GMA11 10 10 10-BIT DAC GMA12 10 10 10-BIT DAC GMA13* 10 10 10-BIT DAC GMA14* 10 10 10-BIT DAC GMA15** 10 10 10-BIT DAC GMA16** 10 10 10-BIT DAC 18V DAC REGISTERS REGISTERS SOURCE DRIVER LCD PANEL AVDD_AMP VCOM DVDD SDA SCL A0 GND MAX9672 MAX9673 MAX9674 I2C INTERFACE VCOM_FB AGND_AMP GND *NOT AVAILABLE FOR THE MAX9672. **NOT AVAILABLE FOR THE MAX9672/MAX9673. ______________________________________________________________________________________ 21 MAX9672/MAX9673/MAX9674 Typical Operating Circuit Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 TQFN-EP T2855+8 21-0140 90-0028 QFN THIN.EPS MAX9672/MAX9673/MAX9674 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs 22 ______________________________________________________________________________________ 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ______________________________________________________________________________________ 23 MAX9672/MAX9673/MAX9674 Package Information (continued) MAX9669 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 9/09 Initial release -- 1 10/09 MTP factory initialization values changed per customer request in Table 3 12 2 11/09 Updated write operations and soldering temperature (reflow) 3 3/10 Added lead temperature and made various corrections 4 2/11 Changed MTP factory initialization value of MAX9673 for GMA5 1, 2, 8, 16 2, 3, 4, 6, 8, 11, 14, 19, 21 12 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX9672ETI+T MAX9673ETI+ MAX9673ETI+T MAX9674ETI+ MAX9674ETI+T