MAX1778EUG+ - Maxim Integrated Products, Inc.

General Description

The MAX1778/MAX1880–MAX1885 multiple-output

DC-DC converters provide the regulated voltages

required by active matrix thin-film transistor (TFT) liquid

crystal displays (LCD) in a low-profile TSSOP package.

One high-power step-up converter and two low-power

charge pumps convert the 2.7V to 5.5V input voltage

into three independent output voltages. A built-in linear

regulator and VCOM buffer complete the power-supply

requirements.

The main step-up converter accurately generates an

externally set output voltage up to 13V that can supply

the display’s row/column drivers. The converter’s high

switching frequency and current-mode PWM architec-

ture provide fast transient response and allow the use

of small low-profile inductors and ceramic capacitors.

The low-power BiCMOS control circuitry and internal

14V switch (0.35ΩN-channel MOSFET) enable efficien-

cies up to 91%.

The dual low-power charge pumps (MAX1778/

MAX1880/MAX1881/MAX1882 only) independently reg-

ulate one positive output (VPOS) and one negative out-

put (VNEG). These low-power outputs use external

diode and capacitor stages (as many stages as

required) to regulate output voltages up to +40V and

-40V. A unique control scheme minimizes output ripple

as well as capacitor sizes for both charge pumps.

A resistor-programmable, 40mA, low-dropout linear

regulator (MAX1778/MAX1881/MAX1883/MAX1884

only) provides preregulation or postregulation for any of

the supplies. For higher current applications, an exter-

nal transistor can be added. Additionally, the VCOM

buffer provides a high current output that is ideal for

driving the capacitive backplane of TFT LCD panels.

The VCOM buffer’s output voltage is preset with an

internal 50% resistive-divider or can be externally

adjusted for other voltages.

The MAX1778/MAX1880–MAX1885 are protected

against output undervoltage and thermal overload con-

ditions by a latched fault detection circuit that shuts

down the device. All devices are available in the ultra-

thin TSSOP package (1.1mm max height).

Applications

TFT LCD Notebook Displays

TFT LCD Desktop Monitor Panels

Features

♦500kHz/1MHz Current-Mode PWM Step-Up

Regulator

Up to +13V Main High-Power Output

±1% Accurate

High Efficiency (91%)

♦Dual Regulated Charge-Pump Outputs

(MAX1778/MAX1880/MAX1881/MAX1882 only)

Up to +40V Positive Charge-Pump Output

Up to -40V Negative Charge-Pump Output

♦Low-Dropout 40mA Linear Regulator

(MAX1778/MAX1881/MAX1883/MAX1884 only)

Up to +15V LDO Input

♦Optional Higher Current with External Transistor

♦2.7V to 5.5V Input Supply

♦Internal Supply Sequencing and Soft-Start

♦Power-Ready Output

♦Adjustable Fault-Detection Latch

♦Thermal Protection (+160°C)

♦0.1µA Shutdown Current

♦0.7mA IN Quiescent Current

♦Ultra-Small External Components

♦Thin TSSOP Package (1.1mm max height)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

________________________________________________________________ Maxim Integrated Products 1

19-1979; Rev 1; 9/05

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX1778EUG -40°C to +85°C 24 TSSOP

MAX1778EUG+ -40°C to +85°C 24 TSSOP

MAX1880EUG -40°C to +85°C 24 TSSOP

MAX1881EUG -40°C to +85°C 24 TSSOP

MAX1882EUG -40°C to +85°C 24 TSSOP

MAX1883EUP -40°C to +85°C 20 TSSOP

MAX1884EUP -40°C to +85°C 20 TSSOP

MAX1885EUP -40°C to +85°C 20 TSSOP

Typical Operating Circuit appears at end of data sheet.

Pin Configurations and Selector Guide appear at end of

data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

+ Denotes lead-free package.

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

IN, SHDN, TGND, FLTSET to GND...........................-0.3V to +6V

DRVN to GND .........................................-0.3V to (VSUPN + 0.3V)

DRVP to GND..........................................-0.3V to (VSUPP + 0.3V)

PGND to GND.....................................................................±0.3V

RDY, SUPB to GND ................................................-0.3V to +14V

LX, SUPP, SUPN to PGND .....................................-0.3V to +14V

SUPL to GND..........................................................-0.3V to +18V

LDOOUT to GND ....................................-0.3V to (VSUPL + 0.3V)

INTG, REF, FB, FBN, FBP to GND...............-0.3V to (VIN + 0.3V)

FBL to GND .............-0.3V to the lower of (VSUPL+ 0.3V) or +6V

BUFOUT, BUF+, BUF- to GND ...............-0.3V to (VSUPB + 0.3V)

Continuous Power Dissipation (TA= +70°C)

20-Pin TSSOP (derate 10.9mW/°C above +70°C) ......879mW

24-Pin TSSOP (derate 12.2mW/°C above +70°C) ......975mW

Operating Temperature Range

MAX1778EUG, MAX1883EUP ........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply Range VIN 2.7 5.5 V

Input Undervoltage Threshold

VUVLO

VIN rising, 40mV hysteresis (typ) 2.2 2.4 2.6 V

MAX1778/MAX1880/

MAX1883 (fOSC = 1MHz) 0.7 1

IN Quiescent Supply Current IIN

VFB = VFBP

= 1.5V, VFBN

= -0.2V

MAX1881/MAX1882/

MAX1884/MAX1885

(fOSC = 500kHz)

0.6 1

MAX1778/MAX1880

(fOSC = 1MHz) 0.4 0.7

SUPP Quiescent Current ISUPP VFBP = 1.5V

MAX1881/MAX1882

(fOSC = 500kHz) 0.3 0.5

MAX1778/MAX1880

(fOSC = 1MHz) 0.4 0.7

SUPN Quiescent Current ISUPN

VFBN = -0.2V

MAX1881/MAX1882

(fOSC = 500kHz) 0.3 0.5

IN Shutdown Current VSHDN = 0, VIN = 5V 0.1 10 µA

SUPP Shutdown Current VSHDN = 0, VSUPP = 13V,

MAX1778/MAX1880/MAX1881/MAX1882 0.1 10 µA

SUPN Shutdown Current VSHDN = 0, VSUPN = 13V,

MAX1778/MAX1880/MAX1881/MAX1882 0.1 10 µA

SUPL Shutdown Current VSHDN = 0, VSUPL = 13V

MAX1778/MAX1881/MAX1883/MAX1884 0.1 10 µA

SUPB Shutdown Current VSHDN = 0, VSUPB = 13V 6 13 µA

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

MAIN STEP-UP CONVERTER

Main Output Voltage Range VMAIN VIN 13 V

Integrator enabled, CINTG = 1000pF

1.234 1.247 1.260

FB Regulation Voltage VFB Integrator disabled (INTG = REF)

1.220 1.280

FB Input Bias Current IFB VFB = 1.25V, INTG = GND -50

+50

MAX1778/MAX1880/MAX1883

0.85

1.15 MHz

Operating Frequency fOSC MAX1881/MAX1882/MAX1884/MAX1885

425 500

575

kHz

Oscillator Maximum Duty

Cycle 80 85 91 %

Integrator enabled,

CINTG = 1000pF

0.01

Load Regulation ILX = 0 to 200mA,

VMAIN = 10V Integrator disabled

(INTG = REF) 0.2

Line Regulation 0.1

%/V

Integrator Transconductance

317

µs

LX Switch On-Resistance

RLX

(

)

ILX = 100mA

0.35

0.7 Ω

LX Leakage Current ILX VLX = 13V

0.01

20 µA

Phase I = soft-start (1024/fOSC)

0.275 0.38

0.5

Phase II = soft-start (1024/fOSC)

0.75

Phase III = soft-start (1024/fOSC)

1.12

LX Current Limit ILIM

Phase IV = fully-on (after 3072/fOSC)

1.15

1.5

1.85

Maximum RMS LX Current 1A

Soft-Start Period tSS Power-up to the end of Phase III 3072 / fOSC s

Falling edge, FLTSET = GND

1.07

1.1

1.14

FB Fault Trip Level Falling edge, FLTSET = 1V

0.955 0.99 1.025

POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)

SUPP Input Supply Range VSUPP 2.7 13 V

Operating Frequency fCHP 0.5 x fOSC Hz

FBP Regulation Voltage VFBP 1.2

1.25

1.3 V

FBP Input Bias Current IFBP VFBP = 1.5V -50

+50

DRVP PCH On-Resistance

RPCH

(

)

510Ω

VFBP = 1.2V 2 4 Ω

DRVP NCH On-Resistance

RNCH

(

)

VFBP = 1.3V 20 kΩ

Maximum RMS DRVP Current 0.1 A

FBP Power-Ready Trip Level Rising edge

1.09 1.125 1.16

Falling edge, FLTSET = GND

1.08 1.11 1.16

FBP Fault Trip Level Falling edge, FLTSET = 1V

0.955 0.99 1.025

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)

SUPN Input Supply Range

VSUPN

2.7 13 V

Operating Frequency fCHP 0.5 x fOSC Hz

FBN Regulation Voltage VFBN

-50

+50

FBN Input Bias Current IFBN VFBN = 0 -50

+50

DRVN PCH On-Resistance

RPCH

(

)

510Ω

VFBN = +50mV 24Ω

DRVN NCH On-Resistance

RNCH

(

)

VFBN = -50mV 20 kΩ

Maximum RMS DRVN Current 0.1 A

FBN Power-Ready Trip Level Falling edge 80

125

165 mV

FBN Fault Trip Level Rising edge 80

140

190 mV

LOW-DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only)

SUPL Input Supply Range VSUPL 4.5 15 V

SUPL Undervoltage Lockout Rising edge, 50mV hysteresis (typ) 3.8 4 4.3 V

SUPL Quiescent Current ISUPL ILDO = 100µA

120

220 µA

ILDO = 40mA

130

300

Dropout Voltage (Note 1)

VDROP

LDO is set to

regulate at 9V ILDO = 5mA 70 mV

FBL Regulation Voltage VFBL VSUPL = 10V, LDO regulating at 9V,

ILDO = 15mA

1.235 1.25 1.265

LDO Load Regulation VSUPL = 10V, LDO regulating at 9V,

ILDO = 100µA to 40mA 1.2 %

LDO Line Regulation VSUPL = 4.5V to 15V, FBL = LDOOUT,

ILDO = 15mA

0.02

%/V

FBL Input Bias Current IFBL VFBL = 1.25V

-0.8 +0.8

µA

LDO Current Limit

ILDOLIM

VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V 40

130

220 mA

VCOM BUFFER

SUPB Input Supply Range

VSUPB

4.5 13 V

SUPB Quiescent Current ISUPB VSUPB = 13V

420

850 µA

BUFOUT Leakage Current -10

+10

µA

Power-Supply Rejection Ratio PSRR VSUPB = 4.5V to 13V, VCM = 2.25V 85 98 dB

Input Common-Mode Voltage

Range VCM |VOS| < 10mV 1.2 8.8 V

Common-Mode Rejection Ratio

CMRR

VCM = 1.2V to 8.8V 75 dB

Input Bias Current IBIAS VCM = 5V

-100

-10

+100

Input Offset Current IOS VCM = 5V

-100 +100

Gain Bandwidth Product GBW CBUF = 1µF 13

kHz

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

IBUFOUT = 0

4.99 5.01

IBUFOUT = ±5mA

4.97 5.03

Output Voltage

VBUFOUT

BUF+ = GND

IBUFOUT = ±45mA

4.93 5.07

IBUFOUT = ±5mA -30 30

Input Offset Voltage VOS

VSUPB = 4.5V to 13V,

VCM = 1.2V to

(VSUPB –1.2V) IBUFOUT = ±45mA -70 70

Output Voltage Swing High VOH IBUFOUT = -45mA, ΔVOS = 1V 9 9.6 V

Output Voltage Swing Low VOL IBUFOUT = +45mA, ΔVOS = 1V 0.4 1 V

Peak Buffer Output Current

±150

BUF+ Dual Mode™ Threshold

Voltage Falling edge, 20mV hysteresis (typ) 80

125

170 mV

REFERENCE

Reference Voltage VREF -2μA < IREF < 50µA

1.231 1.25 1.269

Reference Undervoltage

Threshold 0.9

1.05

1.2 V

LOGIC SIGNALS

SHDN Input Low Voltage 0.9 V

SHDN Input High Voltage 2.1 V

SHDN Input Current ISHDN

0.01

1µA

FLTSET Input Voltage Range 0.67 x

VREF

0.85 x

VREF

FLTSET Threshold Voltage Rising edge, 25mV hysteresis (typ) 80

125

170 mV

FLTSET Input Current VFLTSET = 1V 0.1 50 nA

RDY Output Low Voltage ISINK = 2mA

0.25

0.5 V

RDY Output High Leakage V RDY = 13V

0.01

1µA

Thermal Shutdown Rising temperature

160

°C

Dual Mode is a registered trademark of Maxim Integrated Products, Inc.

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS MIN

MAX

UNITS

Input Supply Range VIN 2.7 5.5 V

Input Undervoltage

Threshold VUVLO VIN Rising, 40mV hysteresis (typ) 2.2 2.6 V

MAX1778/MAX1880/

MAX1883 (fOSC = 1MHz) 1

IN Quiescent Supply

Current IIN

VFB =

VFBP = 1.5V,

VFBN = -0.2V MAX1881/MAX1882/MAX1884/

MAX1885 (fOSC = 500kHz) 1

MAX1778/MAX1880

(fOSC = 1MHz) 0.7

SUPP Quiescent Current ISUPP VFBP = 1.5V

MAX1881/MAX1882

(fOSC = 500kHz) 0.5

MAX1778/MAX1880

(fOSC = 1MHz) 0.7

SUPN Quiescent Current ISUPN VFBN = -0.2V

MAX1881/MAX1882

(fOSC = 500kHz) 0.5

IN Shutdown Current VSHDN = 0, VIN = 5V 10 µA

SUPP Shutdown Current VSHDN = 0, VSUPP = 13V,

MAX1778/MAX1880/MAX1881/MAX1882 10 µA

SUPN Shutdown Current VSHDN = 0, VSUPN = 13V,

MAX1778/MAX1880/MAX1881/MAX1882 10 µA

SUPL Shutdown Current VSHDN = 0, VSUPL = 13V,

MAX1778/MAX1881/MAX1883/MAX1884 10 µA

SUPB Shutdown Current VSHDN = 0, VSUPB = 13V 13 µA

MAIN STEP-UP CONVERTER

Main Output Voltage Range

VMAIN VIN 13 V

Integrator enabled, CINTG = 1000pF

1.223 1.269

FB Regulation Voltage VFB Integrator disabled (INTG = REF)

1.21 1.29

FB Input Bias Current IFB VFB = 1.25V, INTG = GND -50

+50

MAX1778/MAX1880/MAX1883

0.75 1.25

MHz

Operating Frequency FOSC MAX1881/MAX1882/MAX1884/MAX1885

375

625

kHz

Oscillator Maximum Duty

Cycle 79 91 %

LX Switch On-Resistance

RLX

(

)

ILX = 100mA 0.7 Ω

LX Leakage Current ILX VLX = 13V 20 µA

Phase I = soft-start (1024/fOSC)

0.275 0.525

LX Current Limit ILIM Phase IV = fully on (after 3072/fOSC) 1.1

2.05

FB Fault Trip Level Falling edge, FLTSET = GND

1.07 1.14

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)

SUPP Input Supply Range VSUPP 2.7 13 V

FBP Regulation Voltage VFBP 1.2 1.3 V

FBP Input Bias Current IFBP VFBP = 1.5V -50

+50

DRVP PCH On-Resistance

RPCH

(

)

10 Ω

VFBP = 1.2V 4 Ω

DRVP NCH On-Resistance

RNCH

(

)

VFBP = 1.3V 20 kΩ

FBP Power-Ready Trip Level

Rising edge

1.09 1.16

NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)

SUPN Input Supply Range VSUPN 2.7 13 V

FBN Regulation Voltage VFBN

-50 +50

FBN Input Bias Current IFBN VFBN = 0 -50

+50

DRVN PCH On-Resistance

RPCH

(

)

10 Ω

VFBN = +50mV 4 Ω

DRVN NCH On-Resistance

RNCH

(

)

VFBN = -50mV 20 kΩ

FBN Power-Ready Trip Level

Falling edge 80 165 mV

LOW DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only)

SUPL Input Supply Range VSUPL 4.5 15 V

SUPL Undervoltage Lockout

Rising edge, 50mV hysteresis (typ) 3.8 4.3 V

SUPL Quiescent Current ISUPL ILDO = 100µA 240 µA

Dropout Voltage (Note 1) VDROP LDO regulating to 9V, ILDO = 40mA 330 mV

FBL Regulation Voltage VFBL VSUPL = 10V, LDO regulating to 9V,

ILDO = 15mA

1.222 1.265

LDO Load Regulation VSUPL = 10V, LDO regulating to 9V,

ILDO = 100µA to 40mA 1.2 %

LDO Line Regulation VSUPL = 4.5V to 15V, FBL = LDOOUT,

ILDO = 15mA

0.02 %/V

FBL Input Bias Current IFBL VFBL = 1.25V

-1.2 +1.2

µA

LDO Current Limit

ILDOLIM

VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V 40 260 mA

VCOM BUFFER

SUPB Input Supply Range VSUPB 4.5 13 V

SUPB Quiescent Current ISUPB VSUPB = 13V 850 µA

BUFOUT Leakage Current -10

+10

µA

Input Common-Mode Voltage VCM |VOS| < 10mV 1.2 8.8 V

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =

PGND = GND, CREF = 0.22µF, CBUF = 1µF, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN MAX

UNITS

Input Bias Current IBIAS VCM = 5V

-500 +500

Input Offset Current IOS VCM = 5V

-500 +500

IBUFOUT = 0

4.988 5.012

IBUFOUT = ±5mA

4.97 5.03

Output Voltage

VBUFOUT

BUF+ = GND

IBUFOUT = ±45mA

4.93 5.07

IBUFOUT = ±5mA -30 30

Input Offset Voltage VOS

VSUPB = 4.5V to 13V

VCM = 1.2V to

(VSUPB - 1.2V) IBUFOUT = ±45mA -70 70

Output Voltage Swing High VOH IBUFOUT = -45mA, ΔVOS = 1V 9 V

Output Voltage Swing Low VOL IBUFOUT = +45mA, ΔVOS = 1V 1 V

BUF+ Dual Mode

Threshold Voltage Falling edge, 20mV hysteresis (typ) 80 170 mV

REFERENCE

Reference Voltage VREF -2µA < IREF < 50µA

1.223 1.269

Reference Undervoltage

Threshold 0.9 1.2 V

LOGIC SIGNALS

SHDN Input Low Voltage 0.9 V

SHDN Input High Voltage 2.1 V

SHDN Input Current I SHDN 1µA

FLTSET Input Voltage Range

0.74 x VREF 0.85 x VREF

FLTSET Threshold Voltage Rising edge, 25mV hysteresis (typ) 80 170 mV

FLTSET Input Current VFLTSET = 1V 50 nA

RDY Output Low Voltage ISINK = 2mA 0.5 V

RDY Output High Leakage V RDY = 13V 1 µA

Note 1: Dropout Voltage is defined as the VSUPL - VLDOOUT, when VSUPL is 100mV below the set value of VLDOOUT.

Note 2: Specifications to -40°C are guaranteed by design, not production tested.

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

_______________________________________________________________________________________ 9

7.88

7.92

7.96

8.00

8.04

8.08

8.12

0 200 400 600 800

MAIN 8V OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX1778 toc01

IOUT (mA)

VOUT (V)

VIN = 5V

RCOMP = 24kΩ

CCOMP = 470pF

VIN = 3.3V

CINTG = 470pF

100

0 200 400 600 800

MAIN 8V OUTPUT EFFICIENCY

vs. LOAD CURRENT

MAX1778 toc02

IOUT (mA)

EFFICIENCY (%)

VIN = 3.3V

VOUT = 8V

RCOMP = 24kΩ

CCOMP = 470pF

CINTG = 470pF

VIN = 5V

11.76

11.92

11.84

12.08

12.00

12.16

12.24

0 200 300100 400 500 600

MAIN 12V OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX1778 toc03

IOUT (mA)

VOUT (V)

FIGURE 8

CINTG = 470pF

VIN = 3.3V

VIN = 5V

100

0 200 300100 400 500 600

MAIN 12V OUTPUT EFFICIENCY

vs. LOAD CURRENT

MAX1778 toc04

IOUT (mA)

EFFICIENCY (%)

FIGURE 8

VOUT = 12V

CINTG = 470pF

VIN = 3.3V

VIN = 5V

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

2.5 3.53.0 4.0 4.5 5.0 5.5

STEP UP CONVERTERS

SWITCHING FREQUENCY vs. INPUT VOLTAGE

MAX1778 toc05

VIN (V)

SWITCHING FREQUENCY (MHz)

MAX1778

19.2

19.4

19.8

19.6

20.0

20.2

POSITIVE CHARGE-PUMP OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX1778 toc06

IPOS (mA)

VPOS (V)

01051520

VSUPP = 10V

VSUPP = 8V

VSUPP = 7.5V

VSUPP = 7V

100

POSITIVE CHARGE-PUMP EFFICIENCY

vs. LOAD CURRENT

MAX1778 toc07

INEG (mA)

EFFICIENCY (%)

01051520

VPOS = 20V

VSUPP = 7.5V

VSUPP = 7V

VSUPP = 8V

VSUPP = 10V

2684101214

MAXIMUM POSITIVE CHARGE-PUMP

OUTPUT VOLTAGE vs. SUPPLY VOLTAGE

MAX1778 toc08

VSUPP (V)

VPOS (V)

IPOS = 10mA

IPOS = 1mA

-5.04

-5.00

-5.02

-4.96

-4.98

-4.92

-4.94

-4.90

NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX1778 toc09

INEG (mA)

VNEG (V)

0 10203040

VSUPN = 7V

VSUPN = 8V

VSUPN = 6V

Typical Operating Characteristics

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

100

NEGATIVE CHARGE-PUMP EFFICIENCY

vs. LOAD CURRENT

MAX1778 toc10

INEG (mA)

EFFICIENCY (%)

0 10203040

VSUPN = 7V

VSUPN = 8V

VSUPN = 6V

VNEG = -5V

-14

-10

-12

-6

-8

-4

-2

2684 101214

MAXIMUM NEGATIVE CHARGE-PUMP

OUTPUT VOLTAGE vs. SUPPLY VOLTAGE

MAX1778 toc11

VSUPN (V)

VNEG (V)

INEG = 10mA

INEG = 1mA

1.23

1.24

1.25

1.26

1.27

0 20406080100

REFERENCE VOLTAGE

vs. REFERENCE LOAD CURRENT

MAX1778 toc12

IREF (μA)

VREF (V)

STEP-UP CONVERTER LOAD-TRANSIENT

RESPONSE

MAX1778 toc13

200mA

8.1V

8.0V

7.9V

40μs/div

A. IMAIN = 20mA to 200mA, 200mA/div

B. VMAIN = 8V, 100mV/div

C. INDUCTOR CURRENT, 1A/div

CINTG = 1000pF

STEP-UP CONVERTER LOAD-TRANSIENT

RESPONSE WITHOUT INTEGRATOR

MAX1778 toc14

200mA

8.1V

8.0V

7.9V

40μs/div

A. IMAIN = 20mA to 200mA, 200mA/div

B. VMAIN = 8V, 100mV/div

C. INDUCTOR CURRENT, 1A/div

INTG = REF

STEP-UP CONVERTER LOAD-TRANSIENT

RESPONSE (1μs PULSES)

MAX1778 toc15

0.5A

8.0V

7.9V

0.5A

4μs/div

A. IMAIN = 0 to 500mA, 500mA/div

B. VMAIN = 8V, 100mV/div

C. INDUCTOR CURRENT, 500mA/div

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 11

RIPPLE VOLTAGE WAVEFORMS

MAX1778 toc16

-5V

20V

1μs/div

A. VMAIN = 8V, IMAIN = 200mA, 10mV/div

B. VNEG = -5V, INEG = 10mA, 20mV/div

C. VPOS = 20V, IPOS = 5mA, 20mV/div

STEP-UP CONVERTER

SOFT-START (LIGHT LOAD)

MAX1778 toc17

0.5A

1ms/div

A. VSHDN = O TO 2V, 2V/div

B. VMAIN = 8V, 2V/div

C. INDUCTOR CURRENT, 500mA/div

RLOAD = 400Ω

STEP-UP CONVERTER

SOFT-START (HEAVY LOAD)

MAX1778 toc18

1.0A

1ms/div

A. VSHDN = O TO 2V, 2V/div

B. VMAIN = 8V, 2V/div

C. INDUCTOR CURRENT, 500mA/div

RLOAD = 20Ω

0.5A

POWER-UP SEQUENCE

MAX1778 toc19

10V

2ms/div

A. VSHDN = O TO 2V, 2V/div

B. RDY, 5V/div

C. POSITIVE CHARGE PUMP = VPOS = 20V, RLOAD = 4kΩ, 10V/div

D. STEP-UP CONVERTER: VMAIN = 8V, RLOAD = 40Ω, 10V/div

E. NEGATIVE CHARGE PUMP: VNEG = -5V, RLOAD = 500Ω, 10V/div

20V

-10V

POWER-UP SEQUENCE

(CIRCUIT OF FIGURE 10)

MAX1778 toc20

10V

1ms/div

A. RDY, 2V/div

B. POSITIVE CHARGE PUMP, VPOS(SYS) = 20V, 10V/div

C. STEP-UP CONVERTER: VMAIN(SYS) = 8V, 10V/div

D. NEGATIVE CHARGE PUMP, VNEG = -5V, -5V/div

20V

-5V

MAX1778 toc21

10V

100μs/div

POWER-UP INTO SHORT-CIRCUIT

(CIRCUIT OF FIGURE 10)

A. RDY, 2V/div

B. GATE OF N-CH MOSFET, 5V/div

C. STEP-UP CONVERTER, VMAIN(START) = 8V, 5V/div

VMAIN(SYS) = GND

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

12 ______________________________________________________________________________________

4.75

4.80

4.85

4.90

4.95

5.00

5.05

MAX1778 toc22

VSUPL (V)

VLDOOUT (V)

LDO OUTPUT VOLTAGE

vs. LDO INPUT VOLTAGE

(INTERNAL LINEAR REGULATOR)

4861012

ILDOOUT = 0

ILDOOUT = 40mA

5.04

5.02

4.90

0.01 0.1 10 100

4.92

4.96

4.94

5.00

4.98

MAX1778 toc23

ILDOOUT (mA)

VLDOOUT (V)

LDO OUTPUT VOLTAGE

vs. LDO OUTPUT CURRENT

(INTERNAL LINEAR REGULATOR)

4.90

4.96

4.94

4.92

4.98

5.00

5.02

5.04

5.06

5.08

5.10

-40 10-15 35 60 85

LDO OUTPUT VOLTAGE vs. TEMPERATURE

(INTERNAL LINEAR REGULATOR)

MAX1778 toc24

TEMPERATURE (°C)

VLDO (V)

ILDOOUT = 0

ILDOOUT = 40mA

120

160

200

MAX1778 toc25

ILDOOUT (mA)

VSUPL - VLDOOUT (mV)

02010 30 40

DROPOUT VOLTAGE

vs. LDO LOAD CURRENT

(INTERNAL LINEAR REGULATOR)

VLDOOUT = 5V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0 10203040

MAX1778 toc26

ILDOOUT (mA)

ISUPL - ILDOOUT (mA)

LDO SUPPLY CURRENT

vs. LDO OUTPUT CURRENT

(INTERNAL LINEAR REGULATOR)

VLDOOUT = 5V

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 13

1 100010010

100

MAX1778 toc27

FREQUENCY (kHz)

PSRR (dB)

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY

CLDOOUT = 4.7μF

ILDOOUT = 40mA

040

REGION OF STABLE CLDOOUT ESR

vs. LOAD CURRENT

MAX1778 toc28

ILDOOUT (mA)

CLDOOUT ESR (Ω)

10 20 30

100

0.01

0.1

CLDOOUT = 1μF

STABLE REGION

MAX1778 toc29

4.96V

4OmA

5.00V

100μs/div

LOAD-TRANSIENT RESPONSE

(INTERNAL LINEAR REGULATOR)

A. ILDO = 100μA TO 40mA, 40mA/div

B. VLDO = 5V, 20mV/div

VSUPL = VLDO + 500mV

MAX1778 toc30

4.94V

4OmA

5.00V

100μs/div

LOAD-TRANSIENT RESPONSE NEAR

DROPOUT (INTERNAL LINEAR REGULATOR)

A. ILDO = 100μA TO 40mA, 40mA/div

B. VLDO = 5V, 20mV/div

VIN = VLDO + 100mV

MAX1778 toc31

0.5A

5.0V

8.0V

1.0A

10μs/div

INTERNAL LINEAR-REGULATOR

RIPPLE REJECTION

A. VLDOOUT = 5V, ILDOOUT = 40mA, 10mV/div

B. VMAIN = VSUPL = 8V, 200mV/div

C. IMAIN = 0 TO 750mA, 500mA/div

MAX1778 toc32

400μs/div

INTERNAL LINEAR-REGULATOR

STARTUP

A. V

HDN = 0 TO 2V, 2V/div

B. VLDOOUT = 5V, RLDOOUT = 125Ω, 2V/div

C. VMAIN = 8V, RMAIN = 40Ω, 2V/div

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

14 ______________________________________________________________________________________

2.45

2.47

2.49

2.51

2.53

2.55

2.5 3.53.0 4.0 4.5 5.0 5.5

MAX1778 toc33

VIN (V)

VLDO (V)

LINEAR-REGULATOR OUTPUT VOLTAGE

vs. INPUT VOLTAGE

(EXTERNAL LINEAR REGULATOR)

ILDO = 0

ILDO = 750mA

FIGURE 7

2.55

2.45

0.1 1 10 100 1000

2.47

MAX1778 toc34

ILDO (mA)

VLDO (V)

2.49

2.51

2.53

LINEAR-REGULATOR OUTPUT VOLTAGE

vs. LOAD CURRENT

(EXTERNAL LINEAR REGULATOR)

FIGURE 7

MAX1778 toc35

2.45V

250mA

2.55V

50mA

2.50V

100μs/div

EXTERNAL LINEAR-REGULATOR

LOAD-TRANSIENT RESPONSE

A. ILDO = 50mA TO 250mA, 200mA/div

B. VLDO = 2.5V, 50mV/div

FIGURE 7

MAX1778 toc36

0.5A

2.5V

7.8V

8.0V

10μs/div

EXTERNAL LINEAR-REGULATOR

RIPPLE REJECTION

A. VLDO = 2.5V, ILDO = 200mA, 10mV/div

B. VMAIN = VSUPL = 8V, 200mV/div

C. IMAIN = 0 TO 750mA, 500mA/div

FIGURE 7

-2.5

-1.5

-0.5

1.5

0.5

2.5

02468101214

MAX1778 toc37

VCM (V)

ΔVOS (mV)

INPUT OFFSET VOLTAGE DEVIATION

vs. COMMON-MODE VOLTAGE

VSUPB = 4.5V VSUPB = 13V

-1.0

-0.6

-0.2

0.2

0.6

1.0

486101214

MAX1778 toc38

VSUPB (V)

ΔVOS (mV)

INPUT OFFSET VOLTAGE DEVIATION

vs. BUFFER SUPPLY VOLTAGE

VCM = VSUPB / 2

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 15

-0.6

-0.2

0.2

0.6

1.0

-40 10-15 356085

MAX1778 toc39

TEMPERATURE (°C)

ΔVOS (mV)

INPUT OFFSET VOLTAGE DEVIATION

vs. TEMPERATURE

VSUPB = 13V

VCM = VSUPB / 2

-0.6

-0.2

0.2

0.6

1.0

-40 10-15 356085

MAX1778 toc39

TEMPERATURE (°C)

ΔVOS (mV)

INPUT OFFSET VOLTAGE DEVIATION

vs. TEMPERATURE

VSUPB = 13V

VCM = VSUPB / 2

042 6 8 101214

MAX1778 toc41

VCM (V)

IBIAS (nA)

BUFFER INPUT BIAS CURRENT

vs. COMMON-MODE VOLTAGE

VSUPB = 4.5V

VSUPB = 13V

486 101214

MAX1778 toc42

VSUPB (V)

IBIAS (nA)

BUFFER INPUT BIAS CURRENT

vs. BUFFER SUPPLY VOLTAGE

VCM = VSUPB / 2

-40 -15 10 35 60 85

MAX1778 toc43

TEMPERATURE (°C)

IBIAS (nA)

BUFFER INPUT BIAS CURRENT

vs. TEMPERATURE

VCM = VSUPB / 2

0.30

0.34

0.42

0.38

0.46

0.50

042 6 8 101214

MAX1778 toc44

VCM (V)

ISUPB (mA)

BUFFER SUPPLY CURRENT

vs. COMMON-MODE VOLTAGE

VSUPB = 4.5V

VSUPB = 13V

0.30

0.34

0.38

0.42

0.46

0.50

486 101214

MAX1778 toc45

VSUPB (V)

ISUPB (mA)

BUFFER SUPPLY CURRENT

vs. BUFFER SUPPLY VOLTAGE

VCM = VSUPB / 2

0.3

0.2

0.1

0.4

0.5

0.6

0.7

0.8

0.9

1.0

-40 10-15 35 60 85

ISUPB (mA)

MAX1778 toc46

TEMPERATURE (°C)

NO-LOAD BUFFER SUPPLY CURRENT

vs. TEMPERATURE

VSUPB = 13V

VCM = VSUPB / 2

MAX1778 toc47

4.00V

3.95V

4.05V

4.00V

3.95V

4.05V

4μs/div

VCOM BUFFER

SMALL-SIGNAL RESPONSE

A. VBUF+ = 3.95V TO 4.05V, 50mV/div

B. BUFOUT = BUF-, 50mV/div

CBUF = 1μF, VSUPB = 8V

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

16 ______________________________________________________________________________________

MAX1778 toc48

4.00V

3.50V

4.50V

4.00V

3.50V

4.50V

10μs/div

VCOM BUFFER

LARGE-SIGNAL RESPONSE

A. VBUF+ = 3.50V TO 4.50V, 0.5V/div

B. BUFOUT = BUF-, 0.5V/div

CBUF = 1μF, VSUPB = 8V

MAX1778 toc49

3.8V

8.0V

200mA

4.2V

-200mA

4.0V

4μs/div

VCOM BUFFER

LOAD-TRANSIENT RESPONSE

A. IBUFOUT = 200mA PULSES, 200mA/div

B. BUFOUT = BUF-, 200mV/div

C. VMAIN = 8V, 50mV/div

VSUPB = VMAIN, BUF+ = GND, CBUF = 1μF

MAX1778 toc50

3.5V

8.0V

500mA

4.5V

-500mA

4.0V

4μs/div

VCOM BUFFER

LOAD-TRANSIENT RESPONSE

A. IBUFOUT = 400mA PULSES, 500mA/div

B. BUFOUT = BUF-, 0.5V/div

C. VMAIN = 8V, 100mV/div

VSUPB = VMAIN, BUF+ = GND, CBUF = 1μF

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT,

BUF+ = FLTSET = TGND = PGND = GND, TA= +25°C.)

MAX1778 toc51

8.1V

7.8V

100μs/div

VCOM BUFFER STARTUP

A. RDY, 2V/div

B. BUFOUT = BUF-, CBUF = 1μF, 2V/div

C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div

BUF+ = GND

MAX1778 toc51

8.1V

7.8V

100μs/div

VCOM BUFFER STARTUP

A. RDY, 2V/div

B. BUFOUT = BUF-, CBUF = 1μF, 2V/div

C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div

BUF+ = GND

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 17

Pin Description

MAX1778

MAX1881

MAX1880

MAX1882

MAX1883

MAX1884 MAX1885

NAME FUNCTION

1111FB

Main Step-Up Regulator Feedback Input. Regulates to 1.25V

nominal. Connect a resistive divider from the output (VMAIN) to FB

to analog ground (GND).

2222INTG

Main Step-Up Integrator Output. When using the integrator,

connect 1000pF to analog ground (GND). To disable the

integrator, connect INTG to REF.

3333IN

Main Supply Voltage. The supply voltage powers the control

circuitry for all of the regulators and may range from 2.7V to 5.5V.

Bypass with a 0.1µF capacitor between IN and GND, as close to

the pins as possible.

4444BUF+

VCOM Buffer (Operational Transconductance Amplifier) Positive

Feedback Input. Connect to GND to select the internal resistive

divider that sets the positive input to half the amplifier’s supply

voltage (VBUF+ = V SUPB /2).

5555BUF- VCOM Buffer (Operational Transconductance Amplifier) Negative

Feedback Input

6666SUPB VCOM Buffer (Operational Transconductance Amplifier) Supply

Voltage

7777

BUFOUT

VCOM Buffer (Operational Transconductance Amplifier) Output

8888GND

Analog Ground. Connect to power ground (PGND) underneath the

IC.

9999REF

Internal Reference Bypass Terminal. Connect a 0.22µF ceramic

capacitor from REF to analog ground (GND). External load

capability up to 50µA.

10 10 −−FBP

Positive Charge-Pump Regulator Feedback Input. Regulates to

1.25V nominal. Connect a resistive divider from the positive

charge-pump output (VPOS) to FBP to analog ground (GND).

11 11 −−FBN

Negative Charge-Pump Regulator Feedback Input. Regulates to

0V nominal. Connect a resistive divider from the negative charge-

pump output (VNEG) to FBN to the reference (REF).

12 12 10 10 SHDN

Active-Low Shutdown Control Input. Pull SHDN low to force the

controller into shutdown. If unused, connect SHDN to IN for normal

operation. A rising edge on SHDN clears the fault latch.

13 −11 −SUPL

Low-Dropout Linear Regulator Input Voltage. Can range from 4.5V

to 15V. Bypass with a 1µF capacitor to GND (see Capacitor

Selection and Regulator Stability). Connect both input pins

together externally.

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

18 ______________________________________________________________________________________

Pin Description (continued)

MAX1778

MAX1881

MAX1880

MAX1882

MAX1883

MAX1884 MAX1885

NAME FUNCTION

14 −12 −

LDOOUT

Linear Regulator Output. Sources up to 40mA. Bypass to GND with

a ceramic capacitor determined by:

15 −13 −FBL Voltage Setting Input. Connect a resistive divider from the linear

regulator output (VLDOOUT) to FBL to analog ground (GND).

16 16 14 14 FLTSET

Fault Trip-Level Set Input. Connect to a resistive divider between

REF and GND to set the main step-up converter’s and positive

charge pump’s fault thresholds between 0.67 x VREF and 0.85 x

VREF. Connect to GND for the preset fault threshold (0.9 x VREF).

17 17 −−SUPN Negative Charge-Pump Driver Supply Voltage. Bypass to power

ground (PGND) with a 0.1µF capacitor.

18 18 −−DRVN Negative Charge-Pump Driver Output. Output high level is VSUPN

and low level is PGND.

19 19 −−SUPP Positive Charge-Pump Driver Supply Voltage. Bypass to power

ground (PGND) with a 0.1µF capacitor.

20 20 −−DRVP Positive Charge-Pump Driver Output. Output high level is VSUPP

and low level is PGND

21 21 17 17 PGND Power Ground. Connect to analog ground (GND) underneath the

IC.

22 22 18 18 LX Main Step-Up Regulator Power MOSFET N-Channel Drain. Place

output diode and output capacitor as close to PGND as possible.

23 23 19 19 TGND Must be connected to ground.

24 24 20 20 RDY Active-Low, Open-Drain Output. Indicates all outputs are ready.

On-resistance is 125Ω (typ).

−

13, 14, 15

15, 16 11, 12, 13,

15, 16 N.C. No Connection. Not internally connected.

CmsX

LDOOUT LDOOUT MAX

LDOOUT

. ()

≥⎛

⎝

⎜

⎞

⎠

⎟

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 19

Detailed Description

The MAX1778/MAX1880–MAX1885 are highly efficient

multiple-output power supplies for thin-film transistor

(TFT) liquid crystal display (LCD) applications. The

devices contain one high-power step-up converter, two

low-power charge pumps, an operational transconduc-

tance amplifier (VCOM buffer), and a low-dropout linear

regulator. The primary step-up converter uses an inter-

nal N-channel MOSFET to provide maximum efficiency

and to minimize the number of external components.

The output voltage of the main step-up converter

(VMAIN) can be set from VIN to 13V with external resis-

tors.

The dual charge pumps (MAX1778/MAX1880/

MAX1881/MAX1882 only) independently regulate a

positive output (VPOS) and a negative output (VNEG).

These low-power outputs use external diode and

capacitor stages (as many stages as required) to regu-

late output voltages from -40V to +40V. A unique

control scheme minimizes output ripple as well as

capacitor sizes for both charge pumps.

A resistor-programmable 40mA linear regulator

(MAX1778/MAX1881/MAX1883/MAX1884 only) can

provide preregulation or postregulation for any of the

supplies. For higher current applications, an external

transistor can be added.

Additionally, the VCOM buffer provides a high current

output that is ideal for driving capacitive loads, such as

the backplane of a TFT LCD panel. The positive feed-

back input features dual mode operation, allowing this

input to be connected to an internal 50% resistive-

divider between the buffer’s supply voltage and

ground, or externally adjusted for other voltages.

Also included in the MAX1778/MAX1880–MAX1885 is a

precision 1.25V reference that sources up to 50µA,

logic shutdown, soft-start, power-up sequencing,

adjustable fault detection, thermal shutdown, and an

active-low, open-drain ready output.

BUFFER OUTPUT

VBUFOUT = VSUPB/2

POSITIVE

VPOS = 20V

CBUF

1.0μF

CLDO

4.7μF

CREF

0.22μF

1.0μF

0.1μF

6.8μH

0.1μF

0.22μF

CIN

4.7μF

SHDN

RDY

SUPL

LDOOUT SUPN

SUPP

DRVP

FBP

750kΩ

200kΩ

150kΩ

49.9kΩ

274kΩ

INPUT

VIN = 3.3V

LDO

VLDOOUT = 5V

NEGATIVE

VNEG = -5V

TO LOGIC

BUFOUT

BUF-

BUF+

GND

TGND

FBL

DRVN

FBN

REF

FLTSET

INTG

PGND

SUPB

MAX1778

MAIN

VMAIN = 8V

MAIN

(8V)

COUT

(2) 4.7μF

1.0μF

RRDY

100kΩ

Figure 1. Typical Application Circuit

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

20 ______________________________________________________________________________________

Main Step-up Controller

During normal pulse-width modulation (PWM) opera-

tion, the MAX1778/MAX1880–MAX1885 main step-up

controllers switch at a constant frequency of 500kHz or

1MHz (see Selector Guide), allowing the use of low-

profile inductors and output capacitors. Depending on

the input-to-output voltage ratio, the controller regulates

the output voltage and controls the power transfer by

modulating the duty cycle (D) of each switching cycle:

On the rising edge of the internal clock, the controller

sets a flip-flop when the output voltage is too low, which

turns on the N-channel MOSFET (Figure 2). The induc-

tor current ramps up linearly, storing energy in a mag-

netic field. Once the sum of the feedback voltage error

amplifier, slope-compensation, and current-feedback

signals trip the multi-input comparator, the MOSFET

turns off, the flip-flop resets, and the diode (D1) turns

on. This forces the current through the inductor to ramp

back down, transferring the energy stored in the mag-

netic field to the output capacitor and load. The MOS-

FET remains off for the rest of the clock cycle. Changes

in the feedback voltage-error signal shift the switch-cur-

rent trip level, consequently modulating the MOSFET

duty cycle.

Under very light loads, an inherent switchover to pulse-

skipping takes place (Figure 3). When this occurs, the

controller skips most of the oscillator pulses in order to

reduce the switching frequency and gate charge loss-

es. When pulse-skipping, the step-up controller initiates

a new switching cycle only when the output voltage

drops too low. The N-channel MOSFET turns on, allow-

ing the inductor current to ramp up until the multi-input

comparator trips. Then, the MOSFET turns off and the

diode turns on, forcing the inductor current to ramp

down. When the inductor current reaches zero, the

diode turns off, so the inductor stops conducting cur-

rent. This forces the threshold between pulse-skipping

and PWM operation to coincide with the boundary

between continuous and discontinuous inductor-cur-

rent operation:

LOAD CROSSOVER IN

MAIN

MAIN IN

OSC

()

≈⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

DVV

MAIN IN

MAIN

≈-

MAX1778

MAX1880

MAX1881

MAX1882

MAX1883

MAX1884

MAX1885

VMAIN = 1 + VREF

VREF = 1.25V

( )

ILIM

CREF

VREF

1.25V

INTG

CINTG

RCOMP

(OPTIONAL)

CCOMP

(OPTIONAL)

CIN

COUT

VMAIN

(UP TO 13V)

VIN

(2.7V TO 5.5V)

OSC

(80% DUTY)

REF

GND

PGND

PWM

COMPARATOR

ERROR

AMPLIFIER

ILIM

COMPARATOR

Figure 2. Main Step-Up Converter Block Diagram

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 21

The switching waveforms will appear noisy and asyn-

chronous when light loading causes pulse-skipping

operation; this is a normal operating condition that

improves light-load efficiency.

Dual Charge-Pump Regulator (MAX1778/

MAX1880/MAX1881/MAX1882 Only)

The MAX1778/MAX1880/MAX1881/MAX1882 con-

trollers contain two independent low-power charge

pumps (Figure 4). One charge pump inverts the input

voltage and provides a regulated negative output volt-

age. The second charge pump doubles the input volt-

age and provides a regulated positive output voltage.

The controllers contain internal P-channel and N-chan-

nel MOSFETs to control the power transfer. The

internal MOSFETs switch at a constant frequency

(fCHP = fOSC/2).

Positive Charge Pump

During the first half-cycle, the N-channel MOSFET turns

on and charges flying capacitor CX(POS) (Figure 4).

This initial charge is controlled by the variable N-chan-

nel on-resistance. During the second half-cycle, the N-

channel MOSFET turns off and the P-channel MOSFET

turns on, level shifting CX(POS) by VSUPP volts. This

connects CX(POS) in parallel with the reservoir capaci-

tor COUT(POS). If the voltage across COUT(POS) plus a

diode drop (VPOS + VDIODE) is smaller than the level-

shifted flying capacitor voltage (VCX(POS) + VSUPP),

charge flows from CX(POS) to COUT(POS) until the diode

(D3) turns off.

INDUCTOR CURRENT

ILOAD

tON tOFF

TIME

IPEAK

Figure 3. Discontinuous-to-Continuous Conduction Crossover

Point

MAX1778

MAX1880

MAX1881

MAX1882

VNEG = - VREF

VREF = 1.25V

( )

COUT(NEG)

CX(NEG)

VSUPN

2.7V TO 13V

OSC

REF

PGNDGND

SUPN

DRVN

FBN

SUPP

DRVP

FBP

VPOS = 1 + VREF

VREF = 1.25V

( )

VSUPP

2.7V TO 13V

VSUPD

CREF

0.22μF

VREF

1.25V

CX(POS)

COUT(POS)

VPOS VNEG

Figure 4. Low-Power Charge Pump Block Diagram

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

22 ______________________________________________________________________________________

Negative Charge Pump

During the first half-cycle, the P-channel MOSFET turns

on, and flying capacitor CX(NEG) charges to VSUPN

minus a diode drop (Figure 4). During the second half-

cycle, the P-channel MOSFET turns off, and the N-

channel MOSFET turns on, level shifting CX(NEG). This

connects CX(NEG) in parallel with reservoir capacitor

COUT(NEG). If the voltage across COUT(NEG) minus a

diode drop is greater than the voltage across CX(NEG),

charge flows from COUT(NEG) to CX(NEG) until the diode

(D5) turns off. The amount of charge transferred to the

output is controlled by the variable N-channel on-resis-

tance.

Low-Dropout Linear Regulator (MAX1778/

MAX1881/MAX1883/MAX1884 Only)

The MAX1778/MAX1881/MAX1883/MAX1884 contain a

low-dropout linear regulator (Figure 5) that uses an

internal PNP pass transistor (QP) to supply loads up to

40mA. As illustrated in Figure 5, the 1.25V reference is

connected to the error amplifier, which compares this

reference with the feedback voltage and amplifies the

difference. If the feedback voltage is higher than the

reference voltage, the controller lowers the base cur-

rent of QP, which reduces the amount of current to the

output. If the feedback voltage is too low, the device

increases the pass transistor base current, which

allows more current to pass to the output and increases

the output voltage. However, the linear regulator also

includes an output current limit to protect the internal

pass transistor against short circuits.

The low-dropout linear regulator monitors and controls

the pass transistor’s base current, limiting the output

current to 130mA (typ). In conjunction with the thermal

overload protection, this current limit protects the out-

put, allowing it to be shorted to ground for an indefinite

period of time without damaging the part.

VCOM Buffer

The MAX1778/MAX1880–MAX1885 include a VCOM

buffer, which uses an operational transconductance

amplifier (OTA) to provide a current output that is ideal

for driving capacitive loads, such as the backplane of a

TFT LCD panel. The unity-gain bandwidth of this cur-

rent-output buffer is:

GBW = gm/COUT

where gm is the amplifier’s transconductance. The

bandwidth is inversely proportional to the output

capacitor, so large capacitive loads improve stability;

however, lower bandwidth decreases the buffer’s tran-

sient response time. To improve the transient response

SUPL

CSUPL

VSUPL

4.5V TO 15V

CLDOOUT

LDOOUT

VLDOOUT

1.25V TO (VSUPL - 0.3V)

FBL

VREF

1.25V

ERROR

AMPLIFIER

GND

CURRENT

LIMIT

THERMAL

SENSOR

VLDOOUT = (1 + )VREF

VREF = 1.25V

MAX1778

MAX1881

MAX1883

MAX1884

Figure 5. Low-Dropout Linear Regulator Block Diagram

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 23

times, the amplifier’s transconductance increases as

the output current increases (see Typical Operating

Characteristics).

The VCOM buffer’s positive feedback input features

dual mode operation. The buffer’s output voltage can

be internally set by a 50% resistive divider connected

to the buffer’s supply voltage (SUPB), or the output volt-

age can be externally adjusted for other voltages.

Shutdown (SHDN)

A logic-low level on SHDN shuts down all of the con-

verters and the reference. When shut down, the supply

current drops to 0.1µA to maximize battery life, and the

reference is pulled to ground. The output capacitance,

feedback resistors, and load current determine the rate

at which each output voltage will decay. A logic-level

high on SHDN power activates the MAX1778/

MAX1880–MAX1885 (see Power-Up Sequencing). Do

not leave SHDN floating. If unused, connect SHDN to

IN. A logic-level transition on SHDN clears the fault

latch.

Power-Up Sequencing

Upon power-up or exiting shutdown, the MAX1778/

MAX1880–MAX1885 start a power-up sequence. First,

the reference powers up. Then, the main DC-DC step-

up converter powers up with soft-start enabled. The lin-

ear regulator powers up at the same time as the main

step-up converter; however, the power sequence and

ready output signal are not affected by the regulation of

the linear regulator. While the main step-up converter

powers up, the output of the PWM comparator remains

low (Figure 2), and the step-up converter charges the

output capacitors, limited only by the maximum duty

cycle and current-limit comparator. When the step-up

converter approaches its nominal regulation value and

the PWM comparator’s output changes states for the

first time, the negative charge pump turns on. When the

negative output voltage reaches approximately 90% of

its nominal value (VFBN < 110mV), the positive charge

pump starts up. Finally, when the positive output volt-

age reaches 90% of its nominal value (VFBP > 1.125V),

the active-low ready signal (RDY) goes low (see Power

Ready), and the VCOM buffer powers up. The

MAX1883/MAX1884/MAX1885 do not contain the

charge pumps, but the power-up sequence still con-

tains the charge pumps’ startup logic, which appears

as a delay (2 ✕4096/fOSC) between the step-up con-

verter reaching regulation and when the ready signal

and VCOM buffer are activated.

Soft-Start

For the main step-up regulator, soft-start allows a grad-

ual increase of the current-limit level during startup to

reduce input surge currents. The MAX1778/MAX1880–

MAX1885 divide the soft-start period into four phases.

During the first phase, the controller limits the current

limit to only 0.38A (see Electrical Characteristics),

approximately a quarter of the maximum current limit

SUPB VSUPB

4.5V TO 13V

CBUF

BUFOUT

BUF-

VBUFOUT

1.2V TO (VSUPB - 1.2V)

BUF+

125mV GND

R12

R11

VBUFOUT = ( )VSUPB

R12

R11 + R12

MAX1778

MAX1880

MAX1881

MAX1882

MAX1883

MAX1884

MAX1885

Figure 6. VCOM Buffer Block Diagram

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

24 ______________________________________________________________________________________

(ILX(MAX)). If the output does not reach regulation within

1ms, soft-start enters phase II, and the current limit is

increased by another 25%. This process is repeated for

phase III. The maximum 1.5A (typ) current limit is

reached within 3072 clock cycles or when the output

reaches regulation, whichever occurs first (see the

startup waveforms in the Typical Operating

Characteristics).

For the charge pumps (MAX1778/MAX1880/

MAX1881/MAX1882 only), soft-start is achieved by con-

trolling the rate of rise of the output voltage. Both

charge-pump output voltages are controlled to be in

regulation within 4096 clock cycles, irregardless of out-

put capacitance and load, limited only by the charge

pump’s output impedance. Although the MAX1883/

MAX1884/MAX1885 controllers do not include the

charge pumps, the soft-start logic still contains the

4096 clock cycle startup periods for both charge

pumps.

Fault Trip Level (FLTSET)

The MAX1778/MAX1880–MAX1885 feature dual mode

operation to allow operation with either a preset fault

trip level or an adjustable trip level for the step-up con-

verter and positive charge-pump outputs. Connect FLT-

SET to GND to select the preset 0.9 ✕VREF fault

threshold. The fault trip level may also be adjusted by

connecting a voltage divider from REF to FLTSET

(Figure 8). For greatest accuracy, the total load on the

reference (including current through the negative

charge-pump feedback resistors) should not exceed

50µA so that VREF is guaranteed to be in regulation

(see Electrical Characteristics Table). Therefore, select

R10 in the 100kΩto 1MΩrange, and calculate R9 with

the following equation:

R9 = R10 [(VREF / VFLTSET) - 1]

where VREF = 1.25V, and VFLTSET may range from 0.67

x VREF to 0.85 x VREF. FLTSET’s input bias current has

a maximum value of 50nA. For 1% error, the current

through R10 should be at least 100 times the FLTSET

input bias current (IFLTSET).

Fault Condition

Once RDY is low, if the output of the main regulator or

either low-power charge pump falls below its fault

detection threshold, or if the input drops below its

undervoltage threshold, then RDY goes high imped-

ance and all outputs shut down; however, the reference

remains active. After removing the fault condition, tog-

gle shutdown (below 0.8V) or cycle the input voltage

(below 0.2V) to clear the fault latch and reactivate the

device.

The reference fault threshold is 1.05V. For the step-up

converter and positive charge-pump, the fault trip level is

set by FLTSET (see Fault Trip Level). For the negative

charge pump, the fault threshold measured at the

charge-pump’s feedback input (FBN) is 140mV (typ).

Power Ready (RDY)

Power ready is an open-drain output. When the power-

up sequence for the main step-up converter and low-

power charge pumps has properly completed, the 14V

MOSFET turns on and pulls RDY low with a 125Ω(typ)

on-resistance. If a fault is detected on any of these

three outputs, the internal open-drain MOSFET appears

as a high impedance. Connect a 100kΩpullup resistor

between RDY and IN for a logic-level output.

Voltage Reference (REF)

The voltage at REF is nominally 1.25V. The reference

can source up to 50µA with good load regulation (see

Typical Operating Characteristics). Connect a 0.22µF

ceramic bypass capacitor between REF and GND.

Thermal-Overload Protection

Thermal-overload protection limits total power dissipa-

tion in the MAX1778/MAX1880–MAX1885. When the

junction temperature exceeds TJ= +160°C, a thermal

sensor activates the fault protection, which shuts down

the controller, allowing the IC to cool. Once the device

cools down by 15°C, toggle shutdown (below 0.8V) or

cycle the input voltage (below 0.2V) to clear the fault

latch and reactivate the controller. Thermal-overload

protection protects the controller in the event of fault

conditions. For continuous operation, do not exceed

the absolute maximum junction-temperature rating of

TJ= +150°C.

Operating Region and Power Dissipation

The MAX1778/MAX1880–MAX1885s’ maximum power

dissipation depends on the thermal resistance of the IC

package and circuit board, the temperature difference

between the die junction and ambient air, and the rate

of any airflow. The power dissipated in the device

depends on the operating conditions of each regulator

and the buffer.

The step-up controller dissipates power across the

internal N-channel MOSFET as the controller ramps up

the inductor current. In continuous conduction, the

power dissipated internally can be approximated by:

PIV

STEP UP MAIN MAIN

OSC

DS ON

−≈⎛

⎝

⎜⎞

⎠

⎟+⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

()

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 25

where IMAIN includes the primary load current and the

input supply currents for the charge pumps (see

Charge-Pump Input Power and Efficiency

Considerations), linear regulator, and VCOM buffer.

The linear regulator generates an output voltage by dis-

sipating power across an internal pass transistor, so

the power dissipation is simply the load current times

the input-to-output voltage differential:

When driving an external transistor, the internal linear

regulator provides the base drive current. Depending

on the external transistor’s current gain (β) and the

maximum load current, the power dissipated by the

internal linear regulator may still be significant:

The charge pumps provide regulated output voltages

by dissipating power in the low-side N-channel MOS-

FET, so they could be modeled as linear regulators fol-

lowed by unregulated charge pumps. Therefore, their

power dissipation is similar to a linear regulator:

where N is the number of charge-pump stages, VDIODE

is the diodes’ forward voltage, and VSUPD is the posi-

tive charge-pump diode supply (Figure 4).

The VCOM buffer’s power dissipation depends on the

capacitive load (CLOAD) being driven, the peak-to-

peak voltage change (VP-P) across the load, and the

load’s switching rate:

To find the total power dissipated in the device, the

power dissipated by each regulator and the buffer must

be added together:

The maximum allowed power dissipation is 975mW (24-

pin TSSOP) / 879mW (20-pin TSSOP) or:

PMAX = (TJ(MAX) - TA) / ( θJB + θBA)

where TJ- TAis the temperature difference between

the controller’s junction and the surrounding air, θJB (or

θJC) is the thermal resistance of the package to the

board, and θBA is the thermal resistance from the print-

ed circuit board to the surrounding air.

Design Procedure

Main Step-Up Converter

Output Voltage Selection

Adjust the output voltage by connecting a voltage-

divider from the output (VMAIN) to FB to GND (see

Typical Operating Circuit). Select R2 in the 10kΩto

50kΩrange. Calculate R1 with the following equations:

R1 = R2 [(VMAIN / VREF) - 1]

where VREF = 1.25V. VMAIN may range from VIN to 13V.

Inductor Selection

Inductor selection depends upon the minimum required

inductance value, saturation rating, series resistance, and

size. These factors influence the converter’s efficiency,

maximum output load capability, transient response time,

and output voltage ripple. For most applications, values

between 4.7µH and 22µH work best with the controller’s

switching frequency (Tables 1 and 2).

The inductor value depends on the maximum output

load the application must support, input voltage, output

voltage, and switching frequency. With high inductor

values, the MAX1778/MAX1880–MAX1885 source high-

er output currents, have less output ripple, and enter

continuous conduction operation with lighter loads;

however, the circuit’s transient response time is slower.

On the other hand, low-value inductors respond faster

to transients, remain in discontinuous conduction oper-

ation, and typically offer smaller physical size for a

given series resistance and current rating. The equa-

tions provided here include a constant LIR, which is the

ratio of the peak-to-peak AC inductor current to the

average DC inductor current. For a good compromise

between the size of the inductor, power loss, and out-

put voltage ripple, select an LIR of 0.3 to 0.5. The

inductance value is then given by:

I f LIR

MIN IN MIN

MAIN

MAIN IN MIN

MAIN MAX OSC

() ()

()

=⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

-η

PP P

PPP

TOTAL STEP UP LDO INT

NEG POS BUF

()

+++

PVCfV

BUF P P LOAD LOAD SUPB

PIV VNV

PIV VNV V

NEG NEG SUPN DIODE NEG

POS POS SUPP DIODE SUPD POS

()

[]

()

[]

PIVV V

IVV

LDO INT LDO SUPL LDO

LDOOUT SUPL LDOOUT

()

( )

()

[]

β-

PIVV

LDO INT LDO SUPL LDO()

( )=-

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

26 ______________________________________________________________________________________

where ηis the efficiency, fOSC is the oscillator frequen-

cy (see Electrical Characteristics), and IMAIN includes

the primary load current and the input supply currents

for the charge pumps (see Charge-Pump Input Power

and Efficiency Considerations), linear regulator, and

VCOM buffer. Considering the typical application cir-

cuit, the maximum average DC load current

(IMAIN(MAX)) is 300mA with an 8V output. Based on the

above equations and assuming 85% efficiency, the

inductance value is then chosen to be 4.7µH.

The inductor’s saturation current rating should exceed

the peak inductor current throughout the normal operat-

ing range. The peak inductor current is then given by:

Under fault conditions, the inductor current may reach

up to 1.85A (ILIM(MAX)), see Electrical Characteristics).

However, the controller’s fast current-limit circuitry

allows the use of soft-saturation inductors while still pro-

tecting the IC.

The inductor’s DC resistance may significantly affect

efficiency due to the power loss in the inductor. The

power loss due to the inductor’s series resistance (PLR)

may be approximated by the following equation:

where RLis the inductor’s series resistance. For best per-

formance, select inductors with resistance less than the

internal N-channel MOSFET on-resistance (0.35Ωtyp).

Use inductors with a ferrite core or equivalent. To mini-

mize radiated noise in sensitive applications, use a

shielded inductor.

Output Capacitor

Output capacitor selection depends on circuit stability

and output voltage ripple. A 10µF ceramic capacitor

works well in most applications (Tables 1 and 2).

Additional feedback compensation is required (see

Feedback Compensation) to increase the margin for

stability by reducing the bandwidth further. In cases

where the output capacitance is sufficiently large, addi-

tional feedback compensation will not be necessary.

Output voltage ripple has two components: variations in

the charge stored in the output capacitor with each LX

pulse, and the voltage drop across the capacitor’s

equivalent series resistance (ESR) caused by the cur-

rent into and out of the capacitor:

where IPEAK is the peak inductor current (see Inductor

Selection). For ceramic capacitors, the output voltage

ripple is typically dominated by VRIPPLE(C). The voltage

rating and temperature characteristics of the output

capacitor must also be considered.

Feedback Compensation

For stability, add a pole-zero pair from FB to GND in the

form of a compensation resistor (RCOMP) in series with

a compensation capacitor (CCOMP) as shown in Figure

2. Select RCOMP to be half the value of R2, the low-side

feedback resistor.

Integrator Capacitor

The MAX1778/MAX1880–MAX1885 contain an internal

current integrator that improves the DC load regulation

but increases the peak-to-peak transient voltage (see

the load-transient waveforms in the Typical Operating

Characteristics). For highly accurate DC load regula-

tion, enable the current integrator by connecting a

470pF (ƒOSC = 1MHz)/1000pF (ƒOSC = 500kHz)

capacitor to INTG. To minimize the peak-to-peak tran-

sient voltage at the expense of DC regulation, disable

the integrator by connecting INTG to REF. When using

the MAX1883/MAX1884/MAX1885, connect a 100kΩ

resistor to GND when disabling the integrator.

Input Capacitor

The input capacitor (CIN) in step-up designs reduces

the current peaks drawn from the input supply and

reduces noise injection. The value of CIN is largely

determined by the source impedance of the input sup-

ply. High source impedance requires high input capac-

itance, particularly as the input voltage falls. Since

step-up DC-DC converters act as “constant-power

”

loads to their input supply, input current rises as input

voltage falls. A good starting point is to use the same

capacitance value for CIN as for COUT.

VV V

V I R AND

VVV

RIPPLE RIPPLE C RIPPLE ESR

RIPPLE ESR PEAK ESR COUT

RIPPLE C MAIN IN

MAIN

OUT OSC

() ( )

()

≈

≈−

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

IXV

LR L MAIN MAIN

≅⎛

⎝

⎜⎞

⎠

⎟

IIV

LIR

PEAK

MAIN MAX MAIN

IN MIN

()

=⎛

⎝

⎜

⎞

⎠

⎟+

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 27

Rectifier Diode

Use a Schottky diode with an average current rating

equal to or greater than the peak inductor current, and

a voltage rating at least 1.5 times the main output volt-

age (VMAIN).

Charge Pumps (MAX1778/ MAX1880/

MAX1881/MAX1882 Only)

Selecting the Number of Charge-Pump Stages

The number of charge-pump stages required to regu-

late the output voltage depends on the supply voltage,

output voltage, load current, switching frequency, the

diode’s forward voltage drop, and ceramic capacitor

values.

For positive charge-pump outputs, the number of

required stages may be determined by:

where VSUPD is the positive charge-pump diode supply

(Figure 4), VDIODE is the diode’s forward voltage drop,

and RTX is the charge pump’s output impedance. The

charge pump’s output impedance may be approximat-

ed using the following equation:

where the charge pump’s switching frequency (fCHP) is

equal to 0.5 x fOSC, the P-channel MOSFET’s on-resis-

tance (RPCH(ON)) is 10Ω, and the N-channel MOSFET’s

on-resistance (RNCH(ON)) is 4Ω(see Electrical

Characteristics).

For negative charge pump outputs, the number of

required stages may be determined by:

where NNEG is rounded up to the nearest integer.

VVRI

NEG NEG

SUPN DROP TX LOAD

.( ) ≥+

⎛

⎝

⎜⎞

⎠

⎟

-112

RR R Cf

TX PCH ON NCH ON X CHP

OUT CHP

( )

() ()

=++

⎛

⎝

⎜⎞

⎠

⎟

+⎛

⎝

⎜⎞

⎠

⎟

NVV

VVRI

POS POS SUPD

SUPP DIODE TX LOAD

.( ) ≥+

⎛

⎝

⎜⎞

⎠

⎟

-112

CIRCUIT 1 CIRCUIT 2 CIRCUIT 3 CIRCUIT 4 CIRCUIT 5

VIN 3.3V 3.3V 3.3V 5V 5V

VMAIN 9V 9V 9V 12V 12V

IMAIN(MAX) 100mA 200mA 200mA 220mA 220mA

VNEG -5V -5V -5V -5V -5V

INEG 2mA 5mA 5mA 5mA 5mA

VPOS 24V 24V 24V 24V 24V

IPOS 2mA 5mA 5mA 5mA 5mA

L 2.2µH 4.7µH 4.7µH 6.8µH 6.8µH

IPEAK >1A >1A >1A >1A >1A

COUT 4.7µF 10µF 20µF 10µF 20µF

R1 309kΩ309kΩ309kΩ429kΩ429kΩ

R2 49.9kΩ49.9kΩ49.9kΩ49.9kΩ49.9kΩ

RCOMP None None 39kΩ* None 20kΩ*

CCOMP None None 100pF* None 200pF*

Table 1. MAX1778/MAX1880/MAX1883 Component Values (fOSC = 1MHz)

*RCOMP and CCOMP are connected between the step-up converter’s output (VMAIN) and FB.

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

28 ______________________________________________________________________________________

Charge-Pump Input Power and

Efficiency Considerations

The charge pumps in the MAX1778/MAX1880/

MAX1881/MAX1882 provide regulated output voltages

by controlling the voltage drop across the low-side N-

channel MOSFET, so they can be modeled as linear

regulators followed by an unregulated charge pump

when determining the input power requirements and

efficiency.

The charge pump only provides charge to the output

capacitor during half the period (50% duty cycle), so

the input current is a function of the number of stages

and the load current:

for the positive charge pump, and:

for the negative charge pump, where N is the number

of charge pump stages.

The efficiency characteristics of the MAX1778/

MAX1880/MAX1881/MAX1882 regulated charge

pumps are similar to a linear regulator. It is dominated

by quiescent current at low output currents and by the

IIN

SUPP POS

() =+1

CIRCUIT 6 CIRCUIT 7 CIRCUIT 8 CIRCUIT 9

VIN 3.3V 3.3V 3.3V 3.3V

VMAIN 9V 9V 9V 9V

IMAIN(MAX) 100mA 100mA 200mA 200mA

VNEG -5V -5V -5V -5V

INEG 2mA 2mA 5mA 5mA

VPOS 24V 24V 24V 24V

IPOS 2mA 2mA 5mA 5mA

L 4.7µH 10µH 10µH 10µH

IPEAK >1A >1A >1A >1A

COUT 4.7µF 10µF 10µF 20µF

R1 309kΩ309kΩ309kΩ309kΩ

R2 49.9kΩ49.9kΩ49.9kΩ49.9kΩ

RCOMP None None None 20kΩ*

CCOMP None None None 200pF*

Table 2. MAX1881/MAX1882/MAX1884/MAX1885 Component Values (fOSC = 500kHz)

SUPPLIER PHONE FAX

INDUCTORS

Coilcraft 847-639-6400 847-639-1469

Coiltronics 561-241-7876 561-241-9339

Sumida USA 847-956-0666 847-956-0702

Toko 847-297-0070 847-699-1194

CAPACITORS

AVX 803-946-0690 803-626-3123

Kemet 408-986-0424 408-986-1442

Sanyo 619-661-6835 619-661-1055

Taiyo Yuden 408-573-4150 408-573-4159

DIODES

Central

Semiconductor 516-435-1110 516-435-1824

International

Rectifier 310-322-3331 310-322-3332

Motorola 602-303-5454 602-994-6430

Nihon 847-843-7500 847-843-2798

Zetex 516-543-7100 516-864-7630

Table 3. Component Suppliers

*RCOMP and CCOMP are connected between the step-up converter’s output (VMAIN) and FB.

IIN

SUPP POS

() =+1

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 29

input voltage at higher output currents (see Typical

Operating Characteristics). So the maximum efficiency

may be approximated by:

for the positive charge pump, and:

for the negative charge pump, where VSUPD is the pos-

itive charge pump’s diode supply (Figure 4).

Output Voltage Selection

Adjust the positive output voltage by connecting a volt-

age divider from the output (VPOS) to FBP to GND (see

Typical Operating Circuit). Adjust the negative output

voltage by connecting a voltage-divider from the output

(VNEG) to FBN to REF. Select R4 and R6 in the 50kΩto

100kΩrange. Higher resistor values improve efficiency

at low output current but increase output voltage error

due to the feedback input bias current. For the negative

charge pump, higher resistor values also reduce the

load on the reference, which should not exceed 50µA

for greatest accuracy (including current through the

FLTSET resistors) to guarantee that VREF remains in

regulation (see Electrical Characteristics Table).

Calculate the remaining resistors with the following

equations:

R3 = R4 [(VPOS / VREF) - 1]

R5 = R6 |VNEG / VREF|

where VREF = 1.25V. VPOS may range from VSUPP to

40V, and VNEG may range from 0V to -40V.

Flying Capacitor

Increasing the flying capacitor (CX) value increases the

output current capability. Above a certain point,

increasing the capacitance has a negligible effect

because the output current capability becomes domi-

nated by the internal switch resistance and the diode

impedance. The flying capacitor’s voltage rating must

exceed the following:

for the positive charge pump, and:

for the negative charge pump, where N is the stage

number in which the flying capacitor appears, and

VSUPD is the positive charge pump’s diode supply

(Figure 4). For example, the two-stage positive charge

pump in the typical application circuit (Figure 1) where

VSUPP = VSUPD = 8V contains two flying capacitors.

The flying capacitor in the first stage (C4) requires a

voltage rating over 12V. The flying capacitor in the sec-

ond stage (C6) requires a voltage rating over 24V.

Charge-Pump Output Capacitor

Increasing the output capacitance or decreasing the

ESR reduces the output ripple voltage and the peak-to-

peak transient voltage. With ceramic capacitors, the

output voltage ripple is dominated by the capacitance

value. Use the following equation to approximate the

required capacitor value:

where fCHP is typically fOSC/2 (see Electrical

Characteristics).

Charge-Pump Input Capacitor

Use a bypass capacitor with a value equal to or greater

than the flying capacitor. Place the capacitor as close

to the IC as possible. Connect directly to power ground

(PGND).

Charge-Pump Rectifier Diodes

Use Schottky diodes with a current rating equal to or

greater than two times the average charge-pump input

current, and a voltage rating at least 1.5 times VSUPP

for the positive charge pump and VSUPN for the nega-

tive charge pump.

Low-Dropout Linear Regulator (MAX1778/

MAX1881/MAX1883/MAX1884 Only)

Output Voltage Selection

Adjust the linear-regulator output voltage by connecting

a voltage-divider from LDOOUT to FBL to GND (Figure

5). Select R8 in the 5kΩto 50kΩrange. Calculate R7

with the following equation:

R7 = R8 [(VLDOOUT / VFBL) - 1]

where VFBL = 1.25V, and VLDOOUT may range from

1.25V to (VSUPL - 300mV). FBL’s input bias current is

OUT LOAD

CHP RIPPLE

≥

VVN

CXN NEG SUPN()

.( )>15

VVVN

CXN POS SUPD SUPP()

. ( )>+

[]

15 1-

ηNEG

NEG

SUPN

≅

ηPOS

VVN

POS

SUPD SUPP

≅+

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

30 ______________________________________________________________________________________

0.8µA (max). For less than 0.5% error due to FBL input

bias current (IFBL), R8 must be less than 8kΩ.

Capacitor Selection and Regulator Stability

Capacitors are required at the input and output of the

MAX1778/MAX1881/MAX1883/MAX1884 for stable

operation over the full temperature range and with load

currents up to 40mA. Connect a 1µF input bypass

capacitor (CSUPL) between SUPL and ground to lower

the source impedance of the input supply. Connect a

ceramic capacitor between LDOOUT and ground,

using the following equation to determine the lowest

value required for stable operation:

For example, with a 5V linear regulator output voltage

and a maximum 40mA load, use at least 4µF of output

capacitance. Applications that experience high-current

load pulses may require more output capacitance.

The ESR of the linear regulator’s output capacitor

(CLDOOUT) affects stability and output noise. Use out-

put capacitors with an ESR of 0.1Ωor less to ensure

stability and optimum transient response. Surface-

mount ceramic capacitors are good for this purpose.

Place CSUPL and CLDOOUT as close to the linear regu-

lator as possible to minimize the impact of PC board

trace inductance.

External Pass Transistor

For applications where the linear regulator currents

exceed 40mA or where the power dissipation in the IC

needs to be reduced, an external NPN transistor can

be used. In this case, the internal LDO only provides

the necessary base drive while the external NPN tran-

sistor supports the load, so most of the power dissipa-

tion occurs across the external transistor’s collector

and emitter.

Selection of the external NPN transistor is based on

three factors: the package’s power dissipation, the cur-

rent gain (β), and the collector-to-emitter saturation volt-

age (VCE(SAT)). First, the maximum power dissipation

should not exceed the transistor’s package rating:

Once the appropriate package type is selected, con-

sider the NPN transistor’s current gain. Since the inter-

nal LDO cannot source more than 40mA (min), the

transistor’s current gain must be high enough at the

lowest collector-to-emitter voltage to support the maxi-

mum output load:

For stable operation, place a capacitor (CLDOOUT) and

a minimum load resistor (R5) at the output of the inter-

nal linear regulator (the base of the external transistor)

to set the dominant pole:

Since the LDO cannot sink current, a minimum pull-

down resistor (R5) is required at the base of the NPN

transistor to sink leakage currents and improve the

high-to-low load-transient response. Under no-load

conditions, leakage currents from the internal pass

transistor supply the output capacitor (CLDOOUT), even

when the transistor is off. As the leakage currents

increase over temperature, charge may build up on

CLDOOUT, making the linear regulator’s output rise

above its set point. Therefore, R5 must sink at least

100µA to guarantee proper regulation. Additionally, the

minimum load current provided by R5 improves the

high-to-low load transients by lowering the impedance

seen by CLDOOUT after the transient occurs. Therefore,

if large load transients are expected, select R5 so that

the minimum load current is 10% of the transistor’s

maximum base current:

Alternatively, output capacitance placed on the external

linear regulator’s output (the emitter) adds a second pole

that could destabilize the regulator. A capacitive-divider

from the transistor’s base to the feedback input (C2 and

C3, Figure 7) circumvents this second pole by adding a

pole-zero pair. Furthermore, to minimize excessive over-

shoot, the capacitive-divider’s ratio must be the same as

the resistive-divider’s ratio. Once the output capacitor is

selected, using the following equations to determine the

required capacitive-divider values:

CC CR

LDO

REF

LDO

23 100 14

+≥ +

⎛

⎝

⎜⎞

⎠

⎟

+=+=

RVV

LDO

LDOOUT MIN

LDO MIN

LOAD MAX

507 01 07

. .

( .)

() ( )

=+=+

⎡

⎣

⎢

Cms

xVV

LDOOUT LDO

LDO LOAD MAX

MIN

. ()

≥⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

05 1

5β

βMIN LOAD MAX

ImA

()

≥-40

PV V xI

COLLECTOR LDO LOAD MAX

( ) ()

=−

CmsX

LDOOUT

LDOOUT MAX

LDOOUT

. ()

≥

⎛

⎝

⎜

⎞

⎠

⎟

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 31

Input-Output (Dropout) Voltage and Startup

A linear regulator’s minimum input-to-output voltage dif-

ferential (dropout voltage) determines the lowest use-

able supply voltage. Because the MAX1778/

MAX1881/MAX1883/MAX1884 use an internal PNP

transistor (or external NPN transistor), their dropout

voltage is a function of the transistor’s collector-to-emit-

ter saturation voltage (see Typical Operating

Characteristics). The linear regulator’s quiescent cur-

rent increases when in dropout.

The internal linear regulator will try to start up once its

supply voltage (VSUPL) exceeds 4V. When the linear

regulator powers up, the linear regulator may be in

dropout if the linear regulator’s output set voltage is

higher than its input supply voltage. Therefore, during

this brief period, the linear regulator draws additional

supply current until the input supply voltage exceeds

the output set voltage plus the pass transistor’s satura-

tion voltage (VLDO(SET) + VCE(SAT)).

VCOM Buffer (Operational

Transconductance Amplifier)

Buffer Output Voltage and Capacitor Selection

The positive input (BUF+) features dual mode opera-

tion. Connect BUF+ to GND for the preset VSUPB/2

output voltage, set by an internal 50% resistive-divider.

Adjust the amplifier’s output voltage by connecting a

voltage-divider from SUPB to BUF+ to GND (Figure 6).

Select R12 in the 10kΩto 100kΩrange. Calculate R11

with the following equation:

where VSUPB may range from 4.5V to 13V, and VBUF+

may range from 1.2V to (VSUPB - 1.2V). Connect a mini-

mum 1µF ceramic capacitor from BUFOUT to ground.

PC Board Layout and Grounding

Careful PC board layout is extremely important for

proper operation. Follow the following guidelines for

good PC board layout:

1) Place the main step-up converter output diode and

output capacitor less than 0.2in (5mm) from the LX

and PGND pins with wide traces and no vias.

2) Separate analog ground and power ground. The

ground connections for the step-up converter’s and

charge pump’s input and output capacitors should

be connected to the power ground plane. The lin-

ear regulator’s and VCOM buffer’s input and output

capacitors should be connected to a separate

power-ground path, star-connected to the PGND

pin to minimize voltage drops. When using multi-

layer boards, the top layer should contain the boost

SUPB

BUF

11 12 1 =⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

SHDN

LDOOUT

6.8μH

INPUT

VIN = 3.3V

0.22μF

COUT

(2) 4.7μF

CIN

4.7μFR1

274kΩ

49.9kΩ

GND

FBL

REF

INTG

PGND

CREF

0.22μF

MAX1778

MAX1883

(MAX1881)*

(MAX1884)*

49.9kΩ

CLDO

1μF

0.01μF

CLDOOUT

4.7μF

CLDOIN

1μF

1.5kΩ

MAIN

VMAIN = 8V

LDO

VLDO = 2.5V

SUPL

Figure 7. External Linear Regulator

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

32 ______________________________________________________________________________________

regulator and charge-pump power ground plane,

and the inner layer should contain the analog

ground plane and power-ground plane/path for the

VCOM buffer and LDO. Connect all three ground

planes together at one place near the PGND pin.

3) Locate all feedback resistive-dividers as close to

their respective feedback pins as possible. The

voltage-divider’s center trace should be kept short.

Avoid running any feedback trace near the LX

switching node or the charge-pump drivers. The

resistive-dividers’ ground connections should be to

analog ground (GND).

4) When using multilayer boards, separate the top sig-

nal layer and bottom signal layer with a ground

plane between to eliminate capacitive coupling

between fast-charging nodes on the top layer and

high-impedance nodes on the bottom layer. The

fast-charging nodes, such as the LX and charge-

pump driver nodes, should not have any other

traces or ground planes near by.

5) Keep the charge-pump circuitry as close to the IC

as possible, using wide traces and avoiding vias

when possible. Place 0.1µF ceramic bypass

capacitors near the charge-pump input pins (SUPP

and SUPN) to the PGND pin.

6) To maximize output power and efficiency and mini-

mize output ripple voltage, use extra wide, power

ground traces, and solder the IC’s power ground

pin directly to it.

Refer to the MAX1778/MAX1880-MAX1885 evaluation

kit for an example of proper board layout.

BUFFER OUTPUT

VBUFOUT = VSUPB/2

POSITIVE

VPOS = 20V

SHDN

RDY

SUPL

LDOOUT SUPN

SUPP

DRVP

FBP

10μH

INPUT

VIN = 5V

0.22μF

1μFC6

0.01μF

1.0μF

CREF

0.22μF

0.1μF

CBUF

1.0μF

CCOMP

470pF

COUT

(2) 10μF

0.1μF

CIN

(2) 4.7μF

CLDOOUT

4.7μF

RRDY

100kΩ

1.5kΩ

10kΩ

316kΩR9

30kΩ

750kΩ

49.9kΩ

86.6kΩ

10kΩ

RCOMP

4.7kΩ

R10

100kΩ

49.9kΩ

16.4kΩ

NEGATIVE

VNEG = -8V

TO LOGIC

BUFOUT

BUF-

BUF+

FLTSET

GND

TGND

FBL

DRVN

FBN

REF

INTG

PGND

SUPB

MAX1778

LDO

VLDO = 3.3V

REF

MAIN

VMAIN = 12V

Figure 8. 5V Input Monitor Application

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 33

Applications Information

Low-Profile Components

Notebook applications generally require low-profile

components, potentially limiting the circuit’s perfor-

mance. For example, low-profile inductors typically

have lower saturation ratings and more series resis-

tance, limiting output current and efficiency. Low-profile

capacitors have lower voltage ratings for a given

capacitance value, so 3.3µF low-profile capacitors with

voltage ratings greater than 10V were not available at

the time of publication.

Desktop Monitors

Monitor applications do not have the same component

height restrictions associated with laptops, allowing

more flexibility in component selection (Figure 8).

Larger output capacitors with higher voltage ratings

allow configurations with output voltages above 10V.

Additionally, physically larger inductors with less series

resistance and higher saturation ratings provide more

output current and higher efficiency.

Input Voltage Above and

Below the Output Voltage

Combining the step-up converter and linear regulator

as shown in Figure 9 provides output voltage regulation

above and below the input voltage. Supplied by the

step-up converter, the linear regulator output provides

a constant output voltage (VLDO). When the input volt-

age exceeds the main step-up converter’s nominal out-

put voltage, the controller stops switching but the linear

regulator maintains the output voltage. When the input

voltage drops below the output voltage, the step-up

BUFFER OUTPUT

VBUFOUT = VSUPB/2

POSITIVE

VPOS = 24V

SHDN

RDY

BUF-

BUFOUT

SUPN

SUPP

6.8μH

POWER INPUT

VBATT = 10V TO 15V

INPUT

VIN = 3.3V TO 5V C1

0.1μF

CLDO

(2) 3.3μF

0.1μF

1.0μF

CBUF

1.0μF

CINTG

470pF

0.1μF

COUT

(3) 3.3μF

0.1μF

CIN

4.7μF

CLDOOUT

3.3μF

RRDY

100kΩ

R10

100kΩ

475kΩ

909kΩ

49.9kΩ

511kΩ

49.9kΩ

470kΩ

49.9kΩ

6.8kΩ

NEGATIVE

VNEG = -12V

TO LOGIC

FBL

SUPL

LDOOUT

BUF+

FBP

DRVP

GND

TGND

FBN

DRVN

REF

FLTSET

INTG

PGND

SUPB

CREF

0.22μF

MAX1778

LDO

VLDO = 13V

1.0μF

30kΩ

Figure 9. Input Voltage Above and Below the Output Voltage

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

34 ______________________________________________________________________________________

converter steps up the input voltage so that the linear

regulator will not drop out. Therefore, to guarantee that

the external pass transistor does not saturate, the step-

up converter’s output voltage must be set above the lin-

ear regulator’s output voltage plus the transistor’s

saturation rating (VMAIN ≥VLDO + VSAT).

Power-Up Sequencing and Fault Protection

The MAX1778/MAX1880–MAX1885’s fault protection

cannot be activated until the power-up sequence is

successfully completed and the power ready output

goes low. Therefore, faults on the main output or posi-

tive charge-pump output could damage the controller

or external components. Additional fault protection may

be added as shown in Figure 10. The external MOSFET

and PNP transistor isolate the positive outputs during

startup. When the controller finishes the power-up

sequence, the power-ready output goes low, turning on

the PNP transistor. Any fault on the positive charge-

pump output will pull down the charge pump’s output

voltage and trigger the fault protection; otherwise, the

MOSFET’s gate slow charges. Once the MOSFET turns

on, any faults on the main step-up converter’s output

will pull down the main output voltage and trigger the

fault protection.

VCOM Buffer Startup

The VCOM buffer does not include soft-start. Therefore,

once the VCOM buffer turns on, it draws high surge

currents while charging the output capacitance. In

some applications, the buffer’s high startup surge

current could potentially trip the fault detection circuit,

forcing the controller to shut down. In these cases,

adding a soft-start resistive divider between SUPB and

BUFOUT reduces the startup surge current and voltage

drops associated with this load (Figure 11), as shown in

SYSTEM

POSITIVE

VPOS(SYS) = 20V

STARTUP

POSITIVE

VPOS(START) = 20V

INPUT

VIN = 3.3V

SHDN

SUPP

6.8μH

INPUT

VIN = 3.3V

0.22μF

1.0μF

COUT

(2) 3.3μF

0.1μF

CIN

4.7μF

R10

100kΩ

RRDY

5.1kΩ

274kΩ

49.9kΩ

10kΩ

RDY

FBP

DRVP

GND

TGND

REF

FLTSET

INTG

PGND

CREF

0.22μF

MAX1778

3.3μF

SYSTEM MAIN

VMAIN(SYS) = 8V

STARTUP MAIN

VMAIN(START) = 8V

C10

0.1μF

100kΩ

750kΩ

49.9kΩ

30kΩ

Figure 10. Power-Up Sequencing and Fault Protection;

the Typical Operating Characteristics. Set the resistive

divider to precharge BUFOUT, matching the buffer’s

output set voltage:

These resistor values are selected to charge the output

capacitor close to the output set voltage before the

buffer starts up:

CRR

BUFOUT OSC

(||) 34 5000

≈

SUPB

BUFOUT

34 1 =⎛

⎝

⎜⎞

⎠

⎟−

⎡

⎣

⎢

⎤

⎦

⎥

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 35

PART

STEP-UP

SWITCHING

FREQUENCY

(Hz)

DUAL

CHARGE

PUMPS

LINEAR

REGULATOR

MAX1778 1M Yes Yes

MAX1880 1M Yes No

MAX1881 500k Yes Yes

MAX1882 500k Yes No

MAX1883 1M No Yes

MAX1884 500k No Yes

MAX1885 500k No No

Selector Guide

BUFFER OUTPUT

VBUFOUT = VSUPB/2

SHDN

SUPB

6.8μH

INPUT

VIN = 3.3V

0.22μF

COUT

(2) 4.7μF

CIN

4.7μFR1

274kΩ

49.9kΩ

BUFOUT

GND

BUF+

BUF-

REF

INTG

PGND

CREF

0.22μF

MAX1778

CSUPB

1.0μF

CBUF

1.0μF

10kΩ

MAIN

VMAIN = 8V

R3 = R4[( ) -1]

VSUPB

VBUFOUT

Figure 11. VCOM Buffer Soft-Start;

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

36 ______________________________________________________________________________________

Typical Operating Circuit

BUFFER OUTPUT

POSITIVE

SHDN

RDY

SUPL

LDOOUT

SUPN

SUPP

DRVP

FBP

INPUT

LDO OUTPUT

NEGATIVE

TO LOGIC

BUFOUT

BUF-

BUF+

FLTSET

GND

TGND

FBL

DRVN

FBN

REF

INTG

PGND

SUPB

MAX1778

MAIN

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________ 37

Pin Configurations

TGND

PGNDBUF+

INTG

TOP VIEW

DRVP

SUPP

DRVN

SUPNGND

BUFOUT

SUPB

BUF-

FLTSET

FBL

LDOOUT

SUPL

FBN

FBP

REF

TSSOP

MAX1778

MAX1881

RDY

SHDN

TGND

PGNDBUF+

INTG

DRVP

SUPP

DRVN

SUPNGND

BUFOUT

SUPB

BUF-

FLTSET

N.C.

FBN

FBP

REF

TSSOP

MAX1880

MAX1882

RDY

SHDN

TGND

PGNDBUF+

INTG

TOP VIEW

N.C.

FLTSET

FBLGND

BUFOUT

SUPB

BUF-

LDOOUT

SUPL

REF

MAX1883

MAX1884

TSSOP

RDY

SHDN

TGND

PGNDBUF+

INTG

N.C.

FLTSET

N.C.GND

BUFOUT

SUPB

BUF-

N.C.

REF

MAX1885

TSSOP

RDY

SHDN

Chip Information

TRANSISTOR COUNT: 3739

MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

38 ______________________________________________________________________________________

Quad-Output TFT LCD DC/DC

Converters with Buffer

MAX1778/MAX1880–MAX1885

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

39 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

TSSOP4.40mm.EPS

PACKAGE OUTLINE, TSSOP 4.40mm BODY

21-0066 1

Package Information

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