© Semiconductor Components Industries, LLC, 2016
May, 2018 − Rev. 2 1Publication Order Number:
NCP59748/D
NCP59748
1.5 A, Dual-Rail Very
Low‐Dropout Linear
Regulator with
Programmable Soft‐Start
The NCP59748 is dual−rail very low dropout voltage regulator,
capable of providing an output current in excess of 1.5 A with a
dropout voltage of 60 mV typ. at full load current. The devices are
stable with ceramic and any other type of output capacitor ≥ 2.2 mF.
This series contains adjustable output voltage version with output
voltage down to 0.8 V. Internal protection features consist of built-in
thermal shutdown and output current limiting protection.
User-programmable Soft-Start and Power-Good pins are available on
both QFN and DFN versions.
The NCP59748 is offered in DFN10 3×3 and QFN20 5×5 packages.
Features
•Output Current in Excess of 1.5 A
•VIN Range: 0.8 V to 5.5 V
•VBIAS Range: 2.7 V to 5.5 V
•Output Voltage Range: 0.8 V to 3.6 V
•Dropout Voltage: 60 mV at 1.5 A
•Programmable Soft-Start
•Open Drain Power Good Output
•Fast Transient Response
•Stable with Any Type of Output Capacitor ≥2.2 mF
•Current Limit and Thermal Shutdown Protection
•These are Pb−Free Devices
Applications
•Consumer and Industrial Equipment Point of Load Regulation
•FPGA, DSP and Logic Power Supplies
•Switching Power Supply Post Regulation
Figure 1. Typical Application Schematic
NCP59748
QFN20
CASE 485DB
MARKING DIAGRAMS
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A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G= Pb-Free Package
NCP
59748
ALYWG
G
(Note: Microdot may be in either location)
PIN CONNECTIONS
See detailed ordering, marking and shipping information in the
package dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
DFN10
CASE 485C
DFN10
NCP59748
AWLYYWWG
G
QFN20
1
1
QFN20−5y5−0.65P
DFN10−3y3−0.5P
OUT
OUT
FB
SS
GND
EN
BIAS
PG
IN
IN
Thermal
Pad
1
2
3
4
5
10
9
8
7
6
IN
IN
IN
PG
BIAS
OUT
NC
FB
IN
NC
NC
NC
OUT
EN
GND
NC
NC
SS
GND
20
19
18
17
16
1514131211
12345
6
7
8
9
10
OUT
OUT
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2
Figure 2. Simplified Schematic Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Name QFN20 DFN10 Description
IN 5−8 1, 2 Unregulated input to the device.
EN 11 5Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the
regulator into shutdown mode. This pin must not be left floating.
SS 15 7 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this
pin is left floating, the regulator output soft-start ramp time is typically 200 ms.
BIAS 10 4 Bias input voltage for error amplifier, reference, and internal control circuits.
PG 9 3 Power-Good (PG) is an open-drain, active-high output that indicates the status of
VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When VOUT is below this threshold the pin is driven to a
low-impedance state. A pull-up resistor from 10 kW to 1 MW should be connected from
this pin to a supply up to 5.5 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output monitoring is not necessary.
FB 16 8 This pin is the feedback connection to the center tap of an external resistor divider
network that sets the output voltage. This pin must not be left floating.
OUT 1, 18−20 9, 10 Regulated output voltage. A small capacitor (total typical capacitance ≥2.2 mF,
ceramic) is needed from this pin to ground to assure stability.
NC 2−4, 13, 14, 17 N/A No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
GND 12 6 Ground
PAD/TAB Should be soldered to the ground plane for increased thermal performance.
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Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Input Voltage Range VIN −0.3 to +6 V
Input Voltage Range VBIAS −0.3 to +6 V
Enable Voltage Range VEN −0.3 to +6 V
Power−Good Voltage Range VPG −0.3 to +6 V
PG Sink Current IPG 0 to +1.5 mA
SS Pin Voltage Range VSS −0.3 to +6 V
Feedback Pin Voltage Range VFB −0.3 to +6 V
Output Voltage Range VOUT −0.3 to (VIN + 0.3) ≤ 6 V
Maximum Output Current IOUT Internally Limited
Output Short Circuit Duration Indefinite
Continuous Total Power Dissipation PDSee Thermal Characteristics Table and Formula
Maximum Junction Temperature TJMAX +150 °C
Storage Junction Temperature Range TSTG −55 to +150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V
ESD Capability, Machine Model (Note 2) ESDMM 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latch-up Current Maximum Rating tested per JEDEC standard: JESD78.
Table 3. THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, QFN20, 5x5, 0.65P package
Thermal Resistance, Junction−to−Ambient (Note 5) RqJA 30.5 °C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 6) RqJC 4.1 °C/W
Thermal Characteristics, DFN10, 3x3, 0.5P package
Thermal Resistance, Junction−to−Ambient (Note 5) RqJA 41.5 °C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 6) RqJC 6.6 °C/W
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following
assumptions are used in the simulations:
This data was generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
JEDEC51.7 guidelines.
− QFN20: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated.
− QFN20: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
− DFN10: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. Vias are 0.3 mm diameter, plated.
− DFN10: Each of top and bottom copper layers are assumed to have thermal conductivity representing 20% copper coverage.
5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
6. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7)
Rating Symbol Min Max Unit
Input Voltage VIN VOUT +V
DO 5.5 V
Bias Voltage VBIAS 2.7 5.5 V
Junction Temperature TJ−40 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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Table 5. ELECTRICAL CHARACTERISTICS (At VEN = 1.1 V, VIN =V
OUT + 0.3 V, CBIAS = 0.1 mF, CSS = 1 nF, CIN =C
OUT =10mF,
IOUT = 50 mA, VBIAS = 5.0 V, TJ= −40°C to +125°C, unless otherwise noted. Typical values are at TJ= +25°C.)
Symbol Parameter Test Conditions Min Typ Max Unit
VIN Input Voltage Range VOUT +V
DO − 5.5 V
VBIAS Bias Pin Voltage Range 2.7 − 5.5 V
UVLO Undervoltage Lock-out VBIAS Rising
Hysteresis −
−1.6
0.4 −
−V
VREF Internal Reference (Adj.) TJ= +25°C 0.796 0.8 0.804 V
VOUT Output Voltage Range VIN =5V, I
OUT = 1.5 A VREF − 3.6 V
Accuracy (Note 1) 2.97 V < VBIAS < 5.5 V,
50 mA < IOUT < 1.5 A −2 ±0.5 +2 %
VOUT/VIN Line Regulation VOUT (NOM) + 0.3 < VIN < 5.5 V − 0.03 − %/V
VOUT/IOUT Load Regulation 50 mA < IOUT < 1.5 A − 0.09 − %/A
VDO VIN Dropout Voltage (Note 2) IOUT = 1.5 A,
VBIAS −V
OUT (NOM) ≥3.25 V (Note 3) − 60 165 mV
VBIAS Dropout Voltage (Note 2) IOUT = 1.5 A, VIN =V
BIAS − 1.31 1.6 V
ICL Current Limit VOUT = 80% ×VOUT (NOM) 2.0 − 5.5 A
IBIAS Bias Pin Current − 1 2 mA
ISHDN Shutdown Supply Current (IGND) VEN ≤0.4 V − 1 50 mA
IFB Feedback Pin Current −1 0.15 1 mA
PSRR Power-Supply Rejection
(VIN to VOUT)1 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V − 60 − dB
300 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V − 30 −
Power-Supply Rejection
(VBIAS to VOUT)1 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V − 50 − dB
300 kHz, IOUT = 1.5 A, VIN = 1.8 V,
VOUT = 1.5 V − 30 −
Noise Output Noise Voltage 100 Hz to 100 kHz, IOUT = 1.5 A − 25 ×VOUT −mVrms
tSTRT Minimum Startup Time RLOAD for IOUT = 1.0 A, CSS = open − 200 − ms
ISS Soft-Start Charging Current VSS = 0.4 V − 0.44 − mA
VEN, HI Enable Input High Level 1.1 − 5.5 V
VEN, LO Enable Input Low Level 0 − 0.4 V
VEN, HYS Enable Pin Hysteresis − 50 − mV
VEN, DG Enable Pin Deglitch Time − 20 − ms
IEN Enable Pin Current VEN =5V − 0.1 1 mA
VIT PG Trip Threshold VOUT Decreasing 85 90 94 %VOUT
VHYS PG Trip Hysteresis − 3 − %VOUT
VPG, LO PG Output Low Voltage IPG = 1 mA (Sinking), VOUT <VIT − − 0.3 V
IPG, LKG PG Leakage Current VPG = 5.25 V, VOUT >V
IT − 0.1 1 mA
TSD Thermal Shutdown Temperature Shutdown, Temperature Increasing
Reset, Temperature Decreasing −
−+165
+140 −
−°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Adjustable devices tested at VREF; external resistor tolerance is not taken into account.
2. Dropout is defined as the voltage from the input to VOUT when VOUT is 3% below nominal.
3. 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.
Table 6. ORDERING INFORMATION
Device Output
Current Output
Voltage Junction
Temperature Range Package Shipping†
NCP59748MN1ADJTBG 1.5 A ADJ −40°C to +125°C DFN10 3000 / Tape & Reel
NCP59748MN2ADJTBG 1.5 A ADJ −40°C to +125°C QFN20 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP59748
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN,
CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted.
Figure 3. VIN Line Regulation Figure 4. VBIAS Line Regulation
VIN − VOUT (V) VBIAS − VOUT (V)
4.54.03.02.01.51.00.50
−0.20
−0.15
−0.10
−0.05
0
0.10
0.15
0.20
3.53.0 4.02.52.01.51.00.5
−0.5
−0.4
−0.2
−0.1
0
0.2
0.4
0.5
Figure 5. Load Regulation Figure 6. Load Regulation
IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (A)
50403020100
−0.5
−0.4
−0.2
−0.1
0
0.2
0.3
0.5
1.51.00.50
−0.5
−0.4
−0.3
−0.1
0.1
0.2
0.4
0.5
Figure 7. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 8. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
IOUT, OUTPUT CURRENT (A) VBIAS − VOUT (V)
1.51.00.50
0
10
20
30
40
50
60
4.03.53.02.52.01.51.00.5
0
20
40
80
100
140
180
200
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
2.5 3.5 5.0
0.05
−0.3
0.1
0.3
+125°C
+25°C
−40°C+125°C
+25°C
−40°C
−0.3
0.1
0.4
+125°C
+25°C
−40°C
−0.2
0
0.3 +125°C
+25°C
−40°C
+125°C
+25°C
−40°C
4.5
60
120
160
+125°C
+25°C
−40°C
IOUT = 1.5 A
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN,
CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted.
Figure 9. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
Figure 10. VBIAS Dropout Voltage vs. IOUT and
Temperature TJ
VBIAS − VOUT (V) IOUT, OUTPUT CURRENT (A)
4.03.53.02.52.01.51.00.5
0
20
60
80
120
140
180
200
1.51.00.50
600
700
800
900
1000
1100
1200
Figure 11. BIAS Pin Current vs. IOUT and
Temperature TJ
Figure 12. BIAS Pin Current vs. VBIAS and
Temperature TJ
IOUT, OUTPUT CURRENT (A) VBIAS (V)
1.51.00.50
0
200
600
800
1200
1400
1600
2000
5.04.54.0 5.53.53.02.52.0
0
200
600
800
1000
1400
1800
2000
Figure 13. Soft Start Charging Current ISS vs.
Temperature TJ
Figure 14. L−level PG Voltage vs. Current
TJ, JUNCTION TEMPERATURE (°C) IPG, PG PIN CURRENT (mA)
10075 12550250−25−50
0.300
0.325
0.350
0.375
0.400
0.450
0.475
0.500
121086420
0
0.1
0.3
0.4
0.5
0.7
0.9
1.0
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
IBIAS (mA)
IBIAS (mA)
ISS (mA)
VPG,LO, L−LEVEL PG VOLTAGE (V)
4.5
+125°C
+25°C
−40°C
IOUT = 0.5 A
40
100
160
VDO (VBIAS − VOUT) DROPOUT VOLTAGE (mV)
+125°C
+25°C
−40°C
400
1000
1800
+125°C+25°C
−40°C
400
1200
1600
+125°C
+25°C
−40°C
0.425
0.2
0.6
0.8
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN,
CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted.
Figure 15. Current Limit vs. (VBIAS − VOUT)
VBIAS − VOUT (V)
4.54.03.02.51.51.00.50
0
0.5
1.5
2.0
2.5
3.5
4.0
4.5
ICL, CURRENT LIMIT (A)
+125°C
+25°C
−40°C
2.0 3.5 5.0
1.0
3.0
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APPLICATIONS INFORMATION
The NCP59748 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from VIN voltage. All the low current internal
controll circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike a PMOS topology
devices, the output capacitor has reduced impact on loop
stability. Vin to Vout operating voltage difference can be
very low compared with standard PMOS regulators in very
low Vin applications.
The NCP59748 offers programmable smooth monotonic
start-up. The controlled voltage rising limits the inrush
current what is advantageous in applications with large
capacitive loads. The Voltage Controlled Soft−Start timing
is programmable by external Css capacitor value.
The Enable (EN) input is equipped with internal
hysteresis and deglitch filter.
Open Dr a i n t y p e Power Good (PG) output is available for
Vout monitoring and sequencing of other devices.
NCP58748 is a Adjustable linear regulator. The required
Output voltage can be adjusted by two external resistors.
Typical application schematics is shown in Figure 16.
Figure 16. Typical Application Schematics
VOUT +0.8 ǒ1)R1ńR2Ǔ
Dropout Voltage
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) when VOUT starts to decrease by
percents specified in the Electrical Characteristics table.
VBIAS is high enough, specific value is published in the
Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) when VIN and VBIAS pins are
joined together and VOUT starts to decrease.
Input and Output Capacitors
The device is designed to be stable for all available types
and values of output capacitors ≥ 2.2 mF. The device is also
stable with multiple capacitors in parallel, which can be of
any type or value.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
example), the recommended CIN and CBIAS value is 1 mF or
greater. Ceramic or other low ESR capacitors are
recommended. For the best performance all the capacitors
should be connected to the NCP59748 respective pins
directly in the device PCB copper layer, not through vias
having not negligible impedance.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table i n this data sheet. If the enable function is not to be used
then the pin should be connected to VIN or VBIAS.
The NCP59748 device is equipped with Output Active
Discharge transistor that is pulling the output to GND
through a n 1.2 kW (typ.) resistor when the device is disabled.
To get the full functionality of Soft−Start, it is
recommended t o turn on the VIN and VBIAS supply voltages
first and activate the Enable pin no sooner than VIN and
VBIAS are on their nominal levels.
Output Noise
When the NCP59748 device reaches the end of the
Soft−Start cycle, the Soft Start capacitor is switched to serve
as a Noise filtering capacitor.
Output Voltage Adjust
The output voltage can be adjusted from 0.8 V to 3.6 V
using resistors divider between the output and the FB input.
Recommended resistor values for frequently used voltages
can be found in the Table 7.
Programmable Soft−Start
The Soft-Start ramp time depends on the Soft−Start
charging current ISS, Soft-Start capacitor value CSS and
internal reference voltage VREF.
The Soft–Start time can be calculated using following
equations:
tss = CSS x (VREF / ISS) [s, F,V,A]
or in more practical units
tSS = CSS x 0.8V / 0.44 = CSS x 1.82
where
tss = Soft−Start time in miliseconds
CSS = Soft−Start capacitor value in nano Farads
Capacitor values for frequently used Soft-Start times can be
found in the Table 8.
The maximal recommended value of CSS capacitor is
15 nF. For higher CSS values the capacitor full discharging
before new Soft-Start cycle is not guaranteed.
Power Good
Power−Good (PG) is an open−drain, active−high output
that indicates the status of VOUT. When VOUT exceeds the
PG trip threshold, the PG pin goes into a high−impedance
state. When VOUT is below this threshold the pin is driven
to a low−impedance state. A pull−up resistor from 10 kW to
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1 MW should be connected from this pin to a supply up to
5.5 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output
monitoring is not necessary.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short. The
response time of this protection is in the range of
microseconds.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns of f. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Table 7. RESISTOR VALUES FOR PROGRAMMING
THE OUTPUT VOLTAGE
VOUT (V) R1 (kW) R2 (kW)
0.8 Short Open
0.9 0.619 4.99
1.0 1.13 4.53
1.05 1.37 4.33
1.1 1.87 4.99
1.2 2.49 4.99
1.5 4.12 4.75
1.8 3.57 2.87
2.5 3.57 1.69
3.3 3.57 1.15
NOTE: VOUT = 0.8 x (1 + R1/R2)
Resistors in the table are standard 1% types
Table 8. CAPACITOR VALUES FOR PROGRAMMING
THE SOFT−START TIME
Soft−Start Time CSS
0.2 ms Open
0.5 ms 270 pF
1 ms 560 pF
5 ms 2.7 nF
10 ms 5.6 nF
18 ms 10 nF
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PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE E
ÇÇÇ
ÇÇÇ
ÇÇÇ
10X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
15
10 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B
ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WET-
TABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON
SIDE VIEW OF PACKAGE.
B
A
0.15 CTOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN ONE
REFERENCE
0.10 C
0.08 C
(A3)
C
10X
10X
0.10 C
0.05 C
A B
NOTE 3
K
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 2.40 2.60
E3.00 BSC
E2 1.70 1.90
e0.50 BSC
L0.35 0.45
L1 0.00 0.03
DET AIL A
K0.19 TYP
2X
2X
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ÉÉ
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
ÇÇ
A1
A3
2.64
1.90
0.50
0.55
10X
3.30
0.30
10X
DIMENSIONS: MILLIMETERS
PITCH
PACKAGE
OUTLINE
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ALTERNATE B−2ALTERNATE B−1
AL TERNATE A−2AL TERNATE A−1
DETAIL B
WETTABLE FLANK OPTION
CONSTRUCTION
A1
A3
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PACKAGE DIMENSIONS
QFN20 5x5, 0.65P
CASE 485DB
ISSUE O
SEATING
0.15 C
(A3) A
A1
D2
b
1
11
16
E2
20X
6L
20X
BOTTOM VIEW
DET AIL A
TOP VIEW
SIDE VIEW
DAB
E
0.15 C
ÉÉ
PIN ONE
REFERENCE
0.10 C
0.08 C
C
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. OPTIONAL FEATURES.
PLANE
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 −−− 0.05
A3 0.20 REF
b0.25 0.35
D5.00 BSC
D2 3.05 3.25
E5.00 BSC
E2
e0.65 BSC
L0.45 0.65
3.05 3.25
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
3.30
0.40
3.30
20X
0.78
20X
5.30
5.30
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DETAIL B
ALTERNATE
CONSTRUCTION
NOTE 4
DETAIL B
NOTE 3
L1 −−− 0.15
PITCH DIMENSIONS: MILLIMETERS
A
M
0.10 BC
M
0.05 C
A
M
0.10 B
C
PACKAGE
OUTLINE
RECOMMENDED
A
M
0.10 B
C
NOTE 5
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