Altera Corporation 17
Nios Embedded Processor Development Board
SW2: Reset
When SW3 is pressed, a logic-0 value is driven to U7, the power-on reset
controller. Pressing SW3 is equivalent to a power-on reset. When SW3 is
pressed (or when the board is power-cycled), the configuration controller
will load the APEX device from flash memory. See “Configuration
Controller” on page 14 for more information.
When the development board is delivered from the factory, the APEX
device will be configured with the 32-bit reference design at power-up (or
when SW3 is pressed). The reference design will then begin executing the
GERMS monitor, a serial debug/download utility.
SW3: Clear
When SW2 is pressed, a logic-0 is driven onto the APEX devices'
DEV_CLRn pin (and user I/O F12). The result of pressing SW2 depends
on how the APEX device is currently configured.
The pre-loaded Nios reference design treats SW2 as a CPU-reset pin: The
reference Nios CPU will reset and start executing code from its
boot-address (0) when SW2 is pressed.
Power-supply
circuitry
The Nios development board runs from a 9-V, unregulated, center-
negative input. On-board circuitry generates 5-V, 3.3-V, and 1.8-V
regulated power levels.
■The 1.8-V supply is used only for the APEX device core power source
and it is not available on any connector or header.
■The 3.3-V supply is used as the power source for all APEX device I/O
pins. The 3.3-V supply is also available to daughter cards or other
devices plugged-in to any of the expansion connectors, including the
PMC connectors and the SDRAM SODIMM socket. The total load
from all externally-connected 3.3-V devices may not exceed 500 mA.
■The 5-V supply is presented on Pin2 of JP12 for use by any devices
plugged-in to the 5-V-tolerant expansion connectors. The total load
may not exceed 50 mA.
Clock Circuitry The Nios development board includes a 33.333MHz free-running
oscillator and a zero-skew, point-to-point clock distribution network that
drives both the APEX device and pins on the expansion connectors, PMC
connectors, and SODIMM connector. The zero-skew buffer distributes
both the free-running 33MHz clock and the clock-output from one of the
APEX's device internal PLLs (CLKLK_OUT1).