®
Includes
MAX 7000AE
Alt er a Cor pora t ion 1
MAX 7000A
Programmable Logic
Device
October 2002, ver . 4.3 Data Sheet
DS-M7000A-4.3
Features... ■High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
■3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
■Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
■Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
■Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■Pin-compatible with the popular 5.0-V MAX 7000S devices
■High-density PLDs ranging from 600 to 10,000 usable gates
■Extended temperature range
fFor information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
2Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
...and More
Features
■4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■MultiVoltTM I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
■Supports hot-socketing in MAX 7000AE devices
■Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
■PCI-compatible
■Bus-friendly architecture, including programmable slew-rate control
■Open-drain output option
■Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
■Programmable power-up states for macrocell registers in
MAX 7000AE devices
■Programmable power-saving mode for 50% or greater power
reduction in each macrocell
■Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■Programmable security bit for protection of proprietary designs
■6 to 10 pin- or logic-driven output enable signals
■Two global clock signals with optional inversion
■Enhanced interconnect resources for improved routability
■Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
■Programmable output slew-rate control
■Programmable ground pins
Table 1. MAX 7000A Device Features
Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE
Usable gat es 600 1,2 50 2,500 5,00 0 10,000
Macrocells 32 64 128 256 512
Logic arra y block s 2 4 8 16 32
Maximum user I/O
pins 36 68 100 164 212
tPD (ns) 4.5 4.5 5.0 5.5 7.5
tSU (ns) 2.9 2.8 3.3 3.9 5.6
tFSU (ns) 2.5 2.5 2.5 2.5 3.0
tCO1 (ns) 3.0 3.1 3.4 3.5 4.7
fCNT (MHz) 227.3 222. 2 192.3 172. 4 116.3
Altera Corporation 3
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
■Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
■Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
■Programming support with Altera’s Master Programming Unit
(MPU), MasterBlasterTM serial/universal serial bus (USB)
communications cable, ByteBlasterMVTM parallel port download
cable, and BitBlasterTM serial download cable, as well as
programming hardware from third-party manufacturers and any
JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector
Format File- (.svf) capable in-circuit tester
General
Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5,
-6, -7, and some -10 speed grades are compatible with the timing
requirements for 33 MHz operation of the PCI Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.
Table 2. MAX 7000A Speed Grades
Device Speed Grade
-4 -5 -6 -7 -10 -12
EPM7032AE vvv
EPM7064AE vvv
EPM7128A vvvv
EPM7128AE vvv
EPM7256A vvvv
EPM7256AE vvv
EPM7512AE vvv
4Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See Table 3 and Table 4.
Notes to tables:
(1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(2) All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more
details.
(3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details.
Table 3. MAX 7000A Maximum User I/O Pins Note (1)
Device 44-Pin PLCC 44-Pin TQFP 49-Pin Ultra
FineLine
BGA (2)
84-Pin PLCC 100-Pin
TQFP
100-Pin
FineLine
BGA (3)
EPM7032AE 36 36
EPM7064AE 36 36 41 68 68
EPM7128A 68 84 84
EPM7128AE 68 84 84
EPM7256A 84
EPM7256AE 84 84
EPM7512AE
Table 4. MAX 7000A Maximum User I/O Pins Note (1)
Device 144-Pin TQFP 169-Pin Ultra
FineLine BGA (2)
208-Pin PQFP 256-Pin BGA 256-Pin FineLine
BGA (3)
EPM7032AE
EPM7064AE
EPM7128A 100 100
EPM7128AE 100 100 100
EPM7256A 120 164 164
EPM7256AE 120 164 164
EPM7512AE 120 176 212 212
Altera Corporation 5
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms, providing up to 32 product terms
per macrocell.
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX-workstation-based EDA tools. The
software runs on Windows-based PCs, as well as Sun SPARCstation, and
HP 9000 Series 700/800 workstations.
fFor more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and the
Quartus Programmable Logic Development System & Software Data Sheet.
6Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Functional
Description
The MAX 7000A architecture includes the following elements:
■Logic array blocks (LABs)
■Macrocells
■Expander product terms (shareable and parallel)
■Programmable interconnect array
■I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.
Altera Corporation 7
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 1. MAX 7000A Device Block Diagram
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.
EPM7512AE devices have 10 output enables.
Logic Array Blocks
The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■36 signals from the PIA that are used for general logic inputs
■Global controls that are used for secondary register functions
■Direct input paths from I/O pins to the registers that are used for fast
setup times
6
6
INPUT/GCLRn
6 or 10 Output Enables
(1)
6 or 10 Output Enables
(1)
16
36 36
16
I/O
Control
Block
LAB C LAB D
I/O
Control
Block
6
16
36 36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
Macrocells
17 to 32
Macrocells
33 to 48 Macrocells
49 to 64
8Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Macrocells
MAX 7000A macrocells can be individually configured for either
sequential or combinatorial logic operation. The macrocells consist of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows a MAX 7000A macrocell.
Figure 2. MAX 7000A Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
■Shareable expanders, which are inverted product terms that are fed
back into the logic array
■Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
Product-
Term
Select
Matrix
36 Signals
from PIA 16 Expander
Product Terms
LAB Local Array
Parallel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D/T Q
ENA
Register
Bypass To I/O
Control
Block
From
I/O pin
To PIA
Programmable
Register
Fast Input
Select
VCC
Altera Corporation 9
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera software then selects the most efficient flipflop operation for each
registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■Global clock signal. This mode achieves the fastest clock-to-output
performance.
■Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
■Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement of
either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry. Upon power-up, each register in EPM7128A and
EPM7256A devices are set to a low state.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
10 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Expander Product Terms
Although most logic functions can be implemented with the five product
terms available in each macrocell, more complex logic functions require
additional product terms. Another macrocell can be used to supply the
required logic resources. However, the MAX 7000A architecture also
offers both shareable and parallel expander product terms that provide
additional product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest possible
logic resources to obtain the fastest possible speed.
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (tSEXP) is incurred when
shareable expanders are used. Figure 3 shows how shareable expanders
can feed multiple macrocells.
Figure 3. MAX 7000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Macrocell
Product-Term
Logic
Product-Term Select Matrix
Macrocell
Product-Term
Logic
36 Signals
from PIA 16 Shared
Expanders
Altera Corporation 11
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
The compiler can allocate up to three sets of up to five parallel expanders
to the macrocells that require additional product terms. Each set of five
parallel expanders incurs a small, incremental timing delay (tPEXP). For
example, if a macrocell requires 14 product terms, the compiler uses the
five dedicated product terms within the macrocell and allocates two sets
of parallel expanders; the first set includes five product terms, and the
second set includes four product terms, increasing the total delay by
2×tPEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of eight, the lowest-numbered macrocell
can only lend parallel expanders, and the highest-numbered macrocell
can only borrow them. Figure 4 shows how parallel expanders can be
borrowed from a neighboring macrocell.
12 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 4. MAX 7000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a 2-input AND gate,
which selects a PIA signal to drive into the LAB.
Preset
Clock
Clear
Product-
Term
Select
Matrix
Preset
Clock
Clear
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
From
Previous
Macrocell
To Next
Macrocell
Macrocell
Product-
Term Logic
36 Signals
from PIA 16 Shared
Expanders
Altera Corporation 13
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 5. MAX 7000A PIA Routing
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
To LAB
PIA Signals
14 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 6. I/O Control Block of MAX 7000A Devices
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 7000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
From
Macrocell
Fast Input to
Macrocell
Register
Slew-Rate Control
To PIA
To Other I/O Pins
6 or 10 Global
Output Enable Signals (1)
PIA
VCC
Open-Drain Output
OE Select Multiplexer
GND
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable
signals. EPM7512AE devices have 10 output enable signals.
Altera Corporation 15
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
SameFrame
Pin-Outs
MAX 7000A devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EPM7128AE device in a 100-pin
FineLine BGA package to an EPM7512AE device in a 256-pin
FineLine BGA package.
The Altera design software provides support to design PCBs with
SameFrame pin-out devices. Devices can be defined for present and future
use. The software generates pin-outs describing how to lay out a board to
take advantage of this migration (see Figure 7).
Figure 7. SameFrame Pin-Out Example
Designed for 256-Pin FineLine BGA Package
Printed Circuit Board
100-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
100-Pin
FineLine
BGA
256-Pin
FineLine
BGA
16 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
In-System
Programma-
bility
MAX 7000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient
iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 kΩ.
MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is only available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a PCB with standard pick-and-place equipment before they are
programmed. MAX 7000A devices can be programmed by downloading
the information via in-circuit testers, embedded processors, the Altera
MasterBlaster serial/USB communications cable, ByteBlasterMV parallel
port download cable, and BitBlaster serial download cable. Programming
the devices after they are placed on the board eliminates lead damage on
high-pin-count packages (e.g., QFP packages) due to device handling.
MAX 7000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. A constant algorithm uses a pre-
defined (non-adaptive) programming sequence that does not take
advantage of adaptive algorithm programming time improvements.
Some in-circuit testers cannot program using an adaptive algorithm.
Therefore, a constant algorithm must be used. MAX 7000AE devices can
be programmed with either an adaptive or constant (non-adaptive)
algorithm. EPM7128A and EPM7256A device can only be programmed
with an adaptive algorithm; users programming these two devices on
platforms that cannot use an adaptive algorithm should use EPM7128AE
and EPM7256AE devices.
The Jam Standard Test and Programming Language (STAPL), JEDEC
standard JESD 71, can be used to program MAX 7000A devices with in-
circuit testers, PCs, or embedded processors.
Altera Corporation 17
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
fFor more information on using the Jam STAPL language, see Application
Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor)
and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded
Processor).
ISP circuitry in MAX 7000AE devices is compliant with the IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming
with External
Hardware
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checks to ensure adequate
electrical contact between the adapter and the device.
fFor more information, see the Altera Programming Hardware Data Sheet.
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices.
fFor more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1. Table 5 describes the JTAG instructions supported by MAX 7000A
devices. The pin-out tables, available from the Altera web site
(http://www.altera.com), show the location of the JTAG control pins for
each device. If the JTAG interface is not required, the JTAG pins are
available as user I/O pins.
18 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 5. MAX 7000A JTAG Instructions
JTAG Instruction Description
SAM PLE/PRELOAD Allows a sn aps hot of signa ls at the dev ice pins to be capt ured and examined during
norma l dev ice operat ion, and permits an init ial data pattern ou tp ut at the dev ice pins
EXT EST Allows th e ex ter nal ci rcu itry and board-lev el inte rc onnections to be test ed by forcing a
test patt ern at the ou tpu t pin s and cap tur ing te st res ult s at the input pins
BYPASS Place s the 1-bit by pas s regis ter between the TDI and TDO pins, whic h allow s the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
US ER CO D E Selec ts the 32-bit US ER CO D E regis t er and places it betwee n the TDI and TDO pins ,
allowing the USERCODE value to be shifted out of TDO. The USERCODE instruction is
availa ble fo r MA X 7000AE devices only
UESCODE These instructions select the user electronic signature (UESCODE) and allow the
UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A
and EPM7256A devices only.
ISP Instructions These instructions are used when programming MAX 7000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam
STAP L File , JBC File , or SVF F ile via an emb edded process or or te st equipment.
Altera Corporation 19
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
The instruction register length of MAX 7000A devices is 10 bits. The user
electronic signature (UES) register length in MAX 7000A devices is 16 bits.
The MAX 7000AE USERCODE register length is 32 bits. Tables 6 and 7
show the boundary-scan register length and device IDCODE information
for MAX 7000A devices.
Notes:
(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.
fSee Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices) for more information on JTAG BST.
Table 6. MAX 7000A Boundary-Scan Register Length
Device Boundary-Scan Register Length
EPM7032AE 96
EPM7064AE 192
EPM7128A 288
EPM7128AE 288
EPM7256A 480
EPM7256AE 480
EPM7512AE 624
Table 7. 32-Bit MAX 7000A Device IDCODE Not e (1)
Device IDCODE (32 Bits)
Version
(4 Bits)
Part Number (16 Bits) Manufacturer’s
Identity (11 Bits)
1 (1 Bit)
(2)
EPM7032AE 0001 0111 0000 0011 0010 00001101110 1
EPM7064AE 0001 0111 0000 0110 0100 00001101110 1
EPM7128A 0000 0111 0001 0010 1000 00001101110 1
EPM7128AE 0001 0111 0001 0010 1000 00001101110 1
EPM7256A 0000 0111 0010 0101 0110 00001101110 1
EPM7256AE 0001 0111 0010 0101 0110 00001101110 1
EPM7512AE 0001 0111 0101 0001 0010 00001101110 1
20 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 8 shows timing information for the JTAG signals.
Figure 8. MAX 7000A JTAG Waveforms
Table 8 shows the JTAG timing parameters and values for MAX 7000A
devices.
Note:
(1) Timing parameters shown in this table apply for all specified VCCIO levels.
Table 8. JTAG Timing Parameters & Values for MAX 7000A Devices No t e (1)
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clo ck high t im e 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port se tu p time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clo ck to outp ut 25 ns
tJPZX JTAG port high impedance t o val id out put 25 ns
tJPXZ JTAG port va lid out put to high im pedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 25 ns
tJSZX Update register high impedance to valid output 25 ns
tJSXZ Update register valid output to high impedance 25 ns
TDO
TCK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
Altera Corporation 21
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Programmable
Speed/Power
Control
MAX 7000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000A
device for either high-speed (i.e., with the Turbo BitTM option turned on)
or low-power operation (i.e., with the Turbo Bit option turned off). As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC,
tEN, tSEXP, tACL, and tCPPW parameters.
Output
Configuration
MAX 7000A device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
The MAX 7000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 7000A devices to connect to systems with
differing supply voltages. MAX 7000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
VCC pins for internal operation and input buffers (VCCINT), and another
set for I/O output drivers (VCCIO).
The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 2.5-V power supply, the output levels are compatible with
2.5-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with VCCIO levels lower than 3.0 V
incur a slightly greater timing delay of tOD2 instead of tOD1. Inputs can
always be driven by 2.5-V, 3.3-V, or 5.0-V signals.
Table 9 describes the MAX 7000A MultiVolt I/O support.
Table 9. MAX 7000A MultiVolt I/O Support
VCCIO Voltage Input Signal (V) Output Signal (V)
2.5 3.3 5.0 2.5 3.3 5.0
2.5 vvvv
3.3 vvv vv
22 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Open-Drain Output Option
MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. This
output can also provide an additional wired-OR plane.
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high
VIH. When the open-drain pin is active, it will drive low. When the pin is
inactive, the resistor will pull up the trace to 5.0 V to meet CMOS VOH
requirements. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor.
Programmable Ground Pins
Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the rising
and falling edges of the output signal.
Altera Corporation 23
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Power
Sequencing &
Hot-Socketing
Because MAX 7000A devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be driven into MAX 7000AE devices before and during power-
up (and power-down) without damaging the device. Additionally,
MAX 7000AE devices do not drive out during power-up. Once operating
conditions are reached, MAX 7000AE devices operate as specified by the
user.
Design Security All MAX 7000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
Generic Testing MAX 7000A devices are fully tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in Figure 9. Test patterns can be used and then
erased during early stages of the production flow.
Figure 9. MAX 7000A AC Test Conditions
V
CC
To Test
System
C1 (includes jig
capacitance)
Device input
rise and fall
times < 2 ns
Device
Output
703 Ω
[521 Ω]
586 Ω
[481 Ω]
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V
outputs. Numbers without brackets are for
3.3-V outputs.
24 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Operating
Conditions
Tables 10 through 13 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for MAX 7000A devices.
Table 10. MAX 7000A Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply vol tag e With res pec t to ground (2) –0.5 4.6 V
VIDC input voltage –2.0 5.75 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temp erat ure No bias –65 150 ° C
TAAmbient temperature Under bias –65 135 ° C
TJJunction temperature BGA, FineLine BGA, PQFP, and
TQFP packages, under bias 135 ° C
Table 11. MAX 7000A Device Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic
and input buffers (3), (13) 3.0 3.6 V
VCCIO Supply vol tag e for outp ut
driver s, 3.3 -V operation (3) 3.0 3.6 V
Supply vol tag e for outp ut
driver s, 2.5 -V operation (3) 2.3 2.7 V
VCCISP Supply voltag e during in-
system programming 3.0 3.6 V
VIInput vo lta ge (4) –0.5 5.75 V
VOOutp ut volt age 0 VCCIO V
TAAmbient temperature Commercial range 0 70 ° C
Industrial range (5) –40 85 ° C
Extended range (5) –40 125 ° C
TJJunct ion te m perat ure Comm erc ial range 0 90 ° C
Industrial range (5) –40 105 ° C
Extended range (5) –40 130 ° C
tRInput ris e time 40 ns
tFInput fa ll time 40 ns
Altera Corporation 25
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 12. MAX 7000A Device DC Operating Conditions Note (6)
Symbol Parameter Conditions Min Max Unit
VIH Hig h-lev el input voltage 1.7 5.75 V
VIL Low -lev el input voltage –0. 5 0.8 V
VOH 3.3 -V high-level TTL ou tpu t
voltage IOH = –8 mA DC, VCCIO = 3.00 V (7) 2.4 V
3.3 -V high-level CMO S out put
voltage IOH = –0.1 mA DC, VCCIO = 3.00 V
(7) VCCIO – 0.2 V
2.5 -V high-level output vol tag e IOH = –100 µA DC, VCCIO = 2.30 V
(7) 2.1 V
IOH = –1 mA DC, V CCIO = 2.30 V (7) 2.0 V
IOH = –2 mA DC, V CCIO = 2.30 V (7) 1.7 V
VOL 3.3-V low-level TTL output
voltage IOL = 8 mA DC, VCCIO = 3.00 V (8) 0.45 V
3.3 -V low -lev el C M OS out put
voltage IOL = 0. 1 m A DC, VCCIO = 3.00 V (8) 0.2 V
2.5 -V low -lev el out put voltage IOL = 100 µA DC, V CCIO = 2.30 V (8) 0.2 V
IOL = 1 mA DC, VCCIO = 2.30 V (8) 0.4 V
IOL = 2 mA DC, VCCIO = 2.30 V (8) 0.7 V
IIInput leakage current VI = –0.5 to 5.5 V (9) –10 10 µA
IOZ Tri-stat e out put off-s t ate
current VI = –0.5 to 5.5 V (9) –10 10 µA
RISP Value of I/O pin pull-up resistor
dur in g in-s yst em pr ogr ammi ng
or duri ng pow er-up
VCCIO = 3.0 to 3.6 V (10) 20 50 kΩ
VCCIO = 2.3 to 2.7 V (10) 30 80 kΩ
VCCIO = 2.3 to 3.6 V (11) 20 74 kΩ
Table 13. MAX 7000A Device Capacitance Note (12)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CI/O I/O pin c apac it anc e VOUT = 0 V, f = 1.0 MHz 8 pF
26 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
(3) For EPM7128A and EPM7256A devices only, VCC must rise monotonically.
(4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before
VCCINT and VCCIO are powered.
(5) These devices support in-system programming for –40° to 100° C. For in-system programming support between
–40° and 0° C, contact Altera Applications.
(6) These values are specified under the recommended operating conditions shown in Table 11 on page 24.
(7) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high-level TTL or CMOS output current.
(8) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low-level TTL or CMOS output current.
(9) This value is specified for normal device operation. For MAX 7000AE devices, the maximum leakage current during
power-up is ±300 µA. For EPM7128A and EPM7256A devices, leakage current during power-up is not specified.
(10) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system.
(11) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed
devices during power-up.
(12) Capacitance is measured at 25 °C and is sample-tested only. The OE1 pin (high-voltage pin during programming)
has a maximum capacitance of 20 pF.
(13) The POR time for MAX 7000AE devices (except MAX 7128A and MAX 7256A devices) does not exceed 100 µs. The
sufficient VCCINT voltage level for POR is 3.0 V. The device is fully initialized within the POR time after VCCINT
reaches the sufficient POR voltage level.
Altera Corporation 27
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 10 shows the typical output drive characteristics of MAX 7000A
devices.
Figure 10. Output Drive Characteristics of MAX 7000A Devices
Timing Model MAX 7000A device timing can be analyzed with the Altera software, a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 11. MAX 7000A
devices have predictable internal delays that enable the designer to
determine the worst-case timing of any design. The software provides
timing simulation, point-to-point delay prediction, and detailed timing
analysis for device-wide performance evaluation.
VO Output Voltage (V)
1234
0
0
50
IOL
IOH
VCCINT = 3.3
= 25 C
V
VCCIO = 3.3 V
Temperature
100
150
Typical I
Output
Current (mA)
O
VO Output Voltage (V)
1234
VCCINT = 3.3 V
VCCIO = 2.5 V
IOH
2.5 V3.3 V
Typical I
Output
Current (mA)
O
VO Output Voltage (V)
1234
5
IOH
VCCINT = 3.3 V
VCCIO = 3.3 V
Typical I
Output
Current (mA)
O
VO Output Voltage (V)
1234
VCCINT = 3.3 V
VCCIO = 2.5 V
IOH
T
2.5 V3.3 V
Typical I
Output
Current (mA)
O
EPM7128A & EPM7256A Devices EPM7128A & EPM7256A Devices
00
50
IOL
100
150
00
40
IOL
80
120
0
40
IOL
80
120
O = 25 C
Temperature O
5
MAX 7000AE Devices MAX 7000AE Devices
5
5
= 25 C
emperature O
T = 25 C
emperature O
28 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 11. MAX 7000A Timing Model
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 12 shows the timing relationship
between internal and external delay parameters.
fSee Application Note 94 (Understanding MAX 7000 Timing) for more
information.
Logic Array
Delay
t
LAD
Output
Delay
t
OD3
t
OD2
t
OD1
t
XZ
Z
t
X1
t
ZX2
t
ZX3
Input
Delay
t
IN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
PIA
Delay
t
PIA
Shared
Expander Delay
t
SEXP
Register
Control Delay
t
LAC
t
IC
t
EN
I/O
Delay
t
IO
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Parallel
Expander Delay
t
PEXP
Fast
Input Delay
t
FIN
Altera Corporation 29
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 12. MAX 7000A Switching Waveforms
Combinatorial Mode
Input Pin
I/O Pin
PIA Delay
Shared Expander
Delay
Logic Array
Input
Parallel Expander
Delay
Logic Array
Output
Output Pin
t
IN
t
LAC
, t
LAD
t
PIA
t
OD
t
PEXP
t
IO
t
SEXP
t
COMB
Global Clock Mode
Global
Clock Pin
Global Clock
at Register
Data or Enable
(Logic Array Output)
t
F
t
CH
t
CL
t
R
t
IN
t
GLOB
t
SU
t
H
Array Clock Mode
Input or I/O Pin
Clock into PIA
Clock into
Logic Array
Clock at
Register
Data from
Logic Array
Register to PIA
to Logic Array
Register Output
to Pin
t
F
t
R
t
ACH
t
ACL
t
SU
t
IN
t
IO
t
RD
t
PIA
t
CLR
, t
PRE
t
H
t
PIA
t
IC
t
PIA
t
OD
t
OD
tR & tF < 2 ns. Inputs are
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
30 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Tables 14 through 27 show EPM7032AE, EPM7064AE, EPM7128AE,
EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing
information.
Table 14. EPM7032AE External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-4 -7 -10
Min Max Min Max Min Max
tPD1 Input to non-registered
output C1 = 35 pF (2) 4.5 7.5 10 ns
tPD2 I/O input to non-registered
output C1 = 35 pF (2) 4.5 7.5 10 ns
tSU Global clo ck se tu p time (2) 2.9 4.7 6.3 ns
tHGlobal clo ck hold time (2) 0.0 0.0 0.0 ns
tFSU Global clo ck se tu p time of
fast input 2.5 3.0 3.0 ns
tFH Global clo ck hold time of
fast input 0.0 0.0 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 1.0 3.0 1.0 5.0 1.0 6.7 ns
tCH Global clo ck high time 2.0 3.0 4.0 ns
tCL Global clo ck low time 2.0 3.0 4.0 ns
tASU Array cloc k set up time (2) 1.6 2.5 3.6 ns
tAH Arr ay c l o ck hold time (2) 0.3 0.5 0.5 ns
tACO1 Array cloc k to out put delay C1 = 35 pF (2) 1.0 4.3 1.0 7.2 1.0 9.4 ns
tACH Array cloc k hig h time 2.0 3.0 4.0 ns
tACL Arr ay c l o ck low tim e 2. 0 3.0 4.0 ns
tCPPW Minimum puls e w idt h for
clear and pres et (3) 2.0 3.0 4.0 ns
tCNT Minimum global clock
period (2) 4.4 7.2 9.7 ns
fCNT Maximum internal global
clock frequency (2), (4) 227.3 138.9 103.1 MHz
tACNT Minimum array clock period (2) 4.4 7.2 9.7 ns
fACNT Maximum interna l arr ay
clock frequency (2), (4) 227.3 138.9 103.1 MHz
Altera Corporation 31
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 15. EPM7032AE Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-4 -7 -10
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.7 1.2 1.5 ns
tIO I/O input pad and buffer
delay 0.7 1.2 1.5 ns
tFIN Fas t inpu t de lay 2.3 2.8 3.4 ns
tSEXP Sha red ex pander delay 1.9 3.1 4.0 ns
tPEXP Par allel ex pander delay 0.5 0.8 1.0 ns
tLAD Log ic arr ay delay 1.5 2.5 3.3 ns
tLAC Log ic cont rol array delay 0.6 1.0 1.2 ns
tIOE Internal output enable delay 0.0 0.0 0. 0 ns
tOD1 Ou tpu t buff er and pad
delay, sl ow slew rat e = of f
VCCIO = 3.3 V
C1 = 35 pF 0.8 1.3 1.8 ns
tOD2 Ou tpu t buff er and pad
delay, sl ow slew rat e = of f
VCCIO = 2.5 V
C1 = 35 pF
(5) 1.3 1.8 2.3 ns
tOD3 Ou tpu t buff er and pad
delay, sl ow slew rat e = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.3 6.8 ns
tZX1 Output buffer enable delay,
slow slew rat e = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rat e = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow slew rat e = on
VCCIO = 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buff er dis able delay C1 = 5 pF 4.0 4 .0 5.0 ns
tSU Register se tup time 1.3 2 .0 2.8 ns
tHRegister hold t im e 0.6 1 .0 1.3 ns
tFSU Regis t er se tup time of fast
input 1.0 1.5 1.5 ns
tFH Register hold t im e of fas t
input 1.5 1.5 1.5 ns
tRD Register delay 0.7 1.2 1.5 ns
tCOMB Combina to rial delay 0.6 1.0 1.3 ns
32 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
tIC Array cloc k de lay 1.2 2.0 2.5 ns
tEN Register enable time 0.6 1.0 1.2 ns
tGLOB Global control delay 0.8 1.3 1.9 ns
tPRE Register preset time 1.2 1.9 2.6 ns
tCLR Reg ister clear ti m e 1. 2 1.9 2.6 ns
tPIA PI A delay (2) 0.9 1.5 2.1 ns
tLPA Low -power adde r (6) 2.5 4.0 5.0 ns
Table 15. EPM7032AE Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-4 -7 -10
Min Max Min Max Min Max
Altera Corporation 33
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 16. EPM7064AE External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-4 -7 -10
Min Max Min Max Min Max
tPD1 I nput to non-
regis ter ed out put C 1 = 35 pF
(2) 4.5 7.5 10.0 ns
tPD2 I /O input to no n-
regis ter ed out put C 1 = 35 pF
(2) 4.5 7.5 10.0 ns
tSU Global c loc k setup
time (2) 2.8 4.7 6.2 ns
tHGlobal c loc k hold time (2) 0.0 0.0 0.0 ns
tFSU Global clock setup
time of fast input 2.5 3.0 3.0 ns
tFH Global clock hold time
of fast input 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C 1 = 35 pF 1.0 3.1 1.0 5.1 1. 0 7.0 ns
tCH Global c loc k high time 2.0 3.0 4.0 ns
tCL Global c loc k low time 2.0 3.0 4.0 ns
tASU Array clock se tu p time (2) 1.6 2.6 3.6 ns
tAH Array cl o ck hol d tim e (2) 0.3 0.4 0.6 ns
tACO1 Array clock to outp ut
delay C 1 = 35 pF
(2) 1.0 4.3 1.0 7.2 1.0 9.6 ns
tACH Array clock hig h tim e 2. 0 3 .0 4.0 ns
tACL Array clock low ti me 2.0 3.0 4.0 ns
tCPPW M inim um pulse width
for clear and preset (3) 2.0 3.0 4.0 ns
tCNT M inim um global cloc k
period (2) 4.5 7.4 10.0 ns
fCNT Maximum internal
global clock frequency (2), (4) 222.2 135.1 100.0 MHz
tACNT Minimum array clock
period (2) 4.5 7.4 10.0 ns
fACNT Maximum internal
array clock frequency (2), (4) 222.2 135.1 100.0 MHz
34 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 17. EPM7064AE Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-4 -7 -10
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.6 1.1 1.4 ns
tIO I/O input pa d and buf f er
delay 0.6 1.1 1.4 ns
tFIN Fast inpu t dela y 2.5 3.0 3.7 ns
tSEXP Shared expan der delay 1.8 3.0 3.9 ns
tPEXP Parallel expan der delay 0.4 0.7 0.9 ns
tLAD Logic array delay 1.5 2.5 3.2 ns
tLAC Logic control arra y del ay 0.6 1.0 1.2 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Out put buf f er and pad
delay, slo w slew rat e = off
VCCIO = 3.3 V
C1 = 35 pF 0.8 1.3 1 .8 ns
tOD2 Out put buf f er and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 1.3 1.8 2.3 ns
tOD3 Out put buf f er and pad
delay, slo w slew rat e = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.3 6.8 ns
tZX1 Output buffer enable delay,
slow slew rat e = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rat e = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow slew rat e = on
VCCIO = 3.3 V
C1 = 35 pF 9.0 9.0 10. 0 ns
tXZ Output buf f er dis able delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register setup time 1.3 2.0 2.9 ns
tHRegister hold time 0.6 1.0 1.3 ns
tFSU Regist er se tu p time of fast
input 1.0 1.5 1.5 ns
tFH Re gis ter hold time of fa s t
input 1.5 1.5 1.5 ns
tRD Register delay 0.7 1.2 1.6 ns
tCOMB C om binat orial delay 0. 6 0.9 1.3 ns
Altera Corporation 35
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
tIC Arra y cl o ck del a y 1.2 1.9 2.5 ns
tEN Register enable time 0.6 1.0 1.2 ns
tGLOB Global cont rol delay 1.0 1. 5 2.2 ns
tPRE Register preset time 1.3 2.1 2.9 ns
tCLR Register c lear t im e 1.3 2. 1 2.9 ns
tPIA PIA delay (2) 1.0 1.7 2.3 ns
tLPA Low-pow er adder (6) 3.5 4.0 5.0 ns
Table 17. EPM7064AE Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-4 -7 -10
Min Max Min Max Min Max
36 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 18. EPM7128AE External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -7 -10
Min Max Min Max Min Max
tPD1 Input to non-
registered output C1 = 35 pF
(2) 5.0 7.5 10 ns
tPD2 I/O input to non-
registered output C1 = 35 pF
(2) 5.0 7.5 10 ns
tSU Global clo ck se tu p
time (2) 3.3 4.9 6.6 ns
tHGlobal clo ck hold time (2) 0.0 0.0 0.0 ns
tFSU Global clo ck se tu p
time of fast input 2.5 3.0 3.0 ns
tFH Global clock hold time
of fast input 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C 1 = 35 pF 1.0 3.4 1.0 5.0 1 .0 6.6 ns
tCH Global clo ck high time 2.0 3.0 4 .0 ns
tCL Global clo ck low time 2.0 3. 0 4.0 ns
tASU Array cloc k set up time (2) 1.8 2.8 3.8 ns
tAH Arr ay c l o ck hold time (2) 0.2 0.3 0.4 ns
tACO1 Array cloc k to out put
delay C 1 = 35 pF
(2) 1.0 4.9 1.0 7.1 1.0 9.4 ns
tACH Array cloc k hig h time 2.0 3.0 4.0 ns
tACL Arr ay c l o ck low tim e 2. 0 3. 0 4.0 ns
tCPPW Minimum puls e w idt h
for clear and preset (3) 2.0 3.0 4.0 ns
tCNT Minimum global clock
period (2) 5.2 7.7 10.2 ns
fCNT Maximum interna l
global clock frequency (2), (4) 192.3 129.9 98.0 MHz
tACNT Minimum array clock
period (2) 5.2 7.7 10.2 ns
fACNT Maximum interna l
array cloc k frequency (2), (4) 192.3 129.9 98.0 MHz
Altera Corporation 37
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 19. EPM7128AE Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -7 -10
Min Max Min Max Min Max
tIN Input pad and buf fe r delay 0. 7 1.0 1.4 ns
tIO I/O input pad and buffer
delay 0.7 1.0 1.4 ns
tFIN Fast i n put del a y 2.5 3.0 3.4 ns
tSEXP Shared expander delay 2.0 2.9 3.8 ns
tPEXP Parallel expander delay 0.4 0.7 0.9 ns
tLAD Logic array delay 1.6 2.4 3.1 ns
tLAC Logic control array delay 0.7 1.0 1.3 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.8 1.2 1.6 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 1.3 1.7 2.1 ns
tOD3 Output buffer and pad
delay , slow sle w rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.2 6.6 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow sle w ra te = on
VCCIO = 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register s et up time 1 .4 2.1 2.9 ns
tHRegister hold time 0.6 1.0 1.3 ns
tFSU Register s et up time of fast
input 1.1 1.6 1.6 ns
tFH Register hold time of fast
input 1.4 1.4 1.4 ns
tRD Register delay 0.8 1. 2 1.6 ns
tCOMB Combin at orial delay 0.5 0. 9 1.3 ns
tIC Arra y cl o ck del a y 1.2 1.7 2.2 ns
38 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
tEN Register enable time 0.7 1.0 1.3 ns
tGLOB Global cont rol delay 1.1 1. 6 2.0 ns
tPRE Register preset time 1.4 2.0 2.7 ns
tCLR Register c lear t im e 1.4 2. 0 2.7 ns
tPIA PIA delay (2) 1.4 2.0 2.6 ns
tLPA Low-pow er adder (6) 4.0 4.0 5.0 ns
Table 19. EPM7128AE Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -7 -10
Min Max Min Max Min Max
Altera Corporation 39
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 20. EPM7256AE External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -7 -10
Min Max Min Max Min Max
tPD1 I nput to non-
regis ter ed out put C 1 = 35 pF
(2) 5.5 7.5 10 ns
tPD2 I /O input to no n-
regis ter ed out put C 1 = 35 pF
(2) 5.5 7.5 10 ns
tSU Global c loc k setup
time (2) 3.9 5.2 6.9 ns
tHGlobal c loc k hold time (2) 0.0 0.0 0.0 ns
tFSU Global clock setup
time of fast input 2.5 3.0 3.0 ns
tFH Global clock hold time
of fast input 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C 1 = 35 pF 1.0 3.5 1.0 4.8 1. 0 6.4 ns
tCH Global c loc k high time 2.0 3.0 4.0 ns
tCL Global c loc k low time 2.0 3.0 4.0 ns
tASU Array clock se tu p time (2) 2.0 2.7 3.6 ns
tAH Array cl o ck hol d tim e (2) 0.2 0.3 0.5 ns
tACO1 Array clock to outp ut
delay C 1 = 35 pF
(2) 1.0 5.4 1.0 7.3 1.0 9.7 ns
tACH Array clock hig h tim e 2. 0 3 .0 4.0 ns
tACL Array clock low ti me 2.0 3.0 4.0 ns
tCPPW M inim um pulse width
for clear and preset (3) 2.0 3.0 4.0 ns
tCNT M inim um global cloc k
period (2) 5.8 7.9 10.5 ns
fCNT Maximum internal
global clock frequency (2), (4) 172.4 126.6 95.2 MHz
tACNT Minimum array clock
period (2) 5.8 7.9 10.5 ns
fACNT Maximum internal
array clock frequency (2), (4) 172.4 126.6 95.2 MHz
40 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 21. EPM7256AE Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -7 -10
Min Max Min Max Min Max
tIN Input pad and buf fe r delay 0. 7 0.9 1.2 ns
tIO I/O input pad and buffer
delay 0.7 0.9 1.2 ns
tFIN Fast i n put del a y 2.4 2.9 3.4 ns
tSEXP Shared expander delay 2.1 2.8 3.7 ns
tPEXP Parallel expander delay 0.3 0.5 0.6 ns
tLAD Logic array delay 1.7 2.2 2.8 ns
tLAC Logic control array delay 0.8 1.0 1.3 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.9 1.2 1.6 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 1.4 1.7 2.1 ns
tOD3 Output buffer and pad
delay , slow sle w rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.9 6.2 6.6 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow sle w ra te = on
VCCIO = 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register s et up time 1 .5 2.1 2.9 ns
tHRegister hold time 0.7 0.9 1.2 ns
tFSU Register s et up time of fast
input 1.1 1.6 1.6 ns
tFH Register hold time of fast
input 1.4 1.4 1.4 ns
tRD Register delay 0.9 1. 2 1.6 ns
tCOMB Combin at orial delay 0.5 0. 8 1.2 ns
tIC Arra y cl o ck del a y 1.2 1.6 2.1 ns
Altera Corporation 41
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
tEN Register enable time 0.8 1.0 1.3 ns
tGLOB Global cont rol delay 1.0 1. 5 2.0 ns
tPRE Register preset time 1.6 2.3 3.0 ns
tCLR Register c lear t im e 1.6 2. 3 3.0 ns
tPIA PIA delay (2) 1.7 2.4 3.2 ns
tLPA Low-pow er adder (6) 4.0 4.0 5.0 ns
Table 21. EPM7256AE Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -7 -10
Min Max Min Max Min Max
42 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 22. EPM7512AE External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -12
Min Max Min Max Min Max
tPD1 Input to non-
registered output C1 = 35 pF
(2) 7.5 10.0 12.0 ns
tPD2 I/O input to non-
registered output C1 = 35 pF
(2) 7.5 10.0 12.0 ns
tSU Global clo ck se tu p
time (2) 5.6 7.6 9.1 ns
tHGlobal clo ck hold time (2) 0.0 0.0 0.0 ns
tFSU Global clo ck se tu p
time of fast input 3.0 3.0 3.0 ns
tFH Global clock hold time
of fast input 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C 1 = 35 pF 1.0 4.7 1.0 6.3 1 .0 7.5 ns
tCH Global clo ck high time 3.0 4.0 5 .0 ns
tCL Global clo ck low time 3.0 4. 0 5.0 ns
tASU Array cloc k set up time (2) 2.5 3.5 4.1 ns
tAH Arr ay c l o ck hold time (2) 0.2 0.3 0.4 ns
tACO1 Array cloc k to out put
delay C 1 = 35 pF
(2) 1.0 7.8 1.0 10.4 1.0 12.5 ns
tACH Array cloc k hig h time 3.0 4.0 5.0 ns
tACL Arr ay c l o ck low tim e 3. 0 4. 0 5.0 ns
tCPPW Minimum puls e w idt h
for clear and preset (3) 3.0 4.0 5.0 ns
tCNT Minimum global clock
period (2) 8.6 11.5 13.9 ns
fCNT Maximum interna l
global clock frequency (2), (4) 116.3 87.0 71.9 MHz
tACNT Minimum array clock
period (2) 8.6 11.5 13.9 ns
fACNT Maximum interna l
array cloc k frequency (2), (4) 116.3 87.0 71.9 MHz
Altera Corporation 43
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 23. EPM7512AE Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -12
Min Max Min Max Min Max
tIN Input pad and buf fe r delay 0. 7 0.9 1.0 ns
tIO I/O input pad and buffer
delay 0.7 0.9 1.0 ns
tFIN Fast i n put del a y 3.1 3.6 4.1 ns
tSEXP Shared expander delay 2.7 3.5 4.4 ns
tPEXP Parallel expander delay 0.4 0.5 0.6 ns
tLAD Logic array delay 2.2 2.8 3.5 ns
tLAC Logic control array delay 1.0 1.3 1.7 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 1.0 1.5 1.7 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 1.5 2.0 2.2 ns
tOD3 Output buffer and pad
delay , slow sle w rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 6.0 6.5 6.7 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 5.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.5 5.5 5.5 ns
tZX3 Output buffer enable delay,
slow sle w ra te = on
VCCIO = 3.3 V
C 1 = 35 pF 9.0 10. 0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 5.0 5.0 ns
tSU Register s et up time 2 .1 3.0 3.5 ns
tHRegister hold time 0.6 0.8 1.0 ns
tFSU Register s et up time of fast
input 1.6 1.6 1.6 ns
tFH Register hold time of fast
input 1.4 1.4 1.4 ns
tRD Register delay 1.3 1. 7 2.1 ns
tCOMB Combin at orial delay 0.6 0. 8 1.0 ns
tIC Arra y cl o ck del a y 1.8 2.3 2.9 ns
44 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
tEN Register enable time 1.0 1.3 1.7 ns
tGLOB Global control delay 1.7 2.2 2.7 ns
tPRE Register preset time 1.0 1.4 1.7 ns
tCLR Reg ister clear ti m e 1. 0 1.4 1.7 ns
tPIA PI A delay (2) 3.0 4.0 4.8 ns
tLPA Low -power adde r (6) 4.5 5.0 5.0 ns
Table 23. EPM7512AE Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -12
Min Max Min Max Min Max
Altera Corporation 45
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 24. EPM7128A External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
tPD1 I nput to non-regis te red
output C1 = 35 pF
(2) 6.0 7.5 10.0 12.0 ns
tPD2 I / O input to no n-
regis te red out put C1 = 35 pF
(2) 6.0 7.5 10.0 12.0 ns
tSU Global clock setup time (2) 4.2 5.3 7.0 8.5 ns
tHGlobal clock hold time (2) 0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time
of fast input 2.5 3.0 3.0 3.0 ns
tFH Global clock hold time of
fast input 0.0 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C1 = 35 pF 1.0 3.7 1. 0 4.6 1.0 6.1 1.0 7.3 ns
tCH Global clock high time 3.0 3.0 4.0 5.0 ns
tCL Global clock low time 3.0 3.0 4.0 5.0 ns
tASU Arr a y cl o ck se tu p time (2) 1.9 2.4 3.1 3.8 ns
tAH Array clock hold time (2) 1.5 2.2 3.3 4.3 ns
tACO1 A rray clock to output
delay C1 = 35 pF
(2) 1.0 6.0 1.0 7.5 1.0 10.0 1.0 12.0 ns
tACH Array clock high t im e 3.0 3.0 4. 0 5.0 ns
tACL Arr a y cl o ck low ti me 3. 0 3.0 4. 0 5. 0 ns
tCPPW M inimum pulse width f or
clear and preset (3) 3.0 3.0 4.0 5.0 ns
tCNT M inimum global c loc k
period (2) 6.9 8.6 11.5 13.8 ns
fCNT Maximum internal global
clock frequency (2), (4) 144.9 116.3 87.0 72.5 MHz
tACNT Minimum array clock
period (2) 6.9 8.6 11.5 13.8 ns
fACNT Maximum internal array
clock frequency (2), (4) 144.9 116.3 87 72.5 MHz
46 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 25. EPM7128A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 0.6 0.7 0.9 1.1 ns
tIO I/O input pa d and buf f er
delay 0.6 0.7 0.9 1.1 ns
tFIN Fast inpu t dela y 2.7 3. 1 3.6 3. 9 ns
tSEXP Shared expan der delay 2.5 3.2 4. 3 5.1 ns
tPEXP Parallel expan der delay 0.7 0.8 1. 1 1.3 ns
tLAD Logic array delay 2.4 3. 0 4.1 4. 9 ns
tLAC Logic control arra y de lay 2.4 3.0 4. 1 4.9 ns
tIOE In te rnal out put enable
delay 0.0 0.0 0.0 0.0 ns
tOD1 Out put buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.4 0.6 0.7 0.9 ns
tOD2 Out put buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 0.9 1.1 1.2 1.4 ns
tOD3 Out put buffer and pad
delay, slow slew rate = on
VCCIO = 2. 5 V or 3.3 V
C1 = 35 pF 5.4 5.6 5.7 5.9 ns
tZX1 Out put buffer enab le
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 5.0 ns
tZX2 Out put buffer enab le
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.5 4.5 5.5 5.5 ns
tZX3 Out put buffer enab le
delay, slow slew rate = on
VCCIO = 3.3 V
C1 = 35 pF 9.0 9.0 1 0.0 10.0 ns
tXZ Outpu t buff er dis able
delay C 1 = 5 pF 4.0 4.0 5.0 5.0 ns
tSU Regist er se tup time 1.9 2.4 3. 1 3.8 ns
tHRegist er hold t im e 1.5 2.2 3. 3 4.3 ns
tFSU Register setup time of fast
input 0.81.11.11.1ns
tFH Regist er hold t im e of fas t
input 1.71.91.91.9ns
Altera Corporation 47
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
tRD Register delay 1.7 2. 1 2.8 3.3 ns
tCOMB Combin at orial delay 1.7 2. 1 2.8 3.3 ns
tIC Arra y cl o ck del a y 2.4 3.0 4.1 4.9 ns
tEN Register enable time 2.4 3. 0 4.1 4.9 ns
tGLOB Global cont rol delay 1.0 1. 2 1.7 2.0 ns
tPRE Register preset time 3.1 3.9 5.2 6.2 ns
tCLR Register c lear t im e 3.1 3.9 5 .2 6.2 ns
tPIA PIA delay (2) 0.91.11.51.8ns
tLPA Low-pow er adder (6) 11.0 10.0 10.0 10.0 ns
Table 25. EPM7128A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
48 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Table 26. EPM7256A External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
tPD1 Input to non-registered
output C1 = 35 pF
(2) 6.0 7.5 10.0 12.0 ns
tPD2 I/O input to non-
registered output C1 = 35 pF
(2) 6.0 7.5 10.0 12.0 ns
tSU Global clo ck s etu p time (2) 3.7 4.6 6.2 7.4 ns
tHGlobal clo ck hold time (2) 0.0 0.0 0.0 0.0 ns
tFSU Global clo ck s etu p time
of fast input 2.5 3.0 3.0 3.0 ns
tFH Global clock hold time of
fast input 0.0 0.0 0.0 0.0 ns
tCO1 Global clo ck to outp ut
delay C1 = 35 pF 1.0 3.3 1.0 4.2 1.0 5.5 1.0 6.6 ns
tCH Global clo ck high time 3.0 3 .0 4.0 4.0 ns
tCL Global clo ck low time 3. 0 3.0 4.0 4. 0 ns
tASU Array cloc k set up time (2) 0.8 1.0 1.4 1.6 ns
tAH Arr ay c l o ck hold ti me (2) 1.9 2.7 4.0 5.1 ns
tACO1 Array cloc k to out put
delay C1 = 35 pF
(2) 1.0 6.2 1.0 7.8 1.0 10.3 1.0 12.4 ns
tACH Array cloc k hig h time 3.0 3 .0 4.0 4.0 ns
tACL Array cloc k low ti me 3.0 3.0 4.0 4. 0 ns
tCPPW Minimum puls e w idt h for
clear and pres et (3) 3.0 3.0 4.0 4.0 ns
tCNT Minimum global clock
period (2) 6.4 8.0 10.7 12.8 ns
fCNT Maximu m i n te r n al g l o bal
clock frequency (2), (4) 156.3 125.0 93.5 78.1 MHz
tACNT Minimum array clock
period (2) 6.4 8.0 10.7 12.8 ns
fACNT Maximu m i nt e rna l arr ay
clock frequency (2), (4) 156.3 125.0 93.5 78.1 MHz
Altera Corporation 49
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Table 27. EPM7256A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 0.3 0.4 0.5 0.6 ns
tIO I/O input pad and buffer
delay 0.30.40.50.6ns
tFIN Fast input delay 2.4 3.0 3.4 3.8 ns
tSEXP Shared expander delay 2.8 3.5 4.7 5.6 ns
tPEXP Parallel expander delay 0.5 0.6 0.8 1.0 ns
tLAD Logic array delay 2.5 3.1 4.2 5.0 ns
tLAC Logic control array delay 2.5 3.1 4.2 5.0 ns
tIOE Internal output enable
delay 0.20.30.40.5ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.30.40.50.6ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 0.80.91.01.1ns
tOD3 Output buffer and pad
delay slow slew rate = on
VCCIO = 2.5 V or 3. 3 V
C1 = 35 pF 5.3 5.4 5.5 5.6 ns
tZX1 Output buffer enable
delay slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4 .0 4. 0 5.0 5.0 ns
tZX2 Output buffer enable
delay slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5) 4.54.55.55.5ns
tZX3 Output buffer enable
delay sl o w sle w r at e = on
VCCIO = 2.5 V or 3. 3 V
C1 = 35 pF 9.0 9.0 10.0 10.0 ns
tXZ Output buffer disable
delay C 1 = 5 pF 4.0 4.0 5.0 5.0 ns
tSU Register s et up time 1. 0 1.3 1 .7 2.0 ns
tHRegister hold time 1.7 2. 4 3.7 4.7 ns
tFSU Register setup time of fast
input 1.21.41.41.4ns
tFH Register hold time of fast
input 1.31.61.61.6ns
50 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 11 on page 24. See
Figure 12 for more information on switching waveforms.
(2) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(4) This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) Operating conditions: VCCIO = 2.5 ± 0.2 V for commercial and industrial use.
(6) The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
running in low-power mode.
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000A
devices is calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
The ICCINT value depends on the switching frequency and the application
logic. The ICCINT value is calculated with the following equation:
ICCINT =
(A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC)
tRD Regist er delay 1.6 2. 0 2.7 3. 2 ns
tCOMB C om binatorial delay 1 .6 2.0 2. 7 3.2 ns
tIC Array cloc k de lay 2.7 3. 4 4.5 5. 4 ns
tEN Regist er enable time 2.5 3. 1 4.2 5. 0 ns
tGLOB Global control delay 1.1 1. 4 1.8 2. 2 ns
tPRE R egis t er pres et time 2.3 2.9 3. 8 4.6 ns
tCLR R egis t er cle ar time 2.3 2.9 3.8 4.6 ns
tPIA PI A delay (2) 1.3 1.6 2.1 2.6 ns
tLPA Low -power adde r (6) 11.0 10.0 10.0 10.0 ns
Table 27. EPM7256A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
Altera Corporation 51
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
The parameters in this equation are:
MCTON = Number of macrocells with the Turbo Bit option turned
on, as reported in the MAX+PLUS II Report File (.rpt)
MCDEV = Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported in
the Report File
fMAX = Highest clock frequency to the device
togLC = Average percentage of logic cells toggling at each clock
(typically 12.5%)
A, B, C = Constants, shown in Table 28
This calculation provides an ICC estimate based on typical conditions
using a pattern of a 16-bit, loadable, enabled, up/down counter in each
LAB with no output load. Actual ICC should be verified during operation
because this measurement is sensitive to the actual pattern in the device
and the environmental operating conditions.
Table 28. MAX 7000A ICC Equation Constants
Device A B C
EPM7032AE 0.71 0.30 0.014
EPM7064AE 0.71 0.30 0.014
EPM7128A 0.71 0.30 0.014
EPM7128AE 0.71 0.30 0.014
EPM7256A 0.71 0.30 0.014
EPM7256AE 0.71 0.30 0.014
EPM7512AE 0.71 0.30 0.014
52 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 13 shows the typical supply current versus frequency for
MAX 7000A devices.
Figure 13. ICC vs. Frequency for MAX 7000A Devices (Part 1 of 2)
V
CC
= 3.3 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 1
5
0200
192.3 MHz
108.7 MHz
250
EPM7128A & EPM7128AE
EPM7032AE
V
CC
= 3.3 V
Room Temperature
Frequency (MHz)
30
40
60
70
80
V
CC
= 3.3 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 1
5
0200
222.2 MHz
125.0 MHz
250
050 100 1
5
0200 250
EPM7064AE
10
50
20
10
15
25
30
35
40
High Speed
Low Power
227.3 MHz
144.9 MHz
20
5
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
60
80
120
140
160
20
100
40
Altera Corporation 53
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 13. ICC vs. Frequency for MAX 7000A Devices (Part 2 of 2)
Device
Pin-Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Figures 14 through 23 show the package pin-out diagrams for
MAX 7000A devices.
Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram
Package outlines not drawn to scale.
EPM7256A & EPM7256AE
VCC = 3.3 V
Room Temperature
Frequency (MHz)
Low Power
172.4 MHz
102.0 MHz
50
100
150
200
250
300
High Speed
050 100 150200
Typical I
Active (mA)
CC
EPM7512AE
VCC = 3.3 V
Room Temperature
Frequency (MHz)
Low Power
116.3 MHz
76.3 MHz
100
200
300
400
500
600
020 40 80 100
Typical I
Active (mA)
CC
High Speed
60 120 140
44-Pin PLCC
I/O
I/O
I/O
VCC
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/OE1n
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
EPM7032AE
EPM7064AE
I/O/TDI
I/O
I/O
GND
I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
44-Pin TQFP
Pin 12 Pin 23
Pin 34
Pin 1
I/O
I/O
I/O
VCC
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/OE1n
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O/TDI
I/O
I/O
GND
I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
EPM7032AE
EPM7064AE
54 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 15. 49-Pin Ultra FineLine BGA Package Pin-Out Diagram
Package outlines not drawn to scale.
Figure 16. 84-Pin PLCC Package Pin-Out Diagram
Package outline not drawn to scale.
Indicates
location of
Ball A1
A1 Ball
Pad Corner
A
B
C
D
E
F
G
7654321
EPM7064AE
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GLCRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
EPM7128A
EPM7128AE
I/O
Altera Corporation 55
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 17. 100-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Figure 18. 100-Pin FineLine BGA Package Pin-Out Diagram
Pin 1
Pin 26
Pin 76
Pin 51
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
Indicates
location of
Ball A1
A1 Ball
Pad Corner
A
B
C
D
E
F
G
H
J
K
10987 6543 2 1
EPM7064AE
EPM7128A
EPM7128AE
EPM7256AE
Package outline not drawn to scale.
56 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 19. 144-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Figure 20. 169-Pin Ultra FineLine BGA Package Pin-Out Diagram
Package outline not drawn to scale.
Indicates location
of Pin 1
Pin 1 Pin 109
Pin 73
Pin 37
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Indicates
location of
Ball A1
A1 Ball
Pad Corner
A
B
C
D
E
F
G
H
J
K
10 9 8 7 6 5 4 3 2 1
EPM7064AE
EPM7128A
EPM7128AE
EPM7256AE
Altera Corporation 57
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 21. 208-Pin PQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1 Pin 157
Pin 105Pin 53
EPM7256A
EPM7256AE
EPM7512AE
58 Altera Corporation
MAX 7000A Progra mmable Logic D evi ce D ata Sh eet
Figure 22. 256-Pin BGA Package Pin-Out Diagram
Package outline not drawn to scale.
Indicates
Location of
Ball A1
A1 Ball
Pad Corner
G
F
E
D
C
B
A
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EPM7512AE
U
V
W
Y
17181920
Altera Corporation 59
MAX 7000A Progr ammable Logic D evi ce D ata Sh eet
Figure 23. 256-Pin FineLine BGA Package Pin-Out Diagram
Package outline not drawn to scale.
Revision
History
The information contained in the MAX 7000A Programmable Logic Device
Data Sheet version 4.3 supersedes information published in previous
versions.
Version 4.3
The following changes were made in the MAX 7000A Programmable Logic
Device Data Sheet version 4.3:
■Added extended temperature devices to document
■Updated Table 11.
Version 4.2
The following changes were made in the MAX 7000A Programmable Logic
Device Data Sheet version 4.2:
■Removed Note (1) from Table 2.
■Removed Note (4) from Tables 3 and 4.
Indicates
Location of
Ball A1
A1 Ball
Pad Corner
G
F
E
D
C
B
A
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the
stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their
respective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to
current specifications in accordance with Altera's standard warranty, but reserves the right
to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera Corporation.
Altera customers are advised to obtain the latest version of device specifications before
relying on any published information and before placing orders for products or services.
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Literature Services:
lit_req@altera.com
®
MAX 7000 A Pro gra m mable Logic Devic e Dat a Sheet
60 Altera Corporation
Version 4.1
The following changes were made in the MAX 7000A Programmable Logic
Device Data Sheet version 4.1:
■Updated leakage current information in Table 12.
■Updated Note (9) of Table 12.
■Updated Note (1) of Tables 14 through 27.
