In trodu ction to Cy pres s PLDs
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1990 – Revised October 1995
1
Cypres s PLD Family Features
Cypress Semiconductor’s PLD family offers the user a wide
range of programmable logic solutions that i ncorpor at e lead-
ing-edge circuit d esign t echniques as well as diverse process
tech nology capab il ities. This allows Cypress PLD users to se-
lect PLDs that best suit the needs of their particular hi gh-per-
formance system, regardless of whether speed, power con-
sumption, density, or device flexibility are the critical
requirements imposed by the system .
Cypress offers enhanced-performance industry-standard 20-
and 24-pin device architectures as well as proprietary 28-pin
application-tailored architectures. The range of technologies
of fered includes leading-edge 0.65-micron CMOS EPROM for
high speed, low power, an d high density, 0.65-m icron FLASH
technology for high speed , low power and electrical alterability .
The reprogrammable memory cells us ed by Cypress se rve the
same purpose as the fuse used in most bipolar PLD devices.
Before programming, the AND gates or product te rms are con-
nected via the reprogrammable memory cell to both the true
and complement inputs. When the reprogrammable memory
cell is programmed, the inputs from a gate or product term are
disconnected. Program ming alters the t ransistor threshold of
each cell so that no conduction can occur, which is equivalent
to disconnecti ng the i n put f rom the gate or pr oduct term . Th is
is similar to “blowing” the fuses of BiCMOS or bipolar fusible
devices, which disconnects the input gate from the product
term. Select ive pr ogr amming of e ach of these reprogramma-
ble memory cells enabl e s the specif ic logic function to be im-
plemented by the user.
The programmability of Cypress’s PLDs allows the users to
customize every device in a number of ways to implement their
unique logic req uirements. Using PLDs in pl ace of SSI or MSI
components results in more effective utilization of board
space, reduce d cos t a nd increase d reliability. The flex ibility af-
forded by these PLDs allows the designer to quick ly and effec-
tively implement a number of logic functions ranging from ran-
dom logic gate replacement to complex combinatorial logic
functions.
The PLD family implements the familiar “sum of products” logic
by using a programmab le AND array whos e output terms feed
a fixed OR array. The sum of these can be expressed in a
Boolean transfer function and is limited only by the number of
product term s available in t he AND-O R array. A variety of dif-
ferent sizes and architectures are available. This allows for
more efficient logic optimization by matching inpu t, output, and
product terms to t he desire d a pplication.
PLD Notation
To reduce confusion and to have an orderly way of represent-
ing the complex logic networks, logic diagrams are provided
for the various part types. In order to be useful, Cypress logic
diagrams employ a common logic convention that is easy to
use.
Figure 1
shows the adopted convention. In part (a), an “×”
re pre sents an unprogrammed EPROM cell or intact fuse link
that is used to perform the logical AND operation upon the
input terms. The convention adopted does not imply that the
input terms are connected on the common line that is indicat-
ed. A further extens ion of this convention is shown in part (b),
which shows the implementation of a simple transfer function .
The normal logic re pr esentat ion of the transfer function logic
conventi o n is shown in part ( c).
PLD Circuit Configurations
Cypress PLDs have several different output configurations
that cover a wide spectrum of applications. The available out-
put configurations offer the user the benefits of both lower
pack age counts and reduce d costs when used. This approach
allows designers to select PLDs that best fit their applications.
An example of some of the configurations that are available
are list ed bel ow.
Figure 1. Logic Diagram Conventions
(a)
(b)
(c)
A
B
CASBSC=
ABC
ASBSC
INTRO-1
INTRO-2
INTRO-3
I1
I2
I1I2+I1I2
I1I2+I1I2
I1
I2
2
Programmable I/O
Figure 2
illustrates the programmable I/O offered in the Cy-
press PLD fami ly that all ows product terms to directl y c ontrol
the outputs of the device. One product term is used to directly
control the three-state output buffer , which then gates the sum-
mation of the remaining terms to th e output pin. The output of
this summation can be fed back into the PLD as an input to the
array. This programm able I/O feature allows the PLD to drive
the output pin when the three-state output is enab le d or, whe n
the three-state output is dis abled, the I/O pin can be us ed as
an input to the array.
Registered Outp u ts w ith Feed back
Figure 3
illustrates the registered outputs offered on a number
of the Cypress PLDs which allow any of these circuits to func-
tion as a state sequence r . Th e summation of the produc t terms
is stored in the D-type output flip-flop on the rising edge of the
system clock. The Q output of the flip- fl op can then be gated
to the output p in by enabling the three-state output buffer. The
output of the flip-flop can also be fed b ack into the array as an
input term. The output feedback feature allows the PLD to re-
member and then alter its function based u pon that state. This
circuit can be used to execute such functions as counting,
skip, shift, and branch.
Programmable Macrocell
The programmable macrocell, illustrated in
Figure 4
, provides
the capability of def ining the architecture of each output indi-
vidually. Each of the potential outputs may be specif ied to be
“registered” or “combinatorial.” Polarity of each output may
also be individually selected allowing complete flexibility of
output configuration. Further configurability is provided
through “array” configurable “output enable” for each po tentia l
output. This feature al lows the outputs to be reconfigured a s
inputs on an individual basis or alternately used as a bidire c-
tional I/O controlled by the programmable array (see
Figure 5
).
Buried Register F eedback
The CY7C331 a nd CY7C335 PLDs provide registers that may
be “buried” or “hidden” by electing feedback of the register
output. These buried regist ers, which are u sef ul in state m a-
chines , may be implemen ted wi thout sacrificing the us e of the
associated devic e pin as an input. In previous PLDs, when the
feedback path was activated, the input pin-path to the logic
array was blocked. The proprietary CY7C335 reprogramma-
ble synchronous state machine macrocell illustrates the
shared input multiplexer, which provides an alternative input
path for the I/O pin associated with a buried macroce ll register
(
Figure 6
). Each pair o f macrocells sh ares an input multiplexer,
and as long as a lternate macrocells are buried, up to six of the
twelve output registers can be buried without th e loss of any
I/O pins as inputs. The CY7C33 5 also contains four dedicated
hidden macrocells with no external output that are used as
additio nal state registers for cr eating high-p erfor mance state
machines (
Figure 7
).
Asynchronous Register Control
Cypress also offers PLDs that may be used in asynchronous
systems in whi ch r egi ster clock, set , an d reset ar e contr olled
by the outputs of the product term array. The clock signal is
created by the processing of external inputs and/or internal
feedback by the logic of the product term array, which is then
rou ted to the register clock. The register set and reset are sim-
ilarly control led by product term o utputs and can be triggered
at any time independent of the register clock in response to
external and/or f ee dback input s pr ocessed by the logic array.
The proprietary CY7C331 Asynchronous Register ed PLD, for
which the I/O macrocell is illustrated in
Figure 8
, is an example
of such a device. The register clock, set, and reset functions
Figure 2. Programmable I/o
Figure 3. Registered Outputs with Feedback
I
I/O
INTRO-4
INPUTS, FEEDBACK, AND I/O
I
INTRO-5
INPUTS, FEEDBACK, AND I/O
Q
CLOCK
D
Q
Q
OC
3
of the CY7C331 are all controlled by product terms and are
de pende nt o nly on input signal timing and combinatorial delay
through the device logic array to enable their respective func-
tions.
Input Register Cell
Other Cypress PLDs provide input register cells to capture
short duration inputs that would not otherwise be present at
the inputs long enough to allow the device to respond. The
proprietary CY7C335 Reprogrammable Synchronous State
Machine provides these input register cells (
Figure 9
). The
clock for the input register may be provided from one of two
external clo ck input pins selectable by a config uration bit, C4,
dedicated for this purpose for each input register. This choice
of input register clock allows sig nal s to be capture d and pro-
cessed from two independent system sources, each controlled
by its own independent clock. These input register cells are
provided within I /O macrocells, as well as for dedicat ed input
pins.
Document #: 38-00165-B
Figure 4. Programm able Macrocell
3
INTRO-6
I/O
CLOCK
SP
AR
MACRO–
CELL
11
OE
0
.
.
.
4
Figure 5. CY7C335 I/O Macrocell
INTRO-7
PIN14: OE
C0
OUTPUT
ENABLE
MUX
1
0
I/O
PIN
SQ
D
Q
R
C1
1
0
OUTPUTREG
BYPASSMUX
FEED
BACK
MUX
TOARRAY
OUTPUTENABLEPRODUCTTERM
SETPRODUCTTERM C4
1
0
EXORPRODUCTTERM
RESETPRODUCTTERM C5
1
0STATE
CLK
MUX
SCLK1
SCLK2
C2
1
0INPUT
CLOCK
MUX
ICLK1
ICLK2
C3
1
0
INPUT
REG
BYPASS
MUX QD
INPUTREGISTER
CX(11- 16)
1
0
SHARED
INPUT
MUX
TOARRAY
FROMADJACENTMACROCELL
5
Figure 6. CY7C335 I/O Macrocell Pair Shar e d Input MUX
Figure 7. CY7C335 Hidden Macrocell
INTRO-8
MACRO–
CELLA
MACRO–
CELLB
MACRO–
CELL
INPUT
MUX
C3
1
0
I/O
PIN
Q-OUTPUT
FROMINPUT
REGISTEROFI/O
MACROCELLA
Q-OUTPUT
FROMINPUT
REGISTEROFI/O
MACROCELLB
I/O
PIN
FROM
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUTTO
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY
INTRO-9
SQ
D
Q
R
TOARRAY
SETPRODUCTTERM
RESETPRODUCTTERM
1
0STATE
CLK
MUX
SCLK1
SCLK2
C5
© Cypress Semiconductor Corporation, 1995. T he information c ontained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsib ility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semicondu ctor product. Nor does it convey o r im ply an y licens e under patent or other rights. Cypress Semi conductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application imp lies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor again st all charges.
Figure 8. CY7C331 Register ed Asynchronous Macr ocell
Figure 9. CY7C335 Input Macrocell
INTRO-10
PIN14 OE
MUX
S
Q
D
SETPRODUCTTERM
R
CLOCKPRODUCTTERM
FEEDBACK
MUX
TOSHARED
INPUTMUX
RESETPRODUCTTERM
OUTPUT
REGISTER
S
QD
R
INPUT
REGISTER
NPRODUCT
TERMS
INTRO-11
ICLK1
ICLK2
Q
D
C6
1
0
INPUTREGISTER
INPUT
CLOCK
MUX
TOARRAY
INPUT
PIN
C7
1
0
INPUT
REG
BYPASS
MUX
