BUILT-IN PROGRAMMABLE ROM VERSION 4.1 Overview 4.1 Overview In addition to the mask ROM versions, there are other members of the 7470 Series called built-in programmable ROM versions which are microcomputers with built-in programmable ROM. One version, the window-type EPROM version, has an built-in EPROM that can be written to and erased. Another version is a one-time programmable microcomputer whose built-in PROM can be written to but not erased. Since the functions of the built-in EPROM and one-time programmable versions are exactly the same, apart from whether the ROM contents can be erased, they are both referred to as built-in PROM versions in this manual. The built-in PROM versions have functions similar to those of the mask ROM versions, but they also have a EPROM mode that enables writing to built-in PROM. Seven built-in PROM versions of the 7470 Series are available: the M37470E4-XXXSP (one-time program- mable), the M37470E8-XXXSP (one-time programmable), the M37471E4-XXXSP/FP (one-time program- mable), the M37471E8-XXXSP/FP (one-time programmable), and the M37471E8SS (window version). A brief outline of the specifications of these microcomputers is given in Table 4.1.1. Table 4.1.1 Functions of built-in PROM versions (M37470E4-XXXSP, M37470E8-XXXSP, M37471E4-XXXSP/ FP, M37471E8-XXXSP/FP, and M37471E8SS) Functions Parameter M37470E4-XXXSP M37471E4-XXXSP, M37471E4-XXXFP and M37470E8-XXXSP | M37471E8-XXXSP and M37471E8-XXXFP and M37471E8SS Basic_ instructions 69 Instruction execution time 1.0us (minimum instructions, at 4MHz) Clock frequency 4MHz _ Memory size PROM (Note 4) 8192 bytes (Note 1) _ _ RAM 192 bytes (Note 2) InpuvOutput ports | PO, P1 VO [8btx 2 | 8-bit x2 P2 1/0 4-bit X 1 f8-bIExX 1 }P3s*df Input 4b xX 1000 4K TO (P4 | VO 2b 1 4-bit x 1 P5 Input [ T4-bit x4 Seria VO _ ~ |8-bit x 1 Timer ; 8-bit x 4 (with 8-bit latch) A-D converter 8-bit x 1 (4-channel)/8-bit X 1 (8-channel) Subroutine nesting ~ 96 (max.) (Note 3) _ Interrupt | ~~ lExternal 5, internal 6 and sofware 1 Clock generating circuit 1 builtin (with exter-|2 built-in (with external ceramic or quartz crys- nal ceramic or quartz] tal oscillator) crystal oscillator) Power supply 27 10 55V Power dissipation (typ.) 7 17.5mW (at 4MHz) a a Input/Output Input/Output voliage| 5V characteristics Output current to 10mA (PO, P1, P2 and P4: CMOS 3-state) Operating temperature range (ss [-20 10 B5S Device structure CMOS silicon gate Package ~SY| One-time. ~~ 132-pin shrink plastic] 42-pin shrink plastic] 56-pin plastic molded programmable molded DIP molded DIP QFP Window type = | |42pin shrink ceramic | DIP Note 1 : 16384 bytes for M37470E8-XXXSP, M37471E8-XXXSP/FP and M37471E8SS. 2 : 384 bytes for M37470E8-XXXSP, M37471E8-XXXSP/FP and M37471E8SS. 3: 192 (max.) for M37470E8-XXXSP, M37471E8-XXXSP/FP and M37471E8SS. 4 : Voltage of writing to PROM is 12.5V (corresponding to M5L27256). 92BUILT-IN PROGRAMMABLE ROM VERSION 4.2 Pin configuration 4.2 Pin configuration Figure 4.2.1 shows the pin configuration of M37470E4-XXXSP and M37470E8-XXXSP, Figure 4.2.2 shows the pin configuration of M37471E4-XXXSP, M37471E8-XXXSP and M37471E8SS, and Figure 4.2.3 shows the pin configuration of M37471E4-XXXFP and M37471E8-XXXFP. The built-in PROM versions have pin-compatibil- ity with the mask ROM version. (Top view) (Top view) Pir/Sapv/Aro +> Cl VY 32] PO7/D7 P53 [1 ~ [42] P52 P1sCLK/As + [2] [at] + POe/Ds Pi7/Srov/Ato +[2 41] > PO7/D? Pis/Sout/As + [3] [30] > Pos/Ds PIsvCLK/As + [3] [40] > POs/Ds P1aiSiwA7 [a] [29] + POs/0s Pis/Souv/Aa [a] [30] <-> POs/Ds PivTvAs + [5] 26] > PODs Pt/SivA7 + [5] [33] > POwW/Da PraTolAs + [6] == 27] <> PO2'Dz PraTivAs ++ [6] [37] <-> POxDs PIA ee [7] as [26] > POWD: Pi2TolAs + [7] [36] + PowDz Po + [a] oo 25] > POuwDe PIiAa +[e] zz 3s] <> POD: P2vINvAs + [a] x x 2a] a PAA Pte +[o| z= 3 Si [34] ++ POwDe P2z/INo/A2 + [19] oe 23] > Pairs PaviN7 fol = SS [+> Pas P2vINVAr > [15] Ge Jz2} < P3CNTRi/Ver P2e/INe <> [i] x B e [32] <-> Pao P20/INo/Ao <> [2] ler] P3aCNTRV/OE P2si/iNs <= [12] 2 35 38 [ai] > Pav/Ar VrcriCE [ral [zo] < PavINTivArz P2aiNs <e [ra] nw x [30] + Pao/Ars Xn > [ra] [19] = PIVINTo An P2vINVAa + [ia uv [20] P3a/CNTRi/Ver Xour + [55] [1a] RESET P22/IN2iAz + [15] [28] P3IxCNTR/OE Vss ie] 7] Vee P2viINvA: ++ [3] [27] PviNTivArz P2u/INWAc + [17| [26] < PSo/INToAn Outline 32P4B VecriGe [ral [25] + AESET Xw > [rs 24} > PS1/Xcour Fig.4.2.1_ Pin configuration (M37470E4-XXXSP_ and Xour [zo 23] < PSo/Kein M37470E8-XXXSP) Vss fe] 22 Vec Outline 42P4B (M37471E4/E8-XXXSP) 42S1B (M37471E8SS) Fig.4.2.2 Pin configuration (M37471E4-XXXSP, M37471E8-XXXSP and M374718SS) 93BUILT-IN PROGRAMMABLE ROM VERSION (Tap view) 22 < S253 &3ig ag peeeueeeeee tt Std FUE GEE NG OG o NC P16/Si/A7 < E] O C) 3] a POLDs Pis/T VAs ee Gy a2] we POWDs Pi2iTol/As - {4 1] we POD? PivAa eo [5] a0] POVWwD Pio e+ [eo] Bs 39] <> POoDo P2z/iN7 + [7] = 5 3a] <-> Pas a2 oe ~ ie e e ohae pei >< P2wiNe [19 26 3 [35] > PaciArs P2y/IN3/Ay > [1 a u 34] NC P2z/INeAz < [ia [33] < P3vCNTRVVee PauINviA: [ry [32] < P32/CNTRO/OE P2o/INo/Ao ~ [4] fat) PaviNT VAs Vaer/CE o [3 C) 30] a P3o'iNTo/An nc fi a} NC BEER WETENTY ERs oltossyedied * < 3 x g aq ao Outline 56PEN NC : No conneclion Fig.4.2.3 Pin configuration (M37471E4-XXXFP 94 and M37471E8-XXXFP)4.3 Block diagram Figures 4.3.1 to 4.3.3 shows the block diagrams of M37470E4-XXXSP, M37470E8-XXXSP, M37471E4-XXXSP, M37471E8-XXXSP, M37471E8SS, M37471E4-XXXFP, and M37471E8-XXXFP. BUILT-IN PROGRAMMABLE ROM VERSION 4.3 Block diagram ASXXX-GAOLPZEW 40) SAIAg BE 2 yndur dSXXX-BAOLPLEW 40; S81AG yREgs |b SION a6e]]0A Od vod C1 bd Lod Ot d vod 99U919/8H Eq HOD INdU| pd vod O/ A: 6 a rn es Aad A - ro Los Wo a i - | Vv LN BN ; | FO 1 2 +P : | Ls J i ; i ey ht mh SZ x2 SZ Z (a) Sd ars gS (@) A (9) X saysi6au (@} me saquiod sajs:5a1 saysiBas sme soyenuroay onaunquy ; JOSSa901 IBIS XdPU] X@puy S' id 10-8 | yeu6is josjod rc : i t i 1 Japooap sada | sardq yonanujsu| Sy 2618 (8) 20d (8) Hod <6h Jaunoo sayunod i WOdd weiboig | wesbod Wvu (g) saysiBax : uonomysuy nS (1 @10N) es (% a10N) a 7 Ss r " ae Lad snq Beg yinaa Bunesauab y90/9 - - - - - - o-o-4 - ei) Ss. 39, L3S34 imoy NX A A yndur yndjno yndul 1asay 91D HD0ID 95 Fig.4.3.1 Block diagram of M37470E4-XXXSP and M37470E8-XXXSPBUILT-IN PROGRAMMABLE ROM VERSION 4.3 Block diagram dd uod Oo SSBSALLPLEW PUB dSXXX-BSLLPLEW 40) Savkq pee :Z SSBSLLPLEW Pue dSXXX-BILZPLEW 40} Sg PBEDL <1 SION indui aBerjoa 20U2J3}9Y 54 yod induj dad A, Sd vod indu| pd uod O/| SHINO) HIND ~ I | eeeeeeeee 1 JONUOD WAAd (8) p sow, esa <3 wn i ~~, : ion wan @)s. (@) A (8) x sarsibes (gv i i Ko Jaqul Jaysibas Jaisibas SNIEIS ~ (g) ou | wORIS xapuy xapu| JOSSEI01d Jorejnunaay oman | wae : | jeuBIs josu05 a or } nn a Soh f | | t 7@p038p saikq sag ; uOINISUL z618 (8) 10d | (8) HOd 6h jaluneo | Jaiunos (gy vasa WOud weiboigq | wesbold Wvd uoHanIsul S as f oe snooy NOX : : A \Z 7 X | snq e1eq nous Bunesaveb 49019 ~ eS 3S3u SSA SOA i nox NIX Indul asey indino aindur WOD WD Fig.4.3.2 Block diagram of M37471E4-XXXSP_ and M37471E8-XXXSP(M37471E8SS) 96BUILT-IN PROGRAMMABLE ROM VERSION dd XXX-BALLELEW 40) SAKQ BE | 2 dAXXX-BALLPLEW 40} SAIAG PBEQL : | BION indul abeyjon 1d vod Ov @d vod O/| aoualajay fd bod nut yd nod on Sd vod indy : ' Y NNT) YIN YLNO LnooX | ; | ; 1: oN Epo Ne SE Me b x | : - iL 7 : : i a . a, : S : QO Ph : 4 ZS ZS Z3 i a J ; Sa SZ Z (8) Sd Z yun (8) S (BR) A (a) x 1018109) ay veoiboy wtnea| | mde] [onii,| | some | hoomtutiny| famtny) i | i t [ saviq sag sapODaPp uonons sul 2618 (@) 40d | (8) HOd z6L > Jayunoo 4a)uUN0D - WOdd wei6oig | wesdoig WY (g} se1s160. ( : Z alON uoHonuisut ton {> F i inooy NOX [ i } 4 a SZ. S NZ... 4 WDD sng Pied Bulleaue6 yoatD A 28 - 8 2 = SSAV SSA DOA 13S3u Lnox NIX indu, sey wndyjno jndul WOO} YD0ID. 97 Fig.4.3.3 Block diagram of M37471E4-XXXFP and M37471E8-XXXFPBUILT-IN PROGRAMMABLE ROM VERSION 4.4 EPROM mode 4.4 EPROM mode 4.4.1 EPROM mode The built-in PROM versions of the 7470 Series have an EPROM mode in addition to the ordinary operating mode. Use EPROM mode to write to, read from, and erase built-in PROM, in the same way as in the M5L27256 (EPROM device). The pin assignments in EPROM mode are shown in Table 4.4.1, and pin connection diagrams are shown in Figures 4.4.1 to 4.4.3. Table 4.4.1 Pin correspondence at the EPROM mode Device type name Built-in. PROM version M5L27256 | _ Vcc Vcc P33 : VPP _ Vss Vss = Pin name P11 to P17, P20 to P23 Ao to Ais LL __P80, P31, P4o, P41 _ POo to P07 Do to D7 |... VREFO CE a P32 OE a i ad eo GAs) Pte CLK oo FF [31] + Pos XD) P1s'Sour ee BO} > Pog ee ODD CA). - PiaSin [4] 23} +> Po. - -- CD pot a B Fi] Po. Sen 8 Bre aS : Plows fl 30 [28] * poo () As co P2aviNs < [3] ee fea} a> pay - A) CAz) P2s'INe ae fio x x 23) eh 4, 8 een He 7" &__ GSE pa CA) ~~ P2vINy ee fi] & g 22] < payCNTR1 Cer) Bo P2uINo + [i2| [21] < paxCNTRo -- -ED CE --_. Vacee [13] [20] < payiNT: ---~- Aa) Qo Xin [| 3) P3vViINTso < An Xow [ig] ia} - RESET ----- @- - ve R] vee ED >) are ferminats for PROM (correspanding to MSL 27256) Fig.4.4.1 Pin connection at EPROM mode (M37470E4-XXXSP and M37470E8-XXXSP) 98BUILT-IN PROGRAMMABLE ROM VERSION 4.4 EPROM mode PSs + ne a2] P52 ye P17Saov +2] ol ++ Po op Cs P1sCLK + [3] [a0] = Pos >) Bs P1s/Sour fl [39] + Pos Os) CAD P14/Sin > (5) [3a] <> POa _~d CAs) PiaT: + fe [a7] <> POs On CAs ans D6] > Por - OD GD -- Pueef] ogg leer, a Pieesfo] 299 fel++ po .- cBa) P2viNr + [fo] 3 5 5 33] <> P43 P2w/INe [i = @ 2 [32] + P42 P2siNs + [12 & [i] > pa; ar) P2allNa fy n * zB [30] +> P4y - ___A AD P2viNa + [ta 00 BJ payenta: vee) AD P2g/lNe ++ [28] < PaxCNTRo CD AD PaviN: + [16 [27] pavint, _CA) Rod PaviNe + [17] [26] PaciNTs AD CE vnee [ra] [es] < RESET == Xw * [19 [2a] + P5i/Xcour Vss Xour + [23] P5o/Xew G--vs E Pvc CD are terminals for PROM (corresponding to MSI 27256) Fig.4.4.2 Pin connection at EPROM mode (M37471E4-XXXSP, M37471E8-XXXSP and M37471E8SS) se 8 aae a || Src cbseeegsy ptt ltt TEUVAL FHF NC 4] NC Ary PiwSm ee [e C) a] = PO. Pis'T: [3] [az] Pos Ary Piito ++ [a] [ar] => POs - von Pty oe fal [a] ++ po. Pia Ei zs a6] > PO, af PaniNr + [7] 5 = [38] = Pay P2s'lNe [a] min [37] + Pao . P2siNs = [3] Q : [22] <= pg, - ap . P2eINa ae [r5) fore; [35] ++ pa, AW Cr> P2viN: + [i] uu Ga] = NG - > P22'INo = [i Ea] - paycont a, ee CAD Ravin: + [ial be] pavcntR: COE> CAs y PaalINa = i) ba] Pawint A CE) Yur + fig C) ws Paints AND NC ca 29) NC ae Oe + z ZF 50 |e aM jl 8 i a5 a 2 Oo 232 Jr 3! 3) Vss. Fig.4.4.3 Pin connection at EPROM mode (M37471E4-XXXFP and M37471E8-XXXFP) 99BUILT-IN PROGRAMMABLE ROM VERSION 4.4 EPROM mode 4.4.2 Pin descri ption Table 4.4.2 shows the pin description at ordinary operating mode and EPROM mode. Table 4.4.2 Pin description Pin Name Mode Function Vcc, Vss Supply voltage Ordinary operatiory | Supply 2.7 to 5.5V to Vcc, and OV to Vss. EPROM AVss Analog power supply Ordinary operation | Acts as ground level input pin for A-D con- EPROM verter. Same voltage as VSs is applied. (Note 1) VREF Reference voliage input | Ordinary operation | Acts as reference voltage input pin for the A~D oo converter. _ Mode input. __. | EPROM Becomes CE input. RESET Reset input Ordinary operation | Specifies reset when held at L" for at least Qus. EPROM Connect to Vss. XIN Clock input Ordinary operation | Acts as input and output pins interfacing with EPROM the internal clock generating circuit. Connect a ceramic resonator or crystal oscillator be- tween the XIN and XOUT pins to set the oscil oe lator frequency. An internal feedback resistor XOUT Clock output Ordinary operatiory |is connected between the XiN and XOUT pins. EPROM If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin _. open. PQo-P07 VO port Po Ordinary operation | Acts as 8-bit I/O port with CMOS output for- mat. When input port is selected, these pins can be connected individually to pull-up tran- | sistors. A key on wakeup function is also provided. ____ [Data VO Do-D7 EPROM Becomes data(Do-D7) 1/0. P10-P17 VO port P41 Ordinary operation | Acts as 8-bit /O port with CMOS output for- mat. When input port is selected, these pins /can be connected in groups of four to pull-up transistors. P12 and P13 can also be used as timer outputs To and T1, and P14, P15, Pte, and P17 can also be used as SIN, SOUT, CLK, and SRDY of the serial I/O function. SouT and SRDY outputs can be set to N-channel open drain output. Address input Aa-Ato |EPROM Pins P11 to P17 are address(A4A1o) input pins. Leave P10 pin open. P20-P27 (Note 2) VO port P2SS~S:* Ordinary operation Acts as 8bit /O port with CMOS output for- | Address input Ao-A3 mat. When input port is selected, these pins can be connected in groups of four to pull-up transistors. These pins can also be used as analog inputs INo to IN7. EPROM Pins P20 to P23 are address(Ao-A3) input pins. Leave P24 to P27 open. Note 1: For 56-pin QFP type only. 2: At M37470E4-XXXSP and M37470E8-XXXSP, there are 4-bit as P2o-P23(INo-IN3) only. 100BUILT-IN PROGRAMMABLE ROM VERSION Table 4.4.2 Pin description 4 EPROM mode Pin Name Mode Function P30-P33 Input port P3 Ordinary operation Acts as 4bit input port. P30 and P31 can also be used as external interrupt input pins INTo and INT1, and P32 and P33 can also be used as timer input pins CNTRo and CNTRi. Address input A11, A12 Mode input VPP input EPROM Pins P30 and P31 are address(A11, A12) input pins. P32 becomes OE input pin. P33 be- comes VpP input pin. At programming and program verifing, supply VPP level into this pin. P40-P43 (Note 2) VO port P4 Ordinary operation Acts as 4bit /O port with CMOS output for- mat. When input port is selected, these pins can be connected in groups of four to pull-up transistors. Address input A713, Ata | EPROM Pins P40 and P41 are address(A13, A14) input pins. Leave pins P42 and P43 open. P50-P53 (Note 3) Input port P5 TOrdinary operation Acts as 4bit input port that can be connected as a group of four pins to pull-up transistors. P50 and P51 can also be used as the XCIN and XCOUT pins for the clock-function clock gener- ating circuit. When using these pins as XCIN and XCOUT pins, an internal feedback resistor is connected between them. To enable exter- nal clock input, connect the clock source to the XCIN pin and leave the XCOUT pin open. EPROM Setting to open. Note 2: At M37470E4-XXXSP and M37470E8-XXXSP, there are 2-bit as P4o and P41 only. 3: At M37470E4-XXXSP and M37470E8-XXXSP, there are nothing. 104BUILT-IN PROGRAMMABLE ROM VERSION 4.4 EPROM mode 4.4.3 Reading, writing, and erasure of bulit-in PROM Activate EPROM mode in the built-in PROM versions by forcing the RESET pin to L. In EPROM mode, the built- in PROM can be read from, written to, and erased, as described below. (1) Reading oe Apply OV to the RESET pin and 5V to the Vcc pin. Input the address signal (Ao to A14) and set the CE and OE pins to L"the PROM contents will appear at the data /O pins (Do to D7). If the CE pin or the OE pin is set to H, the data I/O pins will float. (2) Writing a Apply 0V to the RESET pin and 6V to the Vcc pin. Set the OE pin to H" and apply VPP to the VPP pin to activate program mode. Set the address to be written to by the address input pins (Ao to A14) and input the data in parallel through the data '/O pins (Do to D7). When the CE pin is set to L in this status, the data is written to PROM. (3) Erasure Only the built-in EPROM version that has an erasure window on the package's top surface (M37471E8SS) can be erased. To erase the EPROM, shine an ultraviolet light source of wavelength 2537A onto the window for a minimum dose of 15W-s/cm?. Note the following points when writing data with a PROM writer: * M37470E4-XXXSP, and M37471E4-XXXSP/FP When using a PROM writer, the address range should be between 600016 and 7FFF 16. ReadMrite operations on addresses 000016 to SFFF16 cannot be performed correctly. * M37470E8-XXXSP, M37471E8-XXXSP/FP and M37471E8SS When using a PROM writer, the address range should be between 400016 and 7FFF 16. When data is written between addresses 000016 and 7FFF 16, fill addresses 000016 to 3FFFi6 with FFi6. Table 4.4.3 Input/Output signal af each mode Mode Pinname} CE OE VpP Voc RESET Do~D7 Read VIL Vit Vcc Output Output disable =| VIL ViIHO [VCC Floating _ Write Vk VIH 12.5V Voc Ov input Verity ViH Vit | 12.5V | __ Output Write disable VIH VIH 4125V Floating Note : VIL means L input voltage, VIH means H input voltage. 102BUILT-IN PROGRAMMABLE ROM VERSION 4.4 EPROM mode 4.4.4 Notes on handling (1) Sunlight and fluorescent fight include wavelengths that will erase written data. When using the window version of the 7470 Series in read mode, always cover the transparent glass window with a light-proof seal. (2) Mitsubishi provides light-proof seals designed to cover the transparent glass window of the window version. Make sure that the seal does not touch the lead pins of the microcomputer. (3) Before erasing the window version, clean the transparent glass of the window. Dirt such as grease from hands and glue may hinder the passage of ultraviolet light and affect the erasure characteristics. (4) Writing involves the use of high voltages, so make sure that excessive voltages are not used. Pay particular attention when turning on the power source. (5) Mitsubishi does not test or screen any writing to PROM in blank one-time programmable microcomputers after they have left the factory. To improve reliability after writing, we recommend that these microcomputers are written to and tested in the sequence shown in the flow diagram of Figure 4.4.4. (1: Blank microcomputers have nothing written in PROM when they leave the factory.) Writing with PROM writer Screening (Leave at 150C for 40 hours) (Note 1) Verify test with PROM writer ren Function check in target device Note 1: Since the screening temperature is higher than storage temperature, never expose to 150 C exceeding 100 hours. Note 2: Function checks in actual devices can also eliminate damage due to surges during handling. Fig.4.4.4 Writing and test for blank one-time programmable type 103BUILT-IN PROGRAMMABLE ROM VERSION 4.5 Electric Characteristics 4.5 Electric Characteristics 4.5.1 Electric characteristics of M37470E4-XXXSP and M37470E8-XXXSP Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Vec Supply voltage 0.3 to 7 Vv Vi Input voltage Xn . 0.3 to Ver+0.3} V Vv, Input voltage POo-P07, P1o-P17, P2o-P2s, With respect to Vss OF to Vo+03l P30-P3s, Pdo-P41, Vrer, RESET | Output transistors are | (Note 1) Output voltage POo-PO?, Plo-P17, P2c-P2s, at OFF state. Vo P4o-P41, Xour 0.3 to Voc+0.3] V Pd Power dissipation __[Ta=25C 1000 mw Topr Operating temperature ~ ~20 to 85 C Tstg Storage temperature 40 to 150 C Note 1: At writing to PROM, the value for P33 is 13V. Recommended operating conditions (Vcc=2.7 to 5.5V, Vss=0V, Ta=-20 to 85C, unless otherwise noted) Limits ; Symbol Parameter Min. Typ. Max. Unit Veco Supply voltage 2.7 5 55 v Vss Supply voltage 0 V Vin H" input voltage POo-P07, P1o-P17, P3o-P33, RESET, Xw 0.8Vcc Vec Vv Vin H input voltage P2o-P2s, P4o-P4; 0.7Vcc Veco v Vi "L input voltage POo-P07, Plo-P17, P3o-P3s 0 0.2Vcc | V Vit L input voltage P2o-P2s, P4o-P41 | 0 0.25Vec| V Vit "L" input voltage Xn 0 0.16Vcc{ V Vi L" input voltage RESET 0 0.12Vec | V lou(sum) [H" sum output current POo-P07, P4o-P41 30 | mA lon(sum) | H sum output current Pto-P17, P2o-P2s _ -30 mA lor(sum) | L sum output current POc-P07, P4o-P4: 60 mA loi(sum) | L sum output current P1o-P17, P2o-P2s 60 mA lou(peak) | H peak output current POo-P07, P1o-P17, P2c-P2s, P4oP41 ~10 mA lo.(peak) | L peak output current POc-P07, P1o-P17, P2e-P23, P4oP4: | 20 mA lonfavg) | H average output current POr- FOr Plo-P17, P2o-P23, 5 mA __Pdo-P4: (Note 3) CL average output current POo-PO7, P1o-P17, P2o~-P2s, lo.(avg) p P4o-P4 (Note 3) 10 mA tienTA) Timer input frequency CNTRo (P32), CNTR: (P33) (Note 2) | 1 MHz ficuK) Serial VO clock input frequency CLK(P1s) (Note 2) _ to 1 | MHz {(Xin) Clock oscillating frequency (Note 2) 4 MHz Note 2: Oscillation frequency is at 50% duty cycle. 3: The average output current lov(avg) and lo (avg) are the average value during a 100ms. 104BUILT-IN PROGRAMMABLE ROM VERSION 4.5 Electric Characteristics Electrical characteristics (Vcc=2.7 to 5.5V, Vss=OV, Ta=-20 to 85C, unless otherwise noted) a: Limits . Symbol Parameter Test Conditions Min. | Typ. [Max. Unit Vou H" output voltage POc-P07, P1o-P17, Vcc=5V, lou=-5mA 3 Vv P20-P23, P4o, P4: Vec=3V, lou=1.5mA 2 Vor L output voltage POc-P07, P1o-P17, Vcc=5V, lo=10MmA 2. Vv Po P23, P40, P41 Vec=3V, lo.=3mA 1 . Vcc=5V a 0.5 V1--V1-| Hysteresis POQo-PO7, P3cP3s _ Vocz3V 03 Vv : ' Vec=5V 0.5 Vr.-Vr-| Hysteresis RESET - Voo3V a 03 Vv . : Voec=5V 05 wVt- LK Vr.Vr- | Hysteresis PteCLK _ [use as input Voon3V 03 Vv Vi=0V, Vcc=5V -5 A | L input current POe-P07, P1o-P1,, not use pull-up transistor |Vcc=3V -3| # " P30-P32, P4o, P41 Vi=0V, Vec=5V |-0.25| -0.5| -1.0) __use_pulhup transistor |Vco=3V |-0.08)-0.18| -0.35 | wn: Vcc=5V -5 Iie L" input current P3s oo Vi-0V Voca3V 3 uA Vi=0V, not use as analog input, |Vcc=5V 5 A ne nol_use pull-up transistor Vec=3V -3| # ln. L input current P2o-P2s VizOV, not use as analog inpul, [Vcc=5V 1-90.25) -0.5| -1.0 A | use pullup transistor [Veo=3V |-0.08|-0.18/ 0.35] apo Vi=0V Vec=5V -5| i L input current RESET, Xi __| (Kwis at stop mode) Veca3V 23 HA | H input current POo-P07, P1o-P1:, VieVcc, Vec=5V 5 A " P3c-P32, P4o, P41 __{ not_use pull-up transistor [Vcc=3V 3] # Hj - Veo=5V 5 lin H input current P33 _ Meee ee 3 LA ap: VieVec, not use as analog input.) Vcc=5V 5 IPN input current PeePes not use pullup transistor Vec=3V | 3] HA aye: Vi=Vce, Vec=5V 5 [| neat current RESET, Xs | wis at stop mode) __[Veo=3V 3| HA At normal operation, Vece5V 35 7 A-D conversion is not executed f(Xin)=4MHz ee Vec=3V 18 3.6 At normal operation, Vec=5V 4 8) mA lec Supply current A-D conversion is executed = - f(Xn)=4MHz ___Neo=8V a4 At wait mode, Vec=5V 1 2 {(Xin)=4MHz __ [Vcc=3V 05 1 Stop all oscillation Ta=25C 0.1 1 WA Vec=5V Ta=85C, 1| 10 Vaam {RAM retention voltage Stop all oscillation 2 Vv 105BUILT-IN PROGRAMMABLE ROM VERSION 4.5 Electric Characteristics A-D converter characteristics (Vcc=2.7 to 5.5V, Vss=0V, Ta=-20 fo 85C, f(Xin)=4MHz, unless otherwise noted) imit . Symbol Parameter Test Conditions Min. De Max. | Unit ___|Resolution _ fo 8 | bits ___|Non-linearity error oo +2 | LSB - _ [Differential non-linearity error ; +09 | LSB PP Voc=Vrer=5.12V, loi(sum)=OmA 2 Zero transition error : a Vor [ero transition error _iVoc=Vacr=3.072V, lo(sum)=OmA 3 LSB +4; Vec=Vacr=5.12V 4 Full-scale transition error oT ae Mesr__[Fulscale lanstion a, Vec=Vaer=3.072V 7| 8 teow [Conversion time . oe 25 | HS Vvace | Reference input voltage oo 0.5Vcc Vec Vv Riaopea |Ladder resistance value oe / - | 2 5 10 kQ Via Analog input voltage 0 Vaer Vv 106BUILT-IN PROGRAMMABLE ROM VERSION 4.5 Electric Characteristics 4.5.2 Electric characteristics of M37471E4-XXXSP/FP, M37471E8-XXXSP/FP and M37471E8SS Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Vec Supply voltage 43 to7 Vv Vi Input vottage Xwn 0.3 to Vec+03] V Input voltage POc-PO07, Pto-P17, P2o-P2;, With respect to Vss Vi P3c-P32, P4c-P43, P5o-P5s, Output transistors are Note ty Vv Veer, RESET at OFF state. Vo Output voltage pape, P1o-P17, P2o-P27, 03 to Voo40.3| V 4o~-P43, Xout Pd Power dissipation a Ta=25C 1000(Note 2) | mW Topr Operating temperature 20 to 85 C Tstg Storage temperature 40 to 150 C Note 1: At writing to PROM, the value for P33 is 13V. 2: 500mMW for M37471E4-XXXFP and M37471E8-XXXFP. Recommended operating conditions (Vcc=2.7 to 5.5V, Vss=AVss=0V, Ta=-20 to 85C, unless otherwise ngted Limits : ymbol Parameter Min: Typ. Max. Unit Voc Supply voltage | 27] 5 5.5 v Vss Supply voltage oe a _. 0 _[ Vv AVss Analog supply voltage 0 Vv Vin "H input voltage POo-PO7, P1oP17, P3c-P33, RESET, Xw 0.8Vcc Vcc Vv Vin H" input voltage P2c-P27, P4o-P42, P5o-P53 (Note 3) 0.7Vcc Voc Vv Vit L input voltage POc-P07, P1o-P17, P3c-P3s 0 0.2Vcc Vv Viv ( input voltage P2o-P27, P4oP4s, P5o-P53 (Note 3) o | 0.25Vcc| V Vi. L input voltage Xn 0 0.16Vcc| V Vit L input voltage RESET 0. 0.12Vce [__V lox(sum) |H sum output current POc-P07, P4c-P4s -30 mA lou(sum) |H sum output current Pto-P17, P2o-P2z ~30 mA lou(sum) |L sum output current PQo-PQ7, P4o-P43 60 mA _ loi(sum) [L sum output current P1o-P17, P2o-P27 / 60 mA lon(peak) |"H" peak output current POc-P07, P1o-Pi7, P20-P27, P4o-P4s ~10 mA lo.(peak) |"L" peak output current POc-P07, P1o-P17, P2o-P27, Pdo-P43 [| 20 mA lon(avg) H average output current POc-P07, Plo-P17, P20-P27, 5 mA P4o-P43 (Note 6) _ "L average output current POo-P07, Plo-P17, P20-P27, lor(avg) P4o-P43 (Note 6) _ 10 | mA ficnTR) Timer input frequency CNTRo (P32), CNTR: (P33) (Note 4) 1 MHz ficix) Serial VO clock input frequency CLK(P16) (Note 4) 1 MHz f(Xin) Clock oscillating frequency (Note 4) oe 4_ | MHz f(Xcin) Clock oscillating frequency for clock function (Note 4, 5) 32 50 kHz Note 3: It is except to use P50 as Xen. 4: Oscillation frequency is at 50% duty cycle. 5: When used in the low-speed mode, the clock oscillating frequency for clock function should be f(Xcin) <f(Xin)/3. 6: The average output current lon(avg) and la(avg) are the average value during a 100ms. 107BUILT-IN PROGRAMMABLE ROM VERSION 4.5 Electric Characteristics Electrical characteristics (Vcc=2.7 to 5.5V, Vss=AVss=0V, Ta=-20 to 85C, unless otherwise noted) Symbol Parameter Test Conditions Min. Typ [Max Unit Vv. H output voltage POo-P07, P1o-P17, | Vec=5V, lox=5SmA 3 Vv on P20-P27, P4o-P43 [Voc=3V, tox=1.5mA 2 Vor L output voltage POo-P07, P1o-P17, | Vcc=5V, lo=10mA 2 Vv P20-P27, P4o-P43 | Vcc=3V, la=3mA 1 : Vec=5V 05 Vt.-Vr-| Hysteresis POo-P07, P3o-P3s Voor3V 03 V aa Vec=5V 0.5 Vr.-Vr1-|Hysteresis RESET Voo3V 03 Vv V1.-V1_l Hysteresis P1e/CLK use as CLK input veces a8 Vv ae: Vi=0V, Vec=5V -5 L input current oo pe at pa, not use pull-up transistor Voc=3V =g | HA t ni 4o-P43, =OV, Veo=BV |-0.25| -05 [-10| ore use pull-up transistor Vec=3V |-0.08|-0.18 |-0.35 ana Vec=5V -5 In L input current P33 Vi=0V Voon3V =3 pA VicOV, not use as analog input, Vec=5V -5 A gm not use pull-up transistor Vec=3V -3 In L input current P2o-Pe7 V=OV, not use as analog input, [Voc=5V |-0.25| -05 [-10/ use pull-up transistor Vec=3V |-0.08|-0.18}-0.35 am: - Vi=0V Vec=5V 5 be L" input current RESET, Xw (Xv is at stop mode) Vecu3V = pA H input current POc-P07, P1o-P17, VieVoc Vec=5V 5 bn P30-P32, P4o-P4s, rae ; pA P5.-P5, not use pull-up transistor Vec=3V 3 ba H input current P33 Vi=Voc yee 2 HA ap : VieVoc, not use as analog input, |(Vcc=5V 5 laa Ins H input current P2o-P2z not use pull-up transistor Vec=3V 3 |b aps 73; Vi=Vec, Vec=5V 5 Vi H input current RESET, Xx (Xw is at stop mode) Vec=3V 3 HA At normal operation, Vec=5V 35 | 7 A-D conversion is not executed f(Xin)=4MHz Vcc=3V 18 3.6 mA At normal operation, Vec=5V 4 8 A-D conversion is executed f(Xin)=<4MHz Vec=3V 2/4 At low- speed mode Vec=5V 80 Xcour is low-power mode, ec 40 LA lee Supply current A-D conversion is not executed Vece3V 45 | 40 f(Xiw)=OH2, {(Xcw)=32kHz, Tax25C | *O* At wait mode, Vec=5V 1 2 mA {(Xin)=4MHz Vec=3V 0.5 | 1 At wait mode, f(Xn)=0Hz, Vec=5V 3 12 {(Xcw)=32kH2, Xcour is low-power mode, Ta=25C _|Vec=3V 2 | 8 [HA Stop all oscillation Ta=25C 01 | 1 Vec=5V Ta=85C) { 10 Vram __|RAM retention voltage Stop all oscillation 2 V 108BUILT-IN PROGRAMMABLE ROM VERSION 4.5 Electric Characteristics A-D converter characteristics (Voc=2.7 to 5.5V, Vss=AVss=0V, Ta=-20 to 85C, f(Xw}=4MHz, unless otherwise noted) Symbol Parameter Test Condition Min. Typ. Max Unit __|Resolution 8 bits ___|Non-linearity error +2 | LSB ~__| Differential non-linearity error _ +0.9 | LSB ys Vec=Vaer=5.12V, lor(sumj=OMA 2 Vor Zero transition error Voo=Vaer=3.072V,_lo.(sum)-OmA 3 LSB a: Voc=Varer=.12V 4 Vest Full-scale transition error VocuVacru3 072V 7 LSB tconv _| Conversion time | _ 25 us Vvrer | Reference input voltage ; 0.5Vcc Vec Vv Riaover | Ladder resistance value _ 2 5 10 kQ Via Analog input voltage 0 Vaer Vv 109