Low Capacitance, Low Charge Injection,
±15 V/+12 V, iCMOS, SPST in SOT-23
Data Sheet ADG1201
Rev. A Document Feedback
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FEATURES
2.4 pF typical off switch source capacitance, dual supply
<1 pC charge injection
Low leakage: 0.6 nA maximum at 85°C
120 Ω typical on resistance at 25°C, dual supply
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
VINH = 2.0 V minimum
VINL = 0.8 V maximum
Rail-to-rail operation
6-lead SOT-23 package
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
FUNCTIONAL BLOCK DIAGRAM
ADG1201
SD
IN
SWITCH SHOWN FOR A LOGIC 1 INPUT
06576-001
Figure 1.
GENERAL DESCRIPTION
The ADG1201 is a monolithic complementary metal-oxide
semiconductor (CMOS) device containing a single-pole,
single-throw (SPST) switch designed in an iCMOS® process.
iCMOS is a modular manufacturing process combining a
high voltage CMOS and bipolar technologies. iCMOS
enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage devices has been able
to achieve. Unlike analog ICs using conventional CMOS
processes, iCMOS components can tolerate high supply
voltages while providing increased performance,
dramatically lower power consumption, and reduced
package size.
The ultralow capacitance and charge injection of this
switch makes it an ideal solution for data acquisition and
sample-and-hold applications, where low glitch and fast
settling are required. Fast switching speed coupled with
high signal bandwidth also makes the device suitable for
video signal switching.
iCMOS construction ensures ultra low power dissipation,
making the device ideally suited for portable and battery-
powered instruments.
The ADG1201 contains a SPST switch. Figure 1 shows that with
a logic input of 1, the switch of the ADG1201 is closed. The
switch conducts equally well in both directions when on and has
an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
2. <1 pC charge injection.
3. Ultralow leakage.
4. 3 V logic-compatible digital inputs:
VINH = 2.0 V minimum, VINL = 0.8 V maximum.
5. No logic voltage (VL) power supply required.
6. SOT-23 package.
ADG1201 Data Sheet
Rev. A | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings ............................................................6
Thermal Resistance .......................................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Test Circuits ..................................................................................... 11
Terminology .................................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
1/2019Rev. 0 to Rev. A
Deleted ADG1202 .............................................................. Universal
Changes to Features Section and Product Highlights Section ... 1
Changes to Table 1 ............................................................................ 3
Changes to Absolute Maximum Ratings Section and Table 3 .... 6
Added Thermal Resistance Section ............................................... 6
Added Table 4; Renumbered Sequentially .................................... 6
Changes to Figure 3 Caption to Figure 8 Caption ........................ 8
Changes to Figure 9 Caption, Figure 10 Caption, and
Figure 11 Caption ............................................................................. 9
Changes to Figure 15 Caption and Figure 19 Caption .............. 10
Changes to Figure 26 and Figure 27 ............................................. 12
Changes to Ordering Guide .......................................................... 14
2/2008—Revision 0: Initial Version
Data Sheet ADG1201
Rev. A | Page 3 of 14
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C
−40°C to
+85°C
40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 120 typ VDD = +13.5 V, VSS = −13.5 V
200 240 270 max Analog voltage on Terminal S (VS) = ±10 V, source
leakage current (IS) = −1 mA, see Figure 20
On Resistance Flatness
(RFLAT(ON))
20 typ VS = −5 V, 0 V, and +5 V, IS = −1 mA
60 72 79 max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage (I
S
(Off))
±0.004
nA typ
V
S
= ±10 V, analog voltage on Terminal D (V
D
) = ±10 V,
see Figure 21
±0.1 ±0.6 ±1 nA max
Drain Off Leakage (ID (Off )) ±0.004 nA typ VS = ±10 V, VD = ±10 V, see Figure 21
±0.1 ±0.6 ±1 nA max
Channel On Leakage (ID, IS
(On))
±0.04 nA typ VS = VD = ±10 V, see Figure 22
±0.15 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage (VINH) 2.0 V min
Input Low Voltage (VINL) 0.8 V max
Input Current (IINL or IINH) 0.005 µA typ Voltage on IN pin (VIN) = VINL or VINH
±0.1 µA max
Digital Input Capacitance
(CIN)
2.5 pF typ
DYNAMIC CHARACTERISTICS1
On Time (tON) 140 ns typ Load resistance (RL) = 300 Ω, load capacitance (CL) =
35 pF
170 200 230 ns max VS = 10 V, see Figure 26
Off Time (tOFF) 90 ns typ RL = 300 Ω, CL = 35 pF
105 130 141 ns max VS = 10 V, see Figure 26
Charge Injection −0.8 pC typ VS = 0 V, supply resistance (RS) = 0 Ω, CL = 1 nF, see
Figure 27
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23
Total Harmonic Distortion +
Noise (THD + N)
0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
−3 dB Bandwidth 660 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 24
Off Switch Source
Capacitance (CS (Off ))
2.4 pF typ VS = 0 V, frequency = 1 MHz
3 pF max VS = 0 V, frequency = 1 MHz
Off Switch Drain
Capacitance (CD (Off ))
2.8 pF typ VS = 0 V, frequency = 1 MHz
3.3 pF max VS = 0 V, frequency = 1 MHz
On Switch Capacitance (CD,
CS (On))
4.7 pF typ VS = 0 V, frequency = 1 MHz
5.6 pF max VS = 0 V, frequency = 1 MHz
ADG1201 Data Sheet
Rev. A | Page 4 of 14
Parameter 25°C
−40°C to
+85°C
40°C to
+125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
Positive Supply Current (IDD) 0.001 µA typ Digital inputs = 0 V or VDD
1.0
µA max
IDD 60 µA typ Digital inputs = 5 V
95 µA max
Negative Supply Current (ISS) 0.001 µA typ Digital inputs = 0 V, 5 V, or VDD
1.0 µA max
V
DD
/V
SS
±5 to ±16.5
V
min/max
GND = 0 V
1 Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
RON 300 typ VDD = 10.8 V, VSS = 0 V
475 567 625 max VS = 0 V to 10 V, IS = −1 mA, see Figure 20
RFL AT(ON) 60 typ VS = 3 V, 6 V, and 9 V, IS = −1 mA
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
IS (Off ) ±0.006 nA typ VS = 1 V or 10 V, VD = 10 V or 1 V, see Figure 21
±0.1 ±0.6 ±1 nA max
ID (Off ) ±0.006 nA typ VS = 1 V or 10 V, VD = 10 V or 1 V, see Figure 21
±0.1 ±0.6 ±1 nA max
ID, IS (On) ±0.04 nA typ VS = VD = 1 V or 10 V, see Figure 22
±0.15 ±0.6 ±1 nA max
DIGITAL INPUTS
VINH 2.0 V min
VINL 0.8 V max
IINL or IINH 0.001 µA typ VIN = VINL or VINH
±0.1
µA max
CIN 3 pF typ
DYNAMIC CHARACTERISTICS
1
t
ON
190
ns typ
R
L
= 300 , C
L
= 35 pF
250 295 340 ns max VS = 8 V, see Figure 26
tOFF 120 ns typ RL = 300 , CL = 35 pF
155 190 210 ns max VS = 8 V, see Figure 26
Charge Injection 0.8 pC typ VS = 6 V, RS = 0 , CL = 1 nF, see Figure 27
Off Isolation 80 dB typ RL = 50 , CL = 5 pF, frequency = 1 MHz,
see Figure 23
−3 dB Bandwidth 520 MHz typ RL = 50 , CL = 5 pF, see Figure 24
CS (Off ) 2.7 pF typ VS = 6 V, frequency = 1 MHz
3.3 pF max VS = 6 V, frequency = 1 MHz
CD (Off ) 3.1 pF typ VS = 6 V, frequency = 1 MHz
3.6
pF max
V
S
= 6 V, frequency = 1 MHz
CD, CS (On) 5.3 pF typ VS = 6 V, frequency = 1 MHz
6.3 pF max VS = 6 V, frequency = 1 MHz
Data Sheet ADG1201
Rev. A | Page 5 of 14
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
1.0 µA max
IDD 60 µA typ Digital inputs = 5 V
95
µA max
VDD 5 to 16.5 V min/max VSS = 0 V, GND = 0 V
1 Guaranteed by design, not subject to production test.
ADG1201 Data Sheet
Rev. A | Page 6 of 14
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
V
DD
to V
SS
35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1 VSS0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 GND 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D 100 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current per
Channel, S or D
30 mA
Temperature
Industrial Range 40°C to +125°C
Storage Range −65°C to +150°C
Junction 150°C
Reflow Soldering Peak, Pb-
Free
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
RJ-61 229.6 91.99 °C/W
1 Thermal impedance values measured on a JEDEC 1S2P thermal test board.
See JEDEC JESD-51.
ESD CAUTION
Data Sheet ADG1201
Rev. A | Page 7 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06576-002
V
DD 1
GND
2
V
SS 3
IN
6
D
5
S
4
ADG1201
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 GND Ground (0 V) Reference.
3 VSS Most Negative Power Supply Potential.
4 S Source Terminal. This pin can be an input or output.
5 D Drain Terminal. This pin can be an input or output.
6 IN Logic Control Input.
Table 6. ADG1201 Truth Table
IN Switch Condition
1 On
0 Off
ADG1201 Data Sheet
Rev. A | Page 8 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = + 15V
VSS = –15V VDD = +16. 5V
VSS = –16.5V
SOURCE OR DRAI N V OLTAGE (V)
ON RES ISTANCE (Ω)
200
180
160
140
120
100
60
80
0
20
40
–18 –15 –12 –9 –6 –3 39150612 18
06576-003
VDD = + 13.5V
VSS = –13.5V
TA = +25ºC
Figure 3. On Resistance vs. Source or Drain Voltage, Dual Supply
SOURCE OR DRAI N V OLTAGE (V)
ON RES ISTANCE (Ω)
450
400
350
300
250
150
200
0
50
100
–5 –4 –3 –2 –1 240 1 3 5
06576-004
VDD = + 5.5V
VSS = –5.5V
TA = +25°C
Figure 4. On Resistance vs. Source or Drain Voltage, Dual Supply
VDD = 13.2V
VSS = 0V
SOURCE OR DRAI N V OLTAGE (V)
ON RES ISTANCE (Ω)
450
400
350
300
250
150
200
0
50
100
0 2 4 6 8 10 12
06576-005
VDD = 12V
VSS = 0V
VDD = 10.8V
VSS = 0V
TA = 25° C
Figure 5. On Resistance vs. Source or Drain Voltage, Single Supply
SOURCE OR DRAI N V OLTAGE (V)
ON RES ISTANCE (Ω)
250
150
200
0
50
100
–15 –10 –5 0510 15
06576-006
VDD = + 15V
VSS = –15V
TA = +125°C
TA = +25°C
TA = +85°C
TA = –40° C
Figure 6. On Resistance vs. Source or Drain Voltage, Different Temperatures,
Dual Supply
SOURCE OR DRAI N V OLTAGE (V)
ON RES ISTANCE (Ω)
600
400
500
300
200
0
100
0 2 4 6 8 10 12
06576-007
VDD = + 12V
VSS = 0V TA = +125°C
TA = +25°C
TA = +85°C
TA = –40° C
Figure 7. On Resistance vs. Source or Drain Voltage, Different Temperatures,
Single Supply
LEAKAGE CURRE NT (pA)
0
–450
–400
080
06576-028
200
150
100
50
–50
–100
–150
–200
–250
–300
–350
20 40 60 100 120
VDD = + 15V
VSS = –15V
VBIAS = ± 10V
TEMPERATURE (ºC)
IS (OFF) + ID (OFF) +
IS (OFF) – + ID (OFF) – +
ID, IS (ON) + + ID, IS (ON) – –
Figure 8. Leakage Current vs. Temperature, Dual Supply
Data Sheet ADG1201
Rev. A | Page 9 of 14
LEAKAGE CURRENT (pA)
0
–250
100
080
06576-026
150
–50
–100
–150
–200
50
20 40 60 100 120
TEMPERATURE (ºC)
I
S
(OFF) + – I
D
(OFF) + –
I
S
(OFF) – + I
D
(OFF) – +
I
D
, I
S
(ON) + + I
D
, I
S
(ON) – –
V
DD
= +5V
V
SS
= –5V
V
BIAS
= ±4.5V
Figure 9. Leakage Currents vs. Temperature, Dual Supply
LEAKAGE CURRENT (pA)
0
–200
100
080
06576-027
300
250
200
150
–50
–100
–150
50
20 40 60 100 120
TEMPERATURE (ºC)
I
S
(OFF) + – I
D
(OFF) +
I
S
(OFF) – + I
D
(OFF) – +
I
D
, I
S
(ON) + + I
D
, I
S
(ON) – –
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1/10V
Figure 10. Leakage Currents vs. Temperature, Single Supply
120
0
0
06576-021
LOGIC LEVEL, IN (V)
I
DD
(µA)
V
DD
= 12V
V
SS
= 0V
V
DD
= +15V
V
SS
= –15V
I
DD
PER CHANNEL
T
A
= 25ºC
100
80
60
40
20
2 4 6 8 10 12 14
Figure 11. IDD vs. Logic Level, IN
0.5
–0.5
–15 15
06576-022
SOURCE VOLTAGE (V)
CHARGE INJECTION (pC)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–10 –5 0 5 10
T
A
= 25ºC
V
DD
= +15V
V
SS
= –15V
V
DD
= +5V
V
SS
= –5V
V
DD
= 12V
V
SS
= 0V
Figure 12. Charge Injection vs. Source Voltage
300
0
–40 120
06576-023
TEMPERATURE (ºC)
t
ON
/
t
OFF
TIMES (ns)
250
200
150
100
50
–20 0 20 40 60 80 100
15V DS t
ON
15V DS t
OFF
12V SS t
ON
12V SS t
OFF
Figure 13. tON/tOFF Times vs. Temperature
–120
10k 1G
06576-016
FREQUNCY (Hz)
OFF ISOLATION (dB)
100k 1M 10M 100M
–20
–40
0
–60
–80
–100
V
DD
= 15V
V
SS
= –15V
T
A
= 25ºC
Figure 14. Off Isolation vs. Frequency
ADG1201 Data Sheet
Rev. A | Page 10 of 14
–14
10k 1G
06576-0017
FREQUNCY (Hz)
INSERTION LOSS (dE)
100k 1M 10M 100M
0
–2
–4
–6
–8
–10
–12
V
DD
= 15V
V
SS
= –15V
T
A
= 25ºC
Figure 15. Insertion Loss vs. Frequency
FREQUENCY (Hz)
THD + N (%)
10
1
0.1
0.01
10 100 1k 10k 100k
R
L
= 10kΩ
T
A
= 25°C
V
DD
= +5V, V
SS
= –5V, V
S
= +3.5V rms
V
DD
= +15V, V
SS
= –15V, V
S
= +5V rms
06576-024
Figure 16. THD + N vs. Frequency
2
–15 15
06576-018
INPUT VOLTAGE (V)
CAPACITANCE (pF)
6
5.5
5
4.5
4
3.5
3
2.5
–10 –5 0 5 10
SOURCE/DRAIN ON
SOURCE OFF
DRAIN OFF
V
DD
= 15V
V
SS
= –15V
T
A
= 25ºC
Figure 17. Capacitance vs. Input Voltage, Dual Supply
2
012
06576-019
INPUT VOLTAGE (V)
CAPACITANCE (pF)
6
5.5
5
4.5
4
3.5
3
2.5
246810
SOURCE/DRAIN ON
SOURCE OFF
DRAIN OFF
V
DD
= 12V
V
SS
= 0V
T
A
= 25ºC
Figure 18. Capacitance vs. Input Voltage, Single Supply
0
–100
100k 1M 10M
06576-025
FREQUENCY (Hz)
AC PSRR (dB)
100M
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
DD
= +15V
V
SS
= –15V
V p-p = 0.63V
T
A
= 25ºC
DECOUPLING CAPACITORS ON
NO DECOUPLING CAPACITORS ON
Figure 19. AC Power Supply Rejection Ratio (AC PSRR) vs. Frequency
Data Sheet ADG1201
Rev. A | Page 11 of 14
TEST CIRCUITS
I
DS
V1
SD
V
S
R
ON
= V1/I
DS
06576-008
Figure 20. On Resistance
SD
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
06576-009
Figure 21. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
06576-010
Figure 22. On Leakage
VOUT
50Ω
NETWORK
ANALYZER
RL
50Ω
IN
VIN
S
D
50Ω
OFF ISOLATION = 20 LOG
VOUT
VS
VS
VDD VSS
0.1µF
V
DD
0.1µF
VSS
GND
06576-013
Figure 23. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
IN
V
IN
S
D
INSERTION LOSS = 20 LOG
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
06576-014
Figure 24. Bandwidth
V
OUT
R
S
AUDIO PRECISION
R
L
10kΩ
IN
V
IN
S
D
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
06576-015
Figure 25. THD + N
ADG1201 Data Sheet
Rev. A | Page 12 of 14
V
S
IN
SD
GND
R
L
300Ω
C
L
35pF
V
OUT
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
ADG1201
V
IN
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
06576-011
Figure 26. Switching Times
IN
V
OUT
ADG1201
V
IN
V
OUT
OFF
ΔV
OUT
ON
Q
INJ
= C
L
× ΔV
OUT
S D
V
DD
V
SS
V
DD
V
SS
V
S
R
S
GND
C
L
1nF
06576-012
Figure 27. Charge Injection
Data Sheet ADG1201
Rev. A | Page 13 of 14
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
tON
The delay between applying the digital control input and the
output switching on. See Figure 26.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 26.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to avoid coupling noise
and spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated by a
sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the
output to the amplitude of the modulation is the AC PSRR.
ADG1201 Data Sheet
Rev. A | Page 14 of 14
OUTLINE DIMENSIONS
1 3
45
2
6
2.90 BS C
1.60 BSC 2.80 BS C
1.90
BSC
0.95 BSC
0.22
0.08 10°
0.50
0.30
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.60
0.45
0.30
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 28. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADG1201BRJZ-R2 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S25
ADG1201BRJZ-REEL7 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S25
1 Z = RoHS Compliant Part.
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D06576-0-1/19(A)