FEATURES FUNCTIONAL BLOCK DIAGRAM 2.4 pF typical off switch source capacitance, dual supply <1 pC charge injection Low leakage: 0.6 nA maximum at 85C 120 typical on resistance at 25C, dual supply Fully specified at 15 V, +12 V No VL supply required 3 V logic-compatible inputs VINH = 2.0 V minimum VINL = 0.8 V maximum Rail-to-rail operation 6-lead SOT-23 package ADG1201 S D IN SWITCH SHOWN FOR A LOGIC 1 INPUT 06576-001 Data Sheet Low Capacitance, Low Charge Injection, 15 V/+12 V, iCMOS, SPST in SOT-23 ADG1201 Figure 1. APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems GENERAL DESCRIPTION The ADG1201 is a monolithic complementary metal-oxide semiconductor (CMOS) device containing a single-pole, single-throw (SPST) switch designed in an iCMOS(R) process. iCMOS is a modular manufacturing process combining a high voltage CMOS and bipolar technologies. iCMOS enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of this switch makes it an ideal solution for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth also makes the device suitable for video signal switching. Rev. A iCMOS construction ensures ultra low power dissipation, making the device ideally suited for portable and batterypowered instruments. The ADG1201 contains a SPST switch. Figure 1 shows that with a logic input of 1, the switch of the ADG1201 is closed. The switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Ultralow capacitance. <1 pC charge injection. Ultralow leakage. 3 V logic-compatible digital inputs: VINH = 2.0 V minimum, VINL = 0.8 V maximum. No logic voltage (VL) power supply required. SOT-23 package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2008-2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADG1201 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 Thermal Resistance .......................................................................6 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................6 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................7 Product Highlights ........................................................................... 1 Typical Performance Characteristics ..............................................8 Revision History ............................................................................... 2 Test Circuits..................................................................................... 11 Specifications..................................................................................... 3 Terminology .................................................................................... 13 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 14 Single Supply ................................................................................. 4 Ordering Guide .......................................................................... 14 REVISION HISTORY 1/2019--Rev. 0 to Rev. A Deleted ADG1202 .............................................................. Universal Changes to Features Section and Product Highlights Section ... 1 Changes to Table 1 ............................................................................ 3 Changes to Absolute Maximum Ratings Section and Table 3 .... 6 Added Thermal Resistance Section ............................................... 6 Added Table 4; Renumbered Sequentially .................................... 6 Changes to Figure 3 Caption to Figure 8 Caption........................ 8 Changes to Figure 9 Caption, Figure 10 Caption, and Figure 11 Caption ............................................................................. 9 Changes to Figure 15 Caption and Figure 19 Caption .............. 10 Changes to Figure 26 and Figure 27............................................. 12 Changes to Ordering Guide .......................................................... 14 2/2008--Revision 0: Initial Version Rev. A | Page 2 of 14 Data Sheet ADG1201 SPECIFICATIONS DUAL SUPPLY VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Flatness (RFLAT(ON)) 25C Drain Off Leakage (ID (Off )) Channel On Leakage (ID, IS (On)) DIGITAL INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IINL or IINH) -40C to +125C VDD to VSS 120 200 240 270 20 60 LEAKAGE CURRENTS Source Off Leakage (IS (Off )) -40C to +85C Off Time (tOFF) Charge Injection Off Isolation Total Harmonic Distortion + Noise (THD + N) -3 dB Bandwidth Off Switch Source Capacitance (CS (Off )) Off Switch Drain Capacitance (CD (Off )) On Switch Capacitance (CD, CS (On)) V typ max typ 72 79 0.004 nA typ 0.1 0.004 0.1 0.04 0.6 1 0.6 1 0.15 0.6 Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V Analog voltage on Terminal S (VS) = 10 V, source leakage current (IS) = -1 mA, see Figure 20 VS = -5 V, 0 V, and +5 V, IS = -1 mA max nA max nA typ nA max nA typ 1 nA max 2.0 0.8 2.5 V min V max A typ A max pF typ 140 ns typ 0.005 0.1 Digital Input Capacitance (CIN) DYNAMIC CHARACTERISTICS 1 On Time (tON) Unit VDD = +16.5 V, VSS = -16.5 V VS = 10 V, analog voltage on Terminal D (VD) = 10 V, see Figure 21 VS = 10 V, VD = 10 V, see Figure 21 VS = VD = 10 V, see Figure 22 Voltage on IN pin (VIN) = VINL or VINH 80 0.15 dB typ % typ Load resistance (RL) = 300 , load capacitance (CL) = 35 pF VS = 10 V, see Figure 26 RL = 300 , CL = 35 pF VS = 10 V, see Figure 26 VS = 0 V, supply resistance (RS) = 0 , CL = 1 nF, see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 23 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz 660 2.4 MHz typ pF typ RL = 50 , CL = 5 pF, see Figure 24 VS = 0 V, frequency = 1 MHz 3 2.8 pF max pF typ VS = 0 V, frequency = 1 MHz VS = 0 V, frequency = 1 MHz 3.3 4.7 pF max pF typ VS = 0 V, frequency = 1 MHz VS = 0 V, frequency = 1 MHz 5.6 pF max VS = 0 V, frequency = 1 MHz 170 90 105 -0.8 200 230 130 141 ns max ns typ ns max pC typ Rev. A | Page 3 of 14 ADG1201 Data Sheet Parameter POWER REQUIREMENTS Positive Supply Current (IDD) 25C -40C to +85C -40C to +125C 0.001 1.0 IDD 60 95 Negative Supply Current (ISS) 0.001 1.0 5 to 16.5 VDD/VSS 1 Unit A typ A max A typ A max A typ A max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V, or VDD GND = 0 V Guaranteed by design, not subject to production test. SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range RON RFLAT(ON) LEAKAGE CURRENTS IS (Off ) ID (Off ) ID, IS (On) DIGITAL INPUTS VINH VINL IINL or IINH 25C 300 475 60 0.006 0.1 0.006 0.1 0.04 0.15 -40C to +85C -40C to +125C Unit 0 V to VDD V typ max typ 567 625 0.6 1 0.6 1 0.6 1 2.0 0.8 0.001 0.1 CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Charge Injection Off Isolation -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) 3 190 250 120 155 0.8 80 295 340 190 210 520 2.7 3.3 3.1 3.6 5.3 6.3 nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max pC typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max Rev. A | Page 4 of 14 Test Conditions/Comments VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -1 mA, see Figure 20 VS = 3 V, 6 V, and 9 V, IS = -1 mA VDD = 13.2 V, VSS = 0 V VS = 1 V or 10 V, VD = 10 V or 1 V, see Figure 21 VS = 1 V or 10 V, VD = 10 V or 1 V, see Figure 21 VS = VD = 1 V or 10 V, see Figure 22 VIN = VINL or VINH RL = 300 , CL = 35 pF VS = 8 V, see Figure 26 RL = 300 , CL = 35 pF VS = 8 V, see Figure 26 VS = 6 V, RS = 0 , CL = 1 nF, see Figure 27 RL = 50 , CL = 5 pF, frequency = 1 MHz, see Figure 23 RL = 50 , CL = 5 pF, see Figure 24 VS = 6 V, frequency = 1 MHz VS = 6 V, frequency = 1 MHz VS = 6 V, frequency = 1 MHz VS = 6 V, frequency = 1 MHz VS = 6 V, frequency = 1 MHz VS = 6 V, frequency = 1 MHz Data Sheet Parameter POWER REQUIREMENTS IDD ADG1201 25C -40C to +85C -40C to +125C 0.001 1.0 IDD 60 VDD 1 95 5 to 16.5 Guaranteed by design, not subject to production test. Rev. A | Page 5 of 14 Unit A typ A max A typ A max V min/max Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V ADG1201 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 3. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Temperature Industrial Range Storage Range Junction Reflow Soldering Peak, PbFree 1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 30 mA -40C to +125C -65C to +150C 150C 260C JA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 4. Thermal Resistance Package Type RJ-61 1 JA 229.6 JC 91.99 Unit C/W Thermal impedance values measured on a JEDEC 1S2P thermal test board. See JEDEC JESD-51. ESD CAUTION Overvoltages at IN, S, or D are clamped by internal diodes. Current must be limited to the maximum ratings given. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 6 of 14 Data Sheet ADG1201 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 VSS 3 IN 5 D TOP VIEW (Not to Scale) 4 S 06576-002 GND 2 6 ADG1201 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VDD GND VSS S D IN Description Most Positive Power Supply Potential. Ground (0 V) Reference. Most Negative Power Supply Potential. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Logic Control Input. Table 6. ADG1201 Truth Table IN 1 0 Switch Condition On Off Rev. A | Page 7 of 14 ADG1201 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 250 200 VDD = +15V VSS = -15V TA = +25C 180 VDD = +13.5V VSS = -13.5V 200 140 ON RESISTANCE () 120 100 VDD = +15V VSS = -15V 80 VDD = +16.5V VSS = -16.5V 60 40 TA = +125C 150 TA = +85C 100 TA = +25C TA = -40C 06576-003 50 20 0 -18 -15 -12 6 0 9 -3 3 -9 -6 SOURCE OR DRAIN VOLTAGE (V) 12 15 0 -15 18 Figure 3. On Resistance vs. Source or Drain Voltage, Dual Supply 06576-006 ON RESISTANCE () 160 5 -5 0 SOURCE OR DRAIN VOLTAGE (V) -10 15 Figure 6. On Resistance vs. Source or Drain Voltage, Different Temperatures, Dual Supply 450 600 VDD = +12V VSS = 0V TA = +25C 400 TA = +125C 500 350 TA = +85C ON RESISTANCE () ON RESISTANCE () 10 VDD = +5.5V VSS = -5.5V 300 250 200 150 400 300 200 TA = -40C 100 TA = +25C 50 0 -5 -4 -3 -2 -1 2 0 1 3 SOURCE OR DRAIN VOLTAGE (V) 4 0 0 5 Figure 4. On Resistance vs. Source or Drain Voltage, Dual Supply 2 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 10 12 Figure 7. On Resistance vs. Source or Drain Voltage, Different Temperatures, Single Supply 200 TA = 25C 100 LEAKAGE CURRENT (pA) VDD = 12V VSS = 0V VDD = 10.8V VSS = 0V 350 300 250 VDD = 13.2V VSS = 0V 200 VDD = +15V VSS = -15V VBIAS = 10V 150 400 150 100 50 0 -50 -100 -150 -200 -250 -300 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + 06576-005 -350 50 0 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) -400 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 06576-028 450 ON RESISTANCE () 06576-007 06576-004 100 -450 12 0 20 40 60 80 TEMPERATURE (C) 100 120 Figure 8. Leakage Current vs. Temperature, Dual Supply Figure 5. On Resistance vs. Source or Drain Voltage, Single Supply Rev. A | Page 8 of 14 Data Sheet ADG1201 0.5 150 VDD = +5V VSS = -5V VBIAS = 4.5V 0.4 CHARGE INJECTION (pC) 0 -50 -100 -150 0 40 0.1 0 -0.2 80 60 TEMPERATURE (C) 100 -0.5 -15 120 0 5 10 15 300 200 250 tON/tOFF TIMES (ns) 150 100 50 0 -50 -100 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -150 0 20 40 15V DS tOFF 15V DS tON 12V SS t OFF 12V SS t ON 200 150 100 50 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 06576-027 80 60 TEMPERATURE (C) 100 0 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 13. tON/tOFF Times vs. Temperature Figure 10. Leakage Currents vs. Temperature, Single Supply 0 120 IDD PER CHANNEL TA = 25C -20 OFF ISOLATION (dB) 100 80 60 VDD = +15V VSS = -15V 40 VDD = 12V VSS = 0V 0 2 4 6 -40 -60 -80 -100 06576-021 20 VDD = 15V VSS = -15V TA = 25C 8 10 12 -120 10k 14 06576-016 LEAKAGE CURRENT (pA) -5 Figure 12. Charge Injection vs. Source Voltage VDD = 12V VSS = 0V VBIAS = 1/10V 250 IDD (A) -10 SOURCE VOLTAGE (V) 300 0 VDD = +5V VSS = -5V -0.4 Figure 9. Leakage Currents vs. Temperature, Dual Supply -200 VDD = 12V VSS = 0V -0.1 -0.3 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 20 0.2 06576-023 -250 VDD = +15V VSS = -15V 06576-022 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -200 TA = 25C 0.3 50 06576-026 LEAKAGE CURRENT (pA) 100 100k 1M 10M 100M FREQUNCY (Hz) LOGIC LEVEL, IN (V) Figure 14. Off Isolation vs. Frequency Figure 11. IDD vs. Logic Level, IN Rev. A | Page 9 of 14 1G ADG1201 Data Sheet 0 6 VDD = 15V VSS = -15V TA = 25C 5.5 SOURCE/DRAIN ON 5 -4 CAPACITANCE (pF) -6 -8 -10 VDD = 12V VSS = 0V TA = 25C 4.5 4 3.5 DRAIN OFF 3 -14 10k 2.5 06576-0017 -12 100k 1M 10M 100M 2 1G SOURCE OFF 0 2 FREQUNCY (Hz) 4 06576-019 INSERTION LOSS (dE) -2 6 8 12 10 INPUT VOLTAGE (V) Figure 15. Insertion Loss vs. Frequency Figure 18. Capacitance vs. Input Voltage, Single Supply 0 10 RL = 10k TA = 25C -10 -20 VDD = +15V VSS = -15V V p-p = 0.63V TA = 25C NO DECOUPLING CAPACITORS ON -30 AC PSRR (dB) THD + N (%) 1 VDD = +5V, VSS = -5V, VS = +3.5V rms VDD = +15V, VSS = -15V, VS = +5V rms 0.1 -40 -50 -60 DECOUPLING CAPACITORS ON -70 0.01 10 100 1k FREQUENCY (Hz) 10k 100k VDD = 15V VSS = -15V TA = 25C SOURCE/DRAIN ON 4.5 4 3.5 DRAIN OFF 2 -15 06576-018 CAPACITANCE (pF) 5 2.5 SOURCE OFF -10 -5 0 1M 10M 100M Figure 19. AC Power Supply Rejection Ratio (AC PSRR) vs. Frequency 6 3 -90 -100 100k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency 5.5 06576-025 06576-024 -80 5 10 15 INPUT VOLTAGE (V) Figure 17. Capacitance vs. Input Voltage, Dual Supply Rev. A | Page 10 of 14 Data Sheet ADG1201 TEST CIRCUITS VDD VSS 0.1F 0.1F VDD NETWORK ANALYZER VSS S IDS 50 50 IN VS D VIN S GND D 06576-008 RON = V1/IDS VS RL 50 VOUT OFF ISOLATION = 20 LOG Figure 20. On Resistance VOUT VS 06576-013 V1 Figure 23. Off Isolation VDD VSS 0.1F 0.1F VDD NETWORK ANALYZER VSS S 50 IN VS D D VIN ID (OFF) A VS RL 50 GND VD INSERTION LOSS = 20 LOG Figure 21. Off Leakage VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH 06576-014 A S 06576-009 IS (OFF) Figure 24. Bandwidth VDD VSS 0.1F 0.1F VDD AUDIO PRECISION VSS RS S IN ID (ON) D NC = NO CONNECT A VD VIN GND Figure 22. On Leakage RL 10k Figure 25. THD + N Rev. A | Page 11 of 14 VOUT 06576-015 S 06576-010 NC VS V p-p D ADG1201 Data Sheet VDD VSS 0.1F ADG1201 50% 50% VOUT D S VS VIN VSS VDD CL 35pF RL 300 IN 90% VOUT tOFF tON GND 90% 06576-011 0.1F Figure 26. Switching Times VSS VDD VSS VIN ADG1201 ON RS VS S D CL 1nF IN OFF VOUT VOUT GND Figure 27. Charge Injection Rev. A | Page 12 of 14 QINJ = CL x VOUT VOUT 06576-012 VDD Data Sheet ADG1201 TERMINOLOGY IDD The positive supply current. CIN The digital input capacitance. ISS The negative supply current. tON The delay between applying the digital control input and the output switching on. See Figure 26. VD (VS) The analog voltage on Terminal D and Terminal S. tOFF The delay between applying the digital control input and the output switching off. See Figure 26. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. ID (Off) The drain leakage current with the switch off. Bandwidth The frequency at which the output is attenuated by 3 dB. ID, IS (On) The channel leakage current with the switch on. On Response The frequency response of the on switch. VINL The maximum input voltage for Logic 0. Insertion Loss The loss due to the on resistance of the switch. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (AC PSRR) AC PSRR measures the ability of a device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the AC PSRR. Rev. A | Page 13 of 14 ADG1201 Data Sheet OUTLINE DIMENSIONS 2.90 BSC 6 5 4 1 2 3 2.80 BSC 1.60 BSC PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 1.45 MAX 0.50 0.30 0.15 MAX 0.22 0.08 SEATING PLANE 10 4 0 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 28. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG1201BRJZ-R2 ADG1201BRJZ-REEL7 1 Temperature Range -40C to +125C -40C to +125C Package Description 6-Lead Small Outline Transistor Package [SOT-23] 6-Lead Small Outline Transistor Package [SOT-23] Z = RoHS Compliant Part. (c)2008-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06576-0-1/19(A) Rev. A | Page 14 of 14 Package Option RJ-6 RJ-6 Marking Code S25 S25