November 1993 mm) at FiARRIS SEMICONDUCTOR NOT RECOMMENDED FOR NEW DESIGN Features * 8,000 Hours Typical 9V Battery Lite * Guaranteed Zero Reading tor oV input on All Scales * True Polarity at Zero for Precise Null Detection * 1pA Typical Input Current * True Differential Input and Reference * Direct LCD Display Drive - No External Components Required * Pin Compatibie With the ICL7106 * Low Nolse - Less Than 5uVp.p * On-Chip Clock and Reference * Low Power Dissipation Guaranteed Less Than mW * No Additional Active Circuits Required Ordering Information TEMPERATURE 246-859 ICL7126 3"/p Digit Low Power Single-Chip A/D Converter Description The ICL7126 is 3 high performance, very low power 31, digit A/D converter, All the necessary active devices are con- tained on a single CMOS IC, including seven segment decoders, display drivers, reference, and clock. The ICL7126 is designed to interface with a liquid crystal display (LCD; and includes a tackpiane drive. The supply current of 100uA is ideally suited tor 9V battery operation. The ICL7126 briras tagether an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10uV, zero drift of less than Tuvc, input bias current of 10pA maximum, and rollover error of less than one ccunt. The versatility of true differential input and reference is Useful in all systems, but gives the designer an uncommon advantage when measuring load cells, strain gauges and other bridge-type transducers, And finally the true economy of single power Operation allows a high perfor- mance panel meer or multi-meter to be built with the addi- tion of only 10 passive components and a display. The ICL7126 can be used as a plug-in replacement for the PART NUMBER RANGE PACKAGE ICL7126CPL 0C to 470C 40 Lead Plastic DIP ICL7126RCPL 07C ta +70C 90 Lead Plastic DIP ICL7106 in a wide variety of applications, changing only the passive components. " Ro indicates darice with reversed leads. Pinout ICL7126 (PDIP) TOP View vO} 40] osc 1 fo: | 39] Osc C1 [3] 38] OSC3 Bt [4] 37| TEST (1's)4 ar CB] [36] REF HI Fi [el asf REFLO @1 (7) 34] Ceere e1 [a] 33] Cage: o2 [9] [32} COMMON ce {iol 31] IN HI (10's) 4 82 ta] [30] LO az [3] [2g] A-2 Fe [ia] 22) BUFF e2 [ta] [27] INT D3 Gs] 26 | ve Ba (i6 [25] G2 (10's) (100"8) Fa = 24] c3 es [ig] 23] a3 > (100's) (1000) ABs [19] 22] Ga Pat [Ro| [21] BPGNO (MINUS) PETE RVEG Copyaght Harris Capoution 13993 FROM CAUTION: These devices are sensitive to electrostatic dischargeUsers should bllow proper iC Handling 1 3084 2racedures File Number m Llheos, ras graySpecifications ICL7126 Absolute Maximum Ratings Supply oltage V+ to Vv. a Analog Input Veltage (Either Input) (Note 2)... Reference Input Voltage (Either Inpul)........ Clock Input. . CAUTION. Stresses above those listed in Absolute Maximum Aatings may cause permanent damage to Thermal Information 15V Thermal Resistance Stoage Temperature Range Lead Temperature (Soideing 10 Sec Max) Junction Temperature Veto V 40 Lead Plastic Package . Veto Maximum Power Dissisation (Note tj) .. .... TEST to V+ Opemting Temserature Range.... of the device at these or ary other conditions above those indicated in the operational sections of this spec:fication is not implied. y. C 260m ... Cte 670C 65C te -150C +300C +150C the device. This is a stress only rating and aperation Electrical Specifications 1. 425C. Vecz = 100mV. f-_--, + 48kHz, (Note 2. 3) LIMITS PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading V- 2 O.0V, Full-Scale 200mvV 7000.0 | 2000.0 | +000.0 Cigital Reading Ratiometric Reading Vila Vees, Verso 100mV 999 999/ 1000 Cigital 1009 Reading Rollover Error Vieja Vn, 200mV - 20.2 21 Counts Difference in Reading for Equal Positive and Negative inputs Near Full-Scale Linearity Full-Scale 200mV or Full-Scale 2V - 20.2 1 Counts Maximum Deviation from Best Straight Line Fit (Note 5} Common Mode Rejection Ratio Vays s STV Vo, 2 OV Full-Scale 200mV . 50 : Viv (Note 5) Noise V.,, 2 OV, Full-Seale = 200mV - 15 : eV (Pk-Pk Value Not Exceeded 95% of Time} (Note 5) Leakage Current Input Vin 2 0 (Note 5) 1 190 pa Zero Reading Oritt Vis 2 0. 07 < T, < #70C (Note 3) - 0.2 1 eVFC Scale Factor Temperature Coefficient Vip2 199mV, T.+70C. + 1 5 pomhc (Ext. Ref. OppmfC) (Note 5) Ve Supply Current V:, 20 (Does Not Include COMMON : 70 100 uA Current} COMMON Pin Analog Common Voltage 25kQ Between Common and 2.4 2.8 3.2 v Positive Supply (With Respect ta + Supply) Temperature Coefficient of Analag Common 25k Between Common and 80 pomPC Positive Supply (With Respect ta + Supply) (Note 5) Pk-Pk Segment Orive Voltage Vee to V- 2 9V. (Note 4) 4 5 6 Vv Pk-Pk Backplane Orive Voltage Power Dissipation Capacitance vs Clock Frequency : 40 . pF NOTES: 1. Dissipation rating assumes device is mounted with ailleads soldered to printed circuit board, ah YN . Unless otherwise noted. specifications are tested using the circuit of Figure 1. fate. Average OC componentis less than 50mV. 5. Nottested guaranteed by design. . Input voltages may exceed the supply voltages provided the input current is limitet000 uA. . Back plane drive is in phase with segment drive for off segment. 180o0ut of phase for-on segment. Frequenc y is 20 times conversion FECEINED FROMICL7126 Typical Applications Schematic a Ay c, 3 SopF Cy * O.1uF 3 C, = 0.22uF Cy = 0.047 uF PIBIEIGIEIE Gq ~ S0pF ~~. ok FO Cs = 0.01uF gag ae z Ry = 240k ooor gw Rp = 180k01 Ry = 180k12 P Rg = 10ks2 ~ Re = 1MSz >a405R 46 2 WSS g FIGURE 1. ICL7126 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FILL- SCALE SET AEF = 100.0mv C, =0.1pF Cz = 0.33 uF Cy = 0. 5uF wel [en afm C, = 50pF SS = Cs = 0.01uF = 9 GS R, = 240kn wt Rz = 180ka Ry = 180ks2 ? Ra = 10k2 Rs = IMn 2464426 TEE FIGURE 2. ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/SEC Go FECELUEG FFon LL. 2G. 1S55 ftorga F.ICL7126 Typical Applications Schematic (continued) tH . Ay Hs 240K, 1M: Ay c, z SopF C, = 0.1uF 3 Cy = 0.22uF = Cy = 0.047 uF FIBIEIBIBIEIEIEIEIE Ca * SOpF = _ Cs = O.01uF me Fortu = i] : geggat hes R, = 240k2 oo or eH ee Ry = 180k1 > Ry = 180k) 1CL.7126 Ra = 10ki2 rT = Rs = 1MQ. cree eee s SSS SETETDESE tes sege 2 Bs = Si cHsd[all e[pelfofIcia mS 7PEEEEEEEEEEEREEEE DISPLAY FIGURE 3. CLOCK FREQUENCY 48kH2z, 3 READINGS/SEC RPEQVEIVEO FROM Ll. fe. pass bo: SoICL7126 Design Information Summary Sheet * OSCILLATOR FREQUENCY fosc = 0.45/RC Cosc > S0pF: Rosc > S0K2 fosc Typ. = 48KHz * OSCILLATOR PERIOD tose = ACI0.45 * INTEGRATION CLOCK FREQUENCY ferock =fosc4 * INTEGRATION PERIOD tint = 1006 x (4/fggc) * 60/S0Hz REJECTION CRITERION tint teon OF tinttsou2 = Integer * OPTIMUM INTEGRATION CURRENT lint = 4.0uA * FULL-SCALE ANALOG INPUT VOLTAGE Vines Typically = 200mV or 2.0V * INTEGRATE RESISTOR a. = JINFS INT Tint - INTEGRATE CAPACITOR Cie = fin Cin INT * INTEGRATOR OUTPUT VOLTAGE SWING Cin) Cay? INT = * Vint MAXIMUM SWING: (V- + 0.5V) < Ving < (V+ - 0.5V), Vint typically = 2.0V Vv DISPLAY COUNT Vin COUNT = 1600. Veer CONVERSION CYCLE teve= terack x 200 teye = tose x 16.300 when fosc = 464KHAZ: teye = 333ms COMMON MODE INPUT VOLTAGE (V- + F.0V} < Vin < {Ve - 0.5V) AUTO-ZERO CAPACITOR O.01uF <Caz< 1.0uF REFERENCE CAPACITOR O.4uF < Cpee < t.0uF Voom Biased between V+ and V-. Voom = V+ -2.8V Regulation lost wien V+ to V- < 26.8V. If Veomis externaily pulled down to (V + to V -/2, the Veoyy circuit will turn off. ICL7126 POWER SUPPLY: SINGLE 9V V+-V-=9V Digital supply is cenerated internally Vrest =V+- 4.5V ICL7126 DISPLAY: LCD Type: Direct drive vith digital logic supply amplitude. SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS AUTO ZERO PHASE (COUNTS) 2999 - 1000 + Typical Integrator Amplifier Output Waveform (INT Pin) DE-INTEGRATE PHASE 0-1999 COUNTS TOTAL CONVERSION TIME = 4000 x teLock = 16,000 x tese FECETVEO FROM or nnICL7126 Detailed Description Analog Section Figure 4 shows the Functional Diagram of the Analag Sec- tion for the ICL7126. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z}, (2) signal inte- grate (INT) and {3} de-integrate (DE). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference Capacitor is charged to the reference voltage. Third, a feedback loop is Closed around the system to charge the auto-zero capacitor Caz to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10uV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-iIntegrate Phase The final phase is 3-integrate, or reterence integraie, Input low is internally ccanected to analog COMMON and input high is connectes across the previously charged reference capaciter, Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator cutput tc -aturn to zero. The time required for the output to return to zero is proportional to the input sianal, Specifically the dic.tal (2ading displayed is . VIN Display Count = +200 _ Veer : Differential Input The input can accsot differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below he positive supply to 1.0V above the negative supply. Ir this range, the system has a CMRA of 86dB typical. However, care must be exercised to assure the integrator output ces not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full- scale swing with littie loss of accuracy. The integrator output can swing to within 0.5V of either supply without loss of linearity. PECELUEL yh TF Caer | Rint Caz Coir Cace$ REF HI REF Lo} Crer> SUFFER y, Taz i Vs 34 36 35 | 33 28 1 29 l 27 A-Z A-Z j INTEGRATOR : TO THA : DIGITAL 3 2.8V SECTION IN HI $1_{K)- ' baa! INT DE- DE+ INPUT y x 6.2V A-Z HIGH A-Z COMPARATOR N 32 DE+ DE- COMMON $ * INPUT A-Z AND DE{2) Low 30 INLO $(&) INT 26 Vv. FIGURE 4. ANALOG SECTION OF ICL7126 FRE Cro li, isl pase bar$3 F.ICL7126 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a larae common made voltage, the ref- erence capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-cver error. However, by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) Analog COMMON This pin is included primarily to set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the power supply, The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a teference voltage. When the total supply voltage is large enough to cause the zener to regulate (<6.8V), the COM- MON voltage will have a low voltage coefficient (0.001%/V), low output impedance (215), and a temperature coefficient typically less than 80ppm/C. The limitations of the on-chip reference should also be recognized, however. The reference Temperature Coefficient (TC), can cause sorne degradation in performance. Tempera- ture changes of 2C to 8C, typical for instruments, can give a scale factor error of a count or more. Also the common volt: age will have a poor voltage coefficient when the total supply voltage is less than that which will cause the zener to regulate (<7V). These problems are eliminated if an external reference is used, as shown in Figure 5. Analog COMMON is also used as the input low return during auto-Zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMAR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode valtage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the IC, analog COMMON is tied to an N channel FET that can sink approximately 3mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 1uA of source current, so COMMON may easily be tied to a mare negative voltage thus overriding the internal reference. Ve Ve REF H! REF > P\ 6.8V EFLO ZENER 1CL7126 [ V (A) Ve V+ 27k ICL7126 REF HI (CLa069 1.2V REF LO + REFERENCE COMMON (B) FIGURE 5. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. It is coupled to the inter- nally generated digital supply through a S00Q resistor. Thus it can be used as the negative supply for externally gener- ated segment crivers such as decimal points or any other presentation the user may want to include on the LCD dis- play. Figures 6 and 7 show such an application. No more than a {mA load should be applied. The second function is a lamp test. When TEST is pulled high (to V+) all segments will be turned on and the display should read *-1388". The TEST pin will sink about 10mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant OC valtage (No square-wave} and may burn the LCO display if lett in this mode for several minutes. Ve TMgx TO LCD DECIMAL POINT ICL7126 | BPO; TEST 7 TOLCO BACKPLANE FIGURE 6. SIMPLE INVERTER FOR FIXED DECIMAL POINT PECELVeEt FRearttMLIITZO -_ 4] V+ bree Ve my ; "| D+ Tt y>+- TOLCO 1CL7126 DECIMAL : DECIMAL POINT - { POINTS SELECT i) : i TEST t t V+=DPON } CD4030 | GND = DP OFF Teno FIGURE 7. EXCLUSIVE 'OR' GATE FOR DECIMAL POINT ORIVE Digital Section Figure 8 shows the digital section for the ICL7126. An internal digital ground is generated from a 6V Zener diode and a large P channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock fre- quency divided by 800. For three readings/second this is a 60Hz square wave with a nominal amplitude of 5V. The seq- ments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. ~ 13300 TYPICAL SEGMENT OUTPUT SEGMENT OUTPUT INTERNAL DIGITAL GR * THREE INVERTERS. cLocK ONE INVERTER SHOWN FOR CLARITY, 1000's NTER TO SWITCH DRIVERS FROM COMPARATOR OUTPUT Me ocierty mcicat c= -3 ON for negative anasc noes, fy & versed, this indication can se reversed also, if desired, System Timing Figure 9 shows tha Clocking arrangement used in the ICL7126. Two basic clecking arrangements can be used: 1. An external oscillator connected to pin 40, 2. An A-C oscillatsr using ail three pins. The oscillator frequency is divided by four before it clocks the decade counters. it is then further divided to form the three convert-cycle ohases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auio- Zero (1000 te 3006 counts}. For signals less than full-scale, auto-Zero gsts the unused portion of reference de-integrate, This makes a complete measure cycle of 4,000 counts (16,000 clock pulses: independent af input voltage. For three readings/second, an oscillator frequency of 48kHz would be usd. To achieve maximum rejection of 6OHz pickup, the signal inte- grate cycle should te a muttiple of 6OHz. Oscillator frequencies Of 60KHz, 48KHz, 4CkHz, 331/;kHz, etc. should be selected. For S0Hz rejection, oscillator frequencies of 66/3kHz, SOkHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readingssecond) will reject both SOHz and 60Hz (also 400Hz and 440H2}. BACKPLANE LCD PHASE DRIVER 7 SEGMENT DECODE 7 SEGMENT DECODE ? SEGMENT DECOOE LATCH Ve LOGIC CONTROL TEST INTERNAL DIGITAL GROUND Vry = 1V V. FIGURE 8. DIGITAL SECTION FECEIUEG FROMICL7126 INTERNAL TO PART p> +4 40 39 38 EXTERNAL SIGNAL TEST tcl7126 INTERNAL TO PART +4 F CLOCK 40 39 33 R Cc | RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS Component Value Selection integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 6uA of quiescent current. They can supply ~iuA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V tull-scale, 1.8MQ is near optimum and similarly a 180kQ for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the rnaxi- mum voltage swing that ensures tolerance build-up will not saturate the integrator swing (approximately. 0.3V fram either Supply). When the analog COMMON is used as a reference, a nominal =2V full-scale integrator swing is fine. For three read- ings/second (48kHz clock} nominal values for Cwr are 0.047uF, for 1/sec (16kHz) 0.15uF. Of course, if different oscil- lator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. The integrating capacitor should have a low dielectric absorption to prevent roll-over errors. While other types may be adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. At three readings/sec, a 7500 resistor should be placed in series with the integrating capacitor, to compensate for comparator delay. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full-scale where noise is very Reference Capacitor A Q.1uF capacitor gives gcod results in most acciicaticns. However, where a large common mode voltage sxists fie. the REF LO pin is not at analog COMMON) and a 200mv scale is used, a larger value is required to prevent roll-over error. Generally 1.0uF will hold the roll-over error to 0.5 count in this instance, Oscillator Components For all ranges ci frequency a 50k capacitor is recommended and the resistor is selected from the approximation equation = i~ ws - For 43kHz clock (3 readingssec), R = 180k Reference Voltage The analog input required to generate full-scale output (2000 counts) is: Viy = 2Veee . Thus, for the 200mV and 2V scale, Vaer should equal 100mvV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, thers will exist a scale factor other than unity between the input voltage and the digital reading. Far instance, in a weighing system, the designer might like to have a full-scale reading when the valtage from the transducer is 0.682V. Instead of dividing the input down to 200mvV, the designer should use the input voltage directly and select Vrez = 0.341V. Suitable values for integrating resistor 330k02 . This makes the system slightly quieter and also avoids a divider network on the input. Another advan- tage of this system occurs when a digital reading of zero is desired for Vj = 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be con- veniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) off- set voltage between COMMON and IN LO. Typical Applications The ICL7126 may be used in a wide variety of configura- tions. The circuits which follow show some of the possibili- ties, and serve te illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Harris Semiconductor. Application Notes A016 Selecting A/D Converters AQ17 The Integrating A/D Converter" Aais Do's and Don'ts of Applying A/D Converters A023 Low Cost Digital Panel Meter Designs AQ32 Understanding the Auto-Zero and Common Mode Performance of the ICL7106/7/9 Family Building a Gattery-Operated Auto Ranging OVM with the ICL7106" A046 | important, a 0.32uF capacitor is recommended. On the 2V scale, aos2 Tips for Using Single Chip 31/, Digit AYO Converters a 0.33uF capacitor increases the speed of recovery fram aver- load and is adequate for noise on this scale. 9 FECELUE FROM Li. 29.45295 pa:sa FoiuICL7126 Typical Applications ae} OSC t jaa) 180K02 OSC 2 [39+Www 4 osc 3 {33-1 Vace Test [37] SopF y 7 10mV REF HI ss} Caer 34}+-_ TOK =220Ki. O.1uF Caer [33+ COMMON [32}-_+ ima |, IN Hi [34}-+-,_wt-o I 0.01uF A-Z [29}]>__ BUFF Fg} ww rt_4 INT ]27, V- (26 G2 [25] cs {2q] A3 [23] G3 [22] BP |2}- To BACKPLANE rd aT < 750KQ 0.047uF TO DISPLAY Values shown are for 200mV full-scale 3 readings/sec.. floatinc supply witage (9V battey). FIGURE 10. 1CL7126 USING THE INTERNAL REFERENCE ee -_ osc 1 [ag}__ 560K:2 osc 2 [39 Osc3 set4 ; SET Vacs TEST |37 P = 100mV a7] 20K Y " REF HI ss} Ve [38}>- iyo Vs Caer [34] 200KS 27Ki1 0.1.F Caer [33+-T COMMON [32+____4 aa . IN HI {33}-___ _ =F 0.01ue IN INLO 130) 0.33 uF - : BUFF [2a+-VWA +4 int [27}-_}-__ V- {26} pL G2 [2s] 24] c3 [24 A3 [23 G3 [2] GND [21 IN LO is tied to COMMON, thus estalishing the carrect commor mode voltage. COMMON acts as a Pre-regulator dr the reference. Values shawn are for; readings/sec. FIGURE 11. 1CL7126 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) PECEIVEG FROM 10 hs adICL 7126 Typical Applications (continued) OSci OSc2 Osc 3 TEST REF HI Ve Caer Creer COMMON IN HI INLO A-Z BUFF iNT Ye G2 C3 A3 G3 GND 180KL2 39} w+ SET Vaer i = 1.000V r vv V"*-0 V+ 250K = 240Kiz IS] TSIL] FUL L-SCALE IMa . sap tO = 0.01uF IN Soy 0.22uF . a} ji-_ 1.8Mgy Fg} 2n_f 27-ww-{ KJ pg} P500 0.047 uF oy" TO DISPLAY zif}>-_ TOBACK PLANE at 3 reading/sec. For 1 reading/sec., delete 75@2 resistor change Cons Risse to values of Figure 11. FIGURE 12. RECOMMENDED COMPONENT VALUES FOR 2.0 OSC1 Osc 2 Osc 3 TEST REF Hi V+ Crer Cage COMMON IN HI INLO A-Z BUFF INT yY- G2 c3 A3 G3 GND st 20K TO DISPLAY J 2 100m y = 0.01uF _ SET Vaer NAA O45 V CK] 27KR 1.2V (ICLg069) 1M zt} Ta BACK PLANE An extemal reference must be used in this application. since th. voltage betveen V+ and V- is insufficient br correct opeation of the intemal reference. * indiates values depend on clo& frequency FIGURE 14. 1CL7126 OPERATED FROM SINGLE +5V SUPPLY eset [ao} 100K22 osc 2 [39+ AW osc 3 [3g}7-j-___ SET Vaer TEST [37] 100pF = 100mV REF Hi [sg] -4}$, Ve is} m945V TKO 0K] 15Ke1 Caer (34+-y REE O.tyF 4 Cage (33 1.2V (ICL2069) COMMON [32}__4 Ma . IN Hi [31}- > W o INLO s0}~ a 0.01uF ns IN 0.47uF - az fal] 47K. BUFF |[23-~~w+4 INT [27-] 0.22uF v- [2g}-0-22uF G2 [25] cs [za ad TO DISPLAY as fa 63 [22] a __ ak Since lov TC zeners have breakdown voltages -6.8V. diode must be placed across the total supply (10V). As in the case of Figure 1 IN LO may be tie? to COMMON. FIGURE 13. ICL7126 WITH ZENER DIODE REFERENCE * a} 4 o V+ ose1 OSCc2 OSC 3 TEST REF HI Ve Cree Caer COMMOM IN HI INLO AZ BUFF INT Vv. G2 TO DISPLAY A3 G3 GND 22] st 21} TO BACK PLANE The resistor values within the bidge are detemined by the desirec sensitivity "indicates values depend on cloak frequency FIGURE 15. ICL7126 MEASURING RATIOMETRIC VALUES OF QUAD LOAD CELL FECELUEG FROMICL7126 Typical Applications (Continued) ee Ose 3 SCALE TEST SOpF yp FACTOR REF HI ADJUST Ve f TVA i ' Caer 100k22 1Mz 4 rake c 200kK2 470kr2 REF COMMON +. IN HI ZERO SILICOM NPN ADJUST MPS 3704 OR INLO SIMILAR Az lt BUFF = QV INT + V- G2 c3 A3 FIGURE 16. ICL7126 USED AS A DIGITAL CENTIGRADE THERMOMETER < + r [2] os TO Logic 31 ct vo [3] c Osc 3 [4] 81 TEST [Ss] ar REF HI [6] Fi REF LO To 7} G1 LOGIC [7] Caer [34] GND [a] es Cage [3] oz COMMON [ra] c2 IN Hi a b> @ Non OR @ Ss @ z a Pe aN 0 oo @ q) ny = AREER omanss Cer U RANGE | CRe CD4023 OR Ct 74C10 04077 FIGURE 17. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM !CL7126 OUTPUTS moa ew WwW b> & 8 EIRENE SQCElVEG FRM LL. fe. pgs piegs PLItICL7126 Typical Applications (continued) <= - TOPIN1 osc 1 40} ] osc 2 [3a3+ww_+ T 10 pF SCALE FACTOR ADJUST OSC3 138 (Vaer = 100m V FOR AC TO RMS) 50pF (CL7611 TEST [37} uf 5u REF Hi [s}+-_ ,. . 1NO14 REF LO [3}-7+- i$ nv p TOK | 220KR ; Cree [34--_ en [33} TT" " 2.2Mfi uF 10Ksz Tur 10K == tuF I 4.3K | | i ft Cres 133 WY +. +} COMMON [32/-__ a9 Le 3] pai 0.22yF Ly | IN HI INLO {30} av 100pF (FOR OPTIMUM BANOWIDTH) a2 fa IT ox] BUFF [283}--ww-4 | 10pF 75082 int [27}-WA Alt fit v- [26} ; G2 [25] os Fa ey] TOvisPLay 2] A3 G3 BP {21 TO BACKPLANE a | Testis used as a common-mode reference level to ensure compatibility with most op amps FIGURE 18. AC TO DG CONVERTER WITH ICL7125 an roy Dot he RECEIVED FROM ti. lslissICL7126 Die Characteristics DIE DIMENSIONS: 127 x 149 Mils METALLIZATION: Type: Al . . Thickness: 10kA = 1kA GLASSIVATION: Type: PSG Nitride Thickness: 15kA + 3kA WORST CASE CURRENT DENSITY: 9.1 x 104Aem?2 Metallization Mask Layout os) |e a a B, (16) alt 1 Ty) Met. BP/GND (21) G3 (22) ' -} A; (23) Cy (24) G, (25) eLia al = nN a a wets(jos uw? | wn Ih ea oe 18 zal =, mi 2M, z | a oo AB, (19) Ng 1 ti crea Tianna POL (20) Sail 1 TN eoNak i 4 a AROS UY ea el Pe 07) |i zi SS SOR TL Sr ning MEL ov a LUST , ag ss ICL7126 EF, Fp, Ap Bg OD E, 6G, F, Ay (14) (13) 412) (11) (10) (9) (ay 7) @) 6) (4) 8, (3), == a = ris =, flail (2), aR oriet (40) 081 (39) OSC 2 ery ee i ie (38) OSe3 (37) TEST (27) (28) (29) (30) (31) 32) (83) (34) (38) (36) INT BUFF AZ INLO INHI COMM Cpe; Caer, LO HI REF REF 14 PECEIUED FROM lield. pee