LTC2207-14/LTC2206-14
1
220714614fc
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
APPLICATIO S
U
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 TA01b
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
14-Bit, 105Msps/80Msps
ADCs
The LTC
®
2207-14/LTC2206-14 are 105Msps/80Msps,
sampling 14-bit A/D converters designed for digitizing
high frequency, wide dynamic range signals up to input
frequencies of 700MHz. The input range of the ADC can
be optimized with the PGA front end.
The LTC2207-14/LTC2206-14 are perfect for demanding
communications applications, with AC performance that
includes 77.3dB SNR and 98dB spurious free dynamic
range (SFDR). Ultralow jitter of 80fsRMS allows under-
sampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±1.5LSB INL,
±1LSB DNL (no missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
n Telecommunications
n Receivers
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
n ATE
n Sample Rate: 105Msps/80Msps
n 77.3dBFS Noise Floor
n 98dB SFDR
n SFDR >82dB at 250MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Optional Data Output Randomizer
n Single 3.3V Supply
n Power Dissipation: 947mW/762mW
n Optional Clock Duty Cycle Stabilizer
n Out-of-Range Indicator
n Pin-Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
25Msps: LTC2203 (16-Bit) Single-Ended Clock
10Msps: LTC2202 (16-Bit) Single-Ended Clock
n 48-Pin 7mm × 7mm QFN Package
–
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D13
•
•
•
D0
ENC+PGA SHDN DITH MODE OE RANDENC–
VCM
ANALOG
INPUT
2207614 TA01
0.5V TO 3.6V
3.3V
3.3V
SENSE
OGND
OVDD
2.2μF
0.1μF
0.1μF 0.1μF 0.1μF
VDD
GND
ADC CONTROL INPUTS
AIN+
AIN–
OF
CLKOUT+
CLKOUT–
LTC2207-14: 32K Point FFT,
fIN = 14.86MHz, –1dBFS,
PGA = 0, 105Msps
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2207-14/LTC2206-14
2
220714614fc
Supply Voltage (VDD) ......................................................
–0.3V to 4V
Digital Output Ground Voltage (OGND) ...........................
–0.3V to 1V
Analog Input Voltage (Note 3) ........................................
–0.3V to (VDD + 0.3V)
Digital Input Voltage .......................................................
–0.3V to (VDD + 0.3V)
Digital Output Voltage .....................................................
–0.3V to (OVDD + 0.3V)
Power Dissipation ...........................................................
2000mW
OVDD = VDD (Notes 1, 2)
TOP VIEW
UK PACKAGE
48-LEAD (7mm s 7mm) PLASTIC QFN
SENSE 1
VCM 2
VDD 3
VDD 4
GND 5
AIN+ 6
AIN–7
GND 8
ENC+ 9
ENC– 10
GND 11
VDD 12
36 OVDD
35 D11
34 D10
33 D9
32 D8
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D7
27 D6
26 D5
25 OVDD
48 GND
47 PGA
46 RAND
45 MODE
44 OE
43 OF
42 D15
41 D14
40 D13
39 D12
38 OGND
37 OVDD
VDD 13
VDD 14
GND 15
SHDN 16
DITH 17
D0 18
D1 19
D2 20
D3 21
D4 22
OGND 23
OVDD 24
49
EXPOSED PAD IS GND (PIN 49)MUST BE SOLDERED TO PCB BOARD
TJMAX = 125°C, θJA = 29°C/W
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2207CUK-14#PBF LTC2207CUK-14#TRPBF LTC2207UK-14 48-Lead (7mm × 7mm) Plastic Plastic QFN 0°C to 70°C
LTC2206CUK-14#PBF LTC2206CUK-14#TRPBF LTC2206UK-14 48-Lead (7mm × 7mm) Plastic Plastic QFN 0°C to 70°C
LTC2207IUK-14#PBF LTC2207IUK-14#TRPBF LTC2207UK-14 48-Lead (7mm × 7mm) Plastic Plastic QFN –40°C to 85°C
LTC2206IUK-14#PBF LTC2206IUK-14#TRPBF LTC2206UK-14 48-Lead (7mm × 7mm) Plastic Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Integral Linearity Error Differential Analog Input (Note 5) l±0.4 ±1.5 LSB
Differential Linearity Error Differential Analog Input l±0.1 ±1LSB
Offset Error (Note 6) l±1±10.3 mV
Offset Drift ±10 μV/°C
Gain Error External Reference l±0.2 ±2.3 %FS
Full-Scale Drift Internal Reference
External Reference
±30
±15
ppm/°C
ppm/°C
Transition Noise 0.8 LSBRMS
LTC2207-14/LTC2206-14
3
220714614fc
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)
ANALOG INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 3.135V ≤ VDD ≤ 3.465V l1.5 to 2.25 VP-P
VIN, CM Analog Input Common Mode Differential Input (Note 7) l1 1.25 1.5 V
IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD (Note 8) l–1 1 μA
ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD (Note 9) l–4 3 μA
IMODE MODE Pin Pull-Down Current to GND 10 μA
CIN Analog Input Capacitance Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–6.7
1.8
pF
pF
tAP Sample-and-Hold
Acquisition Delay Time
1ns
tJITTER Sample-and-Hold
Acquisition Delay Time Jitter
80 fsRMS
CMRR Analog Input
Common Mode Rejection Ratio
1V < (AIN+ = AIN–) <1.5V 80 dB
BW-3dB Full Power Bandwidth RS ≤ 25Ω700 MHz
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN
LTC2206-14
TYP MAX MIN
LTC2207-14
TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
77.3
75.1
77.3
75.1
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0), TA = 25ºC
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l
76
75.8
77.2
77.2
75
76
75.8
77.2
77.2
75
dBFS
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
76.9
75
76.9
75
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1) l
73.1
72.9
76.2
74.5
74.6
73.1
72.9
76.2
74.5
74.6
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
75.8
75.1
75.8
75.1
dBFS
dBFS
SFDR Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
98
98
98
98
dBc
dBc
15MHz Input (2.25V Range, PGA = 0), TA = 25ºC
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l
85
84
93
93
98
85
84
93
93
98
dBc
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
90
94
90
94
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1) l
82
81
85
90
90
82
81
85
90
90
dBc
dBc
dBc
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
81
85
81
85
dBc
dBc
DYNAMIC ACCURACY
LTC2207-14/LTC2206-14
4
220714614fc
SYMBOL PARAMETER CONDITIONS MIN
LTC2206-14
TYP MAX MIN
LTC2207-14
TYP MAX UNITS
SFDR Spurious Free
Dynamic Range
4th Harmonic
or Higher
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBc
dBc
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l90 100
100
90 100
100
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) l86.5
95
97 86.5
95
97
dBc
dBc
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
89
93
89
93
dBc
dBc
S/(N+D) Signal-to-Noise
Plus Distortion Ratio
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
77
74.9
77
74.9
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0), TA = 25ºC
15MHz Input (2.25V Range, PGA = 0
15MHz Input (1.5V Range, PGA = 1)
l
75.9
75.7
77.1
77.1
75.3
75.9
75.7
77.1
77.1
75.3
dBFS
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
76.7
75
76.7
75
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1) l
72.7
72.5
74.8
74.5
74.5
72.7
72.5
74.8
74.5
74.5
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
74.1
73.7
74.4
73.7
dBFS
dBFS
SFDR Spurious Free
Dynamic Range
at –25dBFS
Dither “OFF”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
97
97
97
97
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
96
96
96
96
dBFS
dBFS
SFDR Spurious Free
Dynamic Range
at –25dBFS
Dither “ON”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
108
108
108
108
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l95 107
107
95 107
107
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
107
107
107
107
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
102
102
102
102
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
DYNAMIC ACCURACY
LTC2207-14/LTC2206-14
5
220714614fc
The l denotes the specifi cations which apply over
the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
COMMON MODE BIAS CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 l1.15 1.25 1.35 V
VCM Output Tempco IOUT = 0 40 ppm/°C
VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 1 mV/ V
VCM Output Resistance –1mA ≤ | IOUT | ≤ 1mA 2 Ω
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
VID Differential Input Voltage (Note 7) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 7) 1.4
1.6
3
V
RIN Input Resistance (See Figure 2) 6 kΩ
CIN Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH High Level Input Voltage VDD = 3.3V l2V
VIL Low Level Input Voltage VDD = 3.3V l0.8 V
IIN Input Current VIN = 0V to VDD l ±10 μA
CIN Input Capacitance (Note 7) 1.5 pF
LOGIC OUTPUTS
OVDD = 3.3V
VOH High Level Output Voltage VDD = 3.3V IO = –10μA
IO = –200μA l3.1
3.299
3.29
V
V
VOL Low Level Output Voltage VDD = 3.3V IO = 160μA
IO = 1.60μA l
0.01
0.1 0.4
V
V
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = 3.3V 50 mA
OVDD = 2.5V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V
OVDD = 1.8V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V
LTC2207-14/LTC2206-14
6
220714614fc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz (LTC2207-14), 80MHz (LTC2206-
14) differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode,
input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise
specifi ed.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from a
“best fi t straight line” to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code fl ickers between 00 0000 0000 0000 and 11 1111 1111 1111
in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: The dynamic current of the switched capacitors analog inputs can
be large compared to the leakage current and will vary with the sample
rate.
Note 9: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1kΩ.
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN
LTC2206-14
TYP MAX MIN
LTC2207-14
TYP MAX UNITS
fSSampling Frequency l1 80 1 105 MHz
tLENC Low Time Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
5.94
4.06
6.25
6.25
500
500
4.52
3.10
4.762
4.762
500
500
ns
ns
tHENC High Time Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
5.94
4.06
6.25
6.25
500
500
4.52
3.10
4.762
4.762
500
500
ns
ns
tAP Sample-and-Hold
Aperture Delay
–0.7 –0.7 ns
tDENC to DATA Delay (Note 7) l1.3 2.7 4 1.3 2.7 4 ns
tCENC to CLKOUT Delay (Note 7) l1.3 2.7 4 1.3 2.7 4 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l–0.6 0 0.6 –0.6 0 0.6 ns
tOE DATA Access time
Bus Relinquish time
CL = 5pF (Note 7)
(Note 7)
l
l
5
5
15
15
5
5
15
15
ns
ns
Pipeline
Latency
77Cycles
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN
LTC2206-14
TYP MAX MIN
LTC2207-14
TYP MAX UNITS
VDD Analog Supply Voltage l3.135 3.3 3.465 3.135 3.3 3.465 V
PSHDN Shutdown Power SHDN = VDD 0.2 0.2 mW
OVDD Output Supply Voltage l0.5 3.6 0.5 3.6 V
IVDD Analog Supply Current DC Input l231 275 287 350 mA
PDIS Power Dissipation DC Input l762 908 947 1155 mW
POWER REQUIREMENTS
LTC2207-14/LTC2206-14
7
220714614fc
TIMING DIAGRAM
tH
tD
tC
tL
N – 7 N – 6 N – 5 N – 4 N – 3
ANALOG
INPUT
ENC–
ENC+
CLKOUT–
CLKOUT+
D0-D13, OF
2207614 TD01
tAP N + 1
N + 2
N + 4
N + 3
N
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G06
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G05
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G04
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
OUTPUT CODE
0
DNL ERROR (LSB)
0
16384
2207614 G02
4096 8192 12288
2048 6144 10240 14336
–0.5
–0.4
–0.2
–0.1
0.5
0.2
–0.3
0.3
0.4
0.1
OUTPUT CODE
0
INL ERROR (LSB)
0
16384
2207614 G01
4096 8192 12288
2048 6144 10240 14336
–1.0
–0.8
–0.4
–0.2
1.0
0.4
–0.6
0.6
0.8
0.2
OUTPUT CODE
8201
COUNT
150000
200000
250000
8209
2207614 G03
100000
50000
08203 8205 8207 8211
LTC2207-14: Differential
Nonlinearity (DNL) vs
Output Code
LTC2207-14: AC Grounded Input
Histogram
LTC2207-14: 32K Point FFT,
fIN = 5.23MHz, –1dBFS, PGA = 0,
RAND “On”, Dither “Off”
LTC2207-14: 32K Point FFT,
fIN = 14.86MHz, –1dBFS, PGA = 0,
RAND “On”, Dither “Off”
LTC2207-14: 64K Point FFT,
fIN = 15.1MHz, –25dBFS, PGA = 0,
RAND “On”, Dither “Off”
LTC2207-14: Integral Nonlinearity
(INL) vs Output Code
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2207-14/LTC2206-14
8
220714614fc
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G07
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
2207614 G08
100
120
–70 –50 –30 –10
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
2207614 G09
100
120
–70 –50 –30 –10
LTC2207-14: SFDR vs Input Level,
fIN = 15.1MHz, PGA = 0,
RAND “On”, Dither “Off”
LTC2207-14: SFDR vs Input Level,
fIN = 15.1MHz, PGA = 0,
RAND “On”, Dither “On”
LTC2207-14: 64K Point FFT,
fIN = 15.1MHz, –25dBFS, PGA = 0,
RAND “On”, Dither “On”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G13
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G14
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G15
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
LTC2207-14: 32K Point 2-Tone FFT,
fIN = 14.87MHz and 18.56MHz, –7dBFS,
PGA = 0, RAND “On”, Dither “Off’
LTC2207-14: 32K Point 2-Tone FFT,
fIN = 14.87MHz and 18.56MHz, –15dBFS,
PGA = 0, RAND “On”, Dither “Off’
LTC2207-14: 32K Point FFT,
fIN = 70.24MHz, –1dBFS,
PGA = 0, RAND “On”, Dither “Off’
LTC2207-14: 32K Point 2-Tone FFT,
fIN = 69.2MHz and 76.5MHz, –7dBFS,
PGA = 0, RAND “On”, Dither “Off’
LTC2207-14: 32K Point 2-Tone FFT, fIN
= 69.2MHz and 76.5MHz, –15dBFS,
PGA = 0, RAND “On”, Dither “Off’
LTC2207-14: 32K Point FFT,
fIN = 70.24MHz, –1dBFS,
PGA = 1, RAND “On”, Dither “Off’
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G10
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G11
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G12
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2207-14/LTC2206-14
9
220714614fc
LTC2207-14: 64K Point FFT,
fIN = 70.1MHz, –25dBFS,
PGA = 0, RAND “On”, Dither “Off’
LTC2207-14: 64K Point FFT,
fIN = 70.1MHz, –25dBFS,
PGA = 0, RAND “On”, Dither “On’
LTC2207-14: 32K Point FFT,
fIN = 174.8MHz, –1dBFS,
PGA = 1, RAND “On”, Dither “Off’
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G16
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G17
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G18
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT FREQUENCY (MHz)
0
60
SFDR (dBc)
65
75
80
85
200 400 500
105
2207614 G22
70
100 300
90
95
100
PGA = 1
PGA = 0
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
73
74
75
300 500
2207614 G23
72
71
70 100 200 400
76
77
78
PGA = 0
PGA = 1
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
90
100
200
2207614 G24
80
70 50 100 150
25 75 125 175
110
85
95
75
105 SFDR
SNR
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
40
2207614 G19
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 50
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
2207614 G20
100
120
–70 –50 –30 –10
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
2207614 G21
100
120
–70 –50 –30 –10
LTC2207-14: 32K Point FFT,
fIN = 250.11MHz, –1dBFS,
PGA = 1, RAND “On”, Dither “Off’
LTC2207-14: SFDR vs Input Level,
fIN = 140.1MHz, PGA = 1, RAND
“On”, Dither “Off”
LTC2207-14: SFDR vs Input Level,
fIN = 140.1MHz, PGA = 1, RAND
“On”, Dither “On”
LTC2207-14: SFDR (HD2 and
HD3) vs Input Frequency
LTC2207-14: SNR vs Input
Frequency
LTC2207-14: SNR and SFDR
vs Sample Rate, fIN = 5.1MHz,
–1dBFS
LTC2207-14/LTC2206-14
10
220714614fc
SUPPLY VOLTAGE (V)
2.8
SNR AND SFDR (dBFS)
90
95
100
3.6
2207614 G25
85
80
70 3.0 3.2 3.4
75
110
105
SFDR
SNR
DUTY CYCLE (%)
30
SNR (dBFS) AND SFDR (dBc)
80
90
70
2207614 G27
70
60 40 50 60
110
100
SFDR DCS OFF
SFDR DCS ON
SNR DCS ON
SNR DCS OFF
SAMPLE RATE (Msps)
10
280
300
340
70 110
2207614 G26
260
240
30 50 90 130 150
220
200
320
IVDD (mA)
VDD = 3.47V
VDD = 3.13V
VDD = 3.3V
LTC2207-14: SNR and SFDR vs
Supply Voltage (VDD),
fIN = 5.1MHz, –1dBFS
LTC2207-14: IVDD vs Sample
Rate, fIN = 5.1MHz, –1dBFS
LTC2207-14: SNR and SFDR vs
Duty Cycle, 105Msps
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT COMMON MODE (V)
0.5
SNR (dBFS) AND SFDR (dBc)
80
90
2.5
2207614 G28
70
60 1.0 1.5 2.0
110
100
SFDR
SFR
OUTPUT CODE
0
–1.0
INL ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192 10240
2207614 G29
–0.6
0.6
0.8
0.2
2048 6144 1228814336 16384
OUTPUT CODE
0
–0.5
DNL ERROR (LSB)
–0.4
–0.2
–0.1
0
0.5
0.2
4096 8192 10240
2207614 G30
–0.3
0.3
0.4
0.1
2048 6144 1228814336 16384
OUTPUT CODE
8181
COUNT
150000
200000
250000
8189
2207614 G31
100000
50000
08183 8185 8187 8191
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G32
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G33
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
LTC2207-14: SNR and SFDR vs
Analog Input Common Mode
Voltage, fIN = 5.1MHz, –1dBFS
LTC2206-14: Integral Nonlinearity
(INL) vs Output Code
LTC2206-14: Differential
Nonlinearity (DNL) vs
Output Code
LTC2206-14: AC Grounded Input
Histogram
LTC2206-14: 32K Point FFT,
fIN = 5.23MHz, –1dBFS, PGA = 0,
RAND = “On”, Dither “Off”
LTC2206-14: 32K Point FFT, fIN
= 14.86MHz, –1dBFS, PGA = 0,
RAND = “On”, Dither “Off”
LTC2207-14/LTC2206-14
11
220714614fc
INPUT LEVEL (dBFS)
–80 –70
SFDR (dBc AND dBFS)
80
100
120
–40 –20
2207614 G36
60
40
–60 –50 –30 –10 0
20
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G35
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G34
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
LTC2206-14: 64K Point FFT, fIN
= 15.1MHz, –25dBFS, PGA = 0,
RAND = “On”, Dither “Off”
LTC2206-14: 64K Point FFT, fIN
= 15.1MHz, –25dBFS, PGA = 0,
RAND = “On”, Dither “On”
LTC2206-14: SFDR vs Input Level,
fIN = 15.1MHz, PGA = 0,
RAND = “On”, Dither “Off”
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G43
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G41
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
INPUT LEVEL (dBFS)
–80 –70
SFDR (dBc AND dBFS)
80
100
120
–40 –20
2207614 G37
60
40
–60 –50 –30 –10 0
20
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G38
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G39
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G40
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
LTC2206-14: SFDR vs Input Level,
fIN = 15.1MHz, PGA = 0,
RAND = “On”, Dither “On”
LTC2206-14: 32K Point 2-Tone FFT, fIN
= 14.87MHz and 18.56MHz, –7dBFS,
PGA = 0, RAND = “On”, Dither “Off”
LTC2206-14: 32K Point 2-Tone FFT, fIN
= 14.87MHz and 18.56MHz, –15dBFS,
PGA = 0, RAND = “On”, Dither “Off”
LTC2206-14: 32K Point FFT, fIN
= 70.24MHz, –1dBFS, PGA = 0,
RAND = “On”, Dither “Off”
LTC2206-14: 32K Point 2-Tone FFT,
fIN = 69.2MHz and 76.5MHz, –7dBFS,
PGA = 0, RAND = “On”, Dither “Off”
LTC2206-14: 32K Point FFT, fIN
= 70.24MHz, –1dBFS, PGA = 1,
RAND = “On”, Dither “Off”
LTC2207-14/LTC2206-14
12
220714614fc
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G45
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G44
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G42
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
LTC2206-14: 32K Point 2-Tone FFT, fIN
= 69.2MHz and 76.5MHz, –15dBFS,
PGA = 0, RAND = “On”, Dither “Off”
LTC2206-14: 64K Point FFT, fIN
= 70.1MHz, –25dBFS, PGA = 0,
RAND = “On”, Dither “Off”
LTC2206-14: 64K Point FFT, fIN
= 70.1MHz, –25dBFS, PGA = 0,
RAND = “On”, Dither “On”
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT FREQUENCY (MHz)
0
60
SFDR (dBc)
65
75
80
85
400
105
2207614 G50
70
200
100 300 500
90
95
100
PGA = 1
PGA = 0
INPUT LEVEL (dBFS)
–80 –70
SFDR (dBc AND dBFS)
80
100
120
–40 –20
2207614 G48
60
40
–60 –50 –30 –10 0
20
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G47
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–70
–30
0
2207614 G46
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120 10 20 30 40
LTC2206-14: 32K Point FFT, fIN =
170.21MHz, –1dBFS, PGA = 1,
RAND = “On”, Dither “Off”
LTC2206-14: 32K Point FFT, fIN =
250.11MHz, –1dBFS, PGA = 1,
RAND = “On”, Dither “Off”
LTC2206-14: SFDR vs Input Level,
fIN = 140.1MHz, PGA = 1,
RAND = “On”, Dither “Off”
LTC2206-14: SFDR vs Input Level,
fIN = 140.1MHz, PGA = 1,
RAND = “On”, Dither “On”
LTC2206-14: SFDR (HD2 and
HD3) vs Input Frequency
LTC2206-14: SNR vs Input
Frequency, RAND = “On”,
DITH = “On”
INPUT LEVEL (dBFS)
–80 –70
SFDR (dBc AND dBFS)
80
100
120
–40 –20
2207614 G49
60
40
–60 –50 –30 –10 0
20
0
INPUT FREQUENCY (MHz)
0
70
SNR (dBFS)
71
73
74
75
200 400 500
79
2207614 G51
72
100 300
76
77
78
PGA = 0
PGA = 1
LTC2207-14/LTC2206-14
13
220714614fc
SAMPLE RATE (Msps)
10
280
300
340
70 110
2207614 G54
260
240
30 50 90 130 150
220
200
320
IVDD (mA)
VDD = 3.47V
VDD = 3.13V
VDD = 3.3V
SUPPLY VOLTAGE (V)
2.8
SNR AND SFDR (dBFS)
85
90
95
3.0 3.4
2207614 G53
80
75
70 3.2
100
105
110
3.6
SFDR
SNR
SAMPLE RATE (Msps)
10
SNR AND SFDR (dBFS)
85
90
95
85 135
2207614 G52
80
75
70 35 60 110
100
105
110
160
SFDR
SNR
LTC2206-14: SNR and SFDR
vs Sample Rate, fIN = 5.1MHz,
–1dBFS
LTC2206-14: SNR and SFDR vs
Supply Voltage (VDD),
fIN = 5.1MHz, –1dBFS
LTC2206-14: IVDD vs Sample
Rate, fIN = 5.1MHz, –1dBFS
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–50
INPUT OFFSET VOLTAGE DRIFT (mV)
0.5
1.0
9070
2207614 G59
–0.5
–2.0 –30 –10 10 30 50
1.5
0
–1.0
–1.5
TEMPERATURE (°C)
–50
GAIN ERROR DRIFT (%)
–0.1
0.1
0.3
0.2
0
30
2207614 G58
–0.3
–0.2
–0.5
–0.4
–0.7
–0.6
–30 –10 10 50 9070
ANALOG INPUT COMMON MODE (V)
0.5
SNR (dBFS) AND SFDR (dBc)
85
90
95
1.0 2.0
2207614 G56
80
75
70 1.5
100
105
110
2.5
SNR
SFDR
DUTY CYCLE (%)
30
SNR (dBFS) AND SFDR (dBc)
80
90
70
2207614 G55
70
60 40 50 60
110
100
SFDR DCS OFF
SFDR DCS ON
SNR DCS ON
SNR DCS OFF
TEMPERATURE (°C)
–50
GAIN ERROR DRIFT (%)
0.02
0.06
0.10
30
2207614 G57
–0.02
–0.06
–0.10 –30 –10 10 50 9070
LTC2206-14: SNR and SFDR vs
Duty Cycle, 80Msps
LTC2206-14: SNR and SFDR vs
Analog Input Common Mode
Voltage, fIN = 5.1MHz, –1dBFS
Gain Error Drift vs Temperature,
External Reference, 5 Units,
Drift from 25°C
Gain Error Drift vs Temperature,
Internal Reference, 5 Units
Drift from 25°C
Input Offset Voltage Drift vs
Temperature, 5 Units,
Drift from 25°C
LTC2207-14/LTC2206-14
14
220714614fc
TYPICAL PERFORMANCE CHARACTERISTICS
TIME AFTER WAKE-UP OR CLOCK START (μs)
0
FULL-SCALE ERROR (%)
0.2
0.6
1.0
400
2207614 G60
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 10050 200150 300 350 450
250 500
TIME FROM WAKE-UP OR CLOCK START (μs)
0
FULL-SCALE ERROR (%)
1
3
5
800
2207614 G61
–1
–3
0
2
4
–2
–4
–5 200100 400300 600 700 900
500 1000
Mid-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
Full-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM (Pin 2): 1.25V Output. Optimum voltage for input com-
mon mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
GND (Pins 5, 8, 11, 15, 48): ADC Power Ground.
AIN+ (Pin 6): Positive Differential Analog Input.
AIN– (Pin 7): Negative Differential Analog Input.
ENC+ (Pin 9): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2k resistor. Output
data can be latched on the rising edge of ENC+.
ENC– (Pin 10): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC–.
Internally biased to 1.6V through a 6.2k resistor. Bypass to
ground with a 0.1μF capacitor for a single-ended Encode
signal.
SHDN (Pin 16): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 17): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
NC (Pins 18, 19): No Connect.
D0-D13 (Pins 20-22, 26-28, 32-35 and 39-42): Digital
Outputs. D13 is the MSB.
OGND (Pins 23, 31 and 38): Output Driver Ground.
OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
CLKOUT– (Pin 29): Data Valid Output. CLKOUT– will toggle
at the sample rate. Latch the data on the falling edge of
CLKOUT–.
CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT+.
PIN FUNCTIONS
LTC2207-14/LTC2206-14
15
220714614fc
PIN FUNCTIONS
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under fl ow has occurred.
OE (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 46): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA (Pin 47): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25VP-P
. High
selects a front-end gain of 1.5, input range of 1.5VP-P
.
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
DITH OEMODEPGA RANDSHDN
ADC CLOCKS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+ENC–
CORRECTION LOGIC
AND
SHIFT REGISTER
OGND
CLKOUT+
CLKOUT–
OF
D13
D12
OVDD
D1
D0
2207614 F01
INPUT
S/H
AIN–
AIN+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC •
•
•
VDD
GND
PGA
SENSE
VCM BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
Figure 1. Functional Block Diagram
BLOCK DIAGRAM
LTC2207-14/LTC2206-14
16
220714614fc
OPERATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim-
ited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
fi rst fi ve harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is
defi ned as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample-
and-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
LTC2207-14/LTC2206-14
17
220714614fc
CONVERTER OPERATION
The LTC2207-14/LTC2206-14 are CMOS pipelined
multistep converters with a front-end PGA. As
shown in Figure 1, the converter has fi ve pipelined
ADC stages; a sampled analog input will result in
a digitized value seven clock cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2207-14/LTC2206-14 have two phases of
operation, determined by the state of the differential
ENC+/ENC– input pins. For brevity, the text will refer to
ENC+ greater than ENC– as ENC high and ENC+ less than
ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifi er. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages oper-
ate out-of-phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the Block Diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifi er which
drives the fi rst pipelined ADC stage. The fi rst stage acquires
the output of the S/H amplifi er during the high phase of
ENC. When ENC goes back low, the fi rst stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden-
tical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fi fth
stage for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
18
220714614fc
Figure 2. Equivalent Input Circuit
CSAMPLE
4.9pF
VDD
VDD
LTC2207-14/LTC2206-14
AIN+
2207614 F02
CSAMPLE
4.9pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2207-14/
LTC2206-14 CMOS differential sample and hold. The dif-
ferential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transistors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specifi ed performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ± 0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 2) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF capacitor or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2207-14/LTC2206-14 can
be infl uenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
input reactance can infl uence SFDR. At the falling edge
of ENC the sample-and-hold circuit will connect the 4.9pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, hold-
ing the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
19
220714614fc
INPUT DRIVE CIRCUITS
Input Filtering
A fi rst order RC lowpass fi lter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2207-
14/LTC2206-14 have a very broadband S/H circuit, DC to
700MHz; it can be used in a wide range of applications;
therefore, it is not possible to provide a single recom-
mended RC fi lter.
Figures 3, 4a and 4b show three examples of input RC
fi ltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated–this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2207-
14/LTC2206-14 do not require any input fi lter to achieve
data sheet specifi cations; however, no fi ltering will put
more stringent noise requirements on the input drive
circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2207-14/LTC2206-14 being driven
by an RF transformer with a center-tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used; however, as the turns ratio increases so does the
impedance seen by the ADC. Source impedance greater
0.1μF
AIN+
AIN–
4.7pF
2.2mF
4.7pF
4.7pF
VCM
LTC2207-14/
LTC2206-14
ANALOG
INPUT
0.1μF
0.1μF
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2207614 F04a
5Ω
50Ω
10Ω
25Ω
25Ω 10Ω 5Ω
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
0.1μF
AIN+
AIN–
2.2μF
2.2pF
2.2pF
VCM
LTC2207-14/
LTC2206-14
ANALOG
INPUT
0.1μF
0.1μF
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2207614 F04b
5Ω
50Ω
25Ω
25Ω 5Ω
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
than 50Ω can reduce the input bandwidth and increase
high frequency distortion. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4a shows transformer coupling using a transmis-
sion line balun transformer. This type of transformer has
much better high frequency response and balance than
fl ux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 150MHz
35Ω
50Ω
35Ω
10Ω
10Ω
5Ω
5Ω
0.1μF
AIN+
AIN–
8.2pF
2.2μF
8.2pF
8.2pF
VCM
LTC2207-14/
LTC2206-14
T1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2207614 F03
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
20
220714614fc
Figure 5. DC Coupled Input with Differential Amplifi er
––
++
AIN+
AIN–
2.2μF
12pF
12pF
VCM
LTC2207-14/
LTC2206-14
ANALOG
INPUT
2207614 F05
CM
AMPLIFIER = LTC6600-20,
LT1993, ETC.
HIGH SPEED
DIFFERENTIAL
AMPLIFIER 25Ω
25Ω
PGA
1.25V
SENSE
VCM BUFFER
INTERNAL
ADC
REFERENCE
RANGE
SELECT
AND GAIN
CONTROL
2.5V
BANDGAP
REFERENCE
2.2μF
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
2207614 F06
LTC2207-14/
LTC2206-14
Figure 6. Reference Circuit
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifi er to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifi er will de-
grade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifi ers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
Reference Operation
Figure 6 shows the LTC2207-14/LTC2206-14 refer-
ence circuitry consisting of a 2.5V bandgap reference,
a programmable gain amplifi er and control circuit. The
LTC2207-14/LTC2206-14 have three modes of reference
operation: Internal Reference, 1.25V external reference
or 2.5V external reference. To use the internal reference,
tie the SENSE pin to VDD. To use an external reference,
simply apply either a 1.25V or 2.5V reference voltage to the
SENSE input pin. Both 1.25V and 2.5V applied to SENSE
will result in a full scale range of 2.25VP-P (PGA = 0). A
1.25V output VCM is provided for a common mode bias
for input drive circuitry. An external bypass capacitor is
required for the VCM output. This provides a high frequency
low impedance path to ground for internal and external
circuitry. This is also the compensation capacitor for the
reference; it will not be stable without this capacitor. The
minimum value required for stability is 2.2μF.
The internal programmable gain amplifi er provides the
internal reference voltage for the ADC. This amplifi er has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1μF (or larger) ceramic capacitor.
PGA Pin
The PGA pin selects between two gain settings for
the ADC front-end. PGA = 0 selects an input range of
2.25VP-P; PGA = 1 selects an input range of 1.5VP-P
. The
2.25V input range has the best SNR; however, the distor-
tion will be higher for input frequencies above 100MHz.
For applications with high input frequencies, the low input
range will have improved distortion; however, the SNR
will be worse by up to approximately 2dB. See the Typical
Performance Characteristics section.
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
21
220714614fc
2207614 F10
ENC–
ENC+
3.3V
3.3V
D0
Q0
Q0
MC100LVELT22
LTC2207-14/
LTC2206-14
Figure 10. ENC Drive Using a CMOS to PECL Translator
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
2207614 F09
ENC–
1.6V
VTHRESHOLD = 1.6V ENC+
0.1μF
LTC2207-14/
LTC2206-14
Figure 7. A 2.25V Range ADC with
an External 2.5V Reference
VCM
SENSE
1.25V
3.3V
2.2μF
2.2μF
1μF
2207614 F07
LTC2207-14/
LTC2206-14
26
4
LT1461-2.5
Figure 8a. Equivalent Encode Input Circuit
Figure 8b. Transformer Driven Encode
VDD
VDD
LTC2207-14/
LTC2206-14
2207614 F08a
VDD
ENC–
ENC+
1.6V
1.6V
6k
6k
TO INTERNAL
ADC CLOCK
DRIVERS
50Ω
100Ω
8.2pF
0.1μF
0.1μF
0.1μF
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2207-14/
LTC2206-14
2207614 F08b
ENC–
ENC+
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
22
220714614fc
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2207-14 is 105Msps.
The maximum encode rate for the LTC2206-14 is 80Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must be at
least 4.52ns for the LTC2207-14 internal circuitry to have
enough settling time for proper operation. For the LTC2206-
14, each half cycle must be at least 5.94ns. Achieving a
precise 50% duty cycle is easy with differential sinusoidal
drive using a transformer or using symmetric differential
logic such as PECL or LVDS. When using a single-ended
ENCODE signal asymmetric rise and fall times can result
in duty cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2207-14/LTC2206-14 sample rate
is determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specifi ed minimum operating
frequency for the LTC2207-14/LTC2206-14 is 1Msps.
Driving the Encode Inputs
The noise performance of the LTC2207-14/LTC2206-14 can
depend on the encode signal quality as much as on the
analog input. The encode inputs are intended to be driven
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 6k
resistor to a 1.6V bias. The bias resistors set the DC oper-
ating point for transformer coupled drive circuits and can
set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fi xed frequency sinusoidal
signal, fi lter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.4V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
23
220714614fc
LTC2207-14/LTC2206-14
2207614 F11
OVDD
VDD VDD
0.1μF
TYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
33Ω
Figure 11. Equivalent Circuit for a Digital Output Buffer
DIGITAL OUTPUTS
Digital Output Buffers
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2207-14/LTC2206-14 should drive
a minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required since
the output buffer has a series resistor of 33Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
The LTC2207-14/LTC2206-14 parallel digital output can
be selected for offset binary or 2’s complement format.
The format is selected with the MODE pin. This pin has a
four level logic input, centered at 0, 1/3VDD, 2/3VDD and
VDD. An external resistor divider can be used to set the
1/3VDD and 2/3VDD logic levels. Table 1 shows the logic
states for the MODE pin.
Table 1. MODE Pin Function
MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER
0(GND) Offset Binary Off
1/3VDD Offset Binary On
2/3VDD 2’s Complement On
VDD 2’s Complement Off
Overfl ow Bit
An overfl ow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overfl ow or underfl ow.
Output Clock
The ADC has a delayed version of the encode input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the
Figure 12. Functional Equivalent of Digital Output Randomizer
•
•
•
CLKOUT+
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0D0
D1
RAND = HIGH,
SCRAMBLE
ENABLED
D2
D12
D13
OF
LTC2207-14/LTC2206-14
CLKOUT
RAND
2207614 F12
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
24
220714614fc
APPLICATIONS INFORMATION
converter data to the digital system. This is necessary
when using a sinusoidal encode. Data can be latched on the
rising edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise fl oor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
when the RAND pin is high.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply. In CMOS mode OVDD can be powered with
any logic voltage up to the VDD of the ADC. OGND can be
powered with any voltage from ground up to 1V and must
be less than OVDD. The logic outputs will swing between
OGND and OVDD.
Internal Dither
The LTC2207-14/LTC2206-14 are 14-bit ADCs with a very
linear transfer function; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the input
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
Figure 13. Descrambling a Scrambled Digital Output
•
•
•
D1
D0
D2
D12
D13
LTC2207-14/
LTC2206-14
PC BOARD
FPGA
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
2207614 F13
LTC2207-14/LTC2206-14
25
220714614fc
Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit
+–
AIN–
AIN+
S/H
AMP
DIGITAL
SUMMATION OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
14-BIT
PIPELINED
ADC CORE
PRECISION
DAC
CLOCK/DUTY
CYCLE
CONTROL
CLKOUT
OF
D13
•
•
•
D0
ENC
DITHER ENABLE
HIGH = DITHER ON, LOW = DITHER OFF
DITH
ENC
ANALOG
INPUT
2207614 F14
LTC2207-14/LTC2206-14
As shown in Figure 14, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise fl oor of the ADC, as compared to the noise fl oor
with dither off.
Grounding and Bypassing
The LTC2207-14/LTC2206-14 require a printed circuit board
with a clean unbroken ground plane; a multilayer board
with an internal ground plane is recommended. The pinout
of the LTC2207-14/LTC2206-14 has been optimized for a
fl owthrough layout so that the interaction between inputs
and digital outputs is minimized. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2207-14/LTC2206-14 differential inputs should run
parallel and close to each other. The input traces should
be as short as possible to minimize capacitance and to
minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2207-14/LTC2206-
14 is transferred from the die through the bottom-side
exposed pad. For good electrical and thermal performance,
the exposed pad must be soldered to a large grounded
pad on the PC board. It is critical that the exposed pad
and all ground pins are connected to a ground plane of
suffi cient area with as many vias as possible.
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
26
220714614fc
Top Side
Silkscreen Top
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
27
220714614fc
APPLICATIONS INFORMATION
Inner Layer 3Inner Layer 2
Inner Layer 5Inner Layer 4
LTC2207-14/LTC2206-14
28
220714614fc
Bottom Side
Silkscreen Bottom
APPLICATIONS INFORMATION
LTC2207-14/LTC2206-14
29
220714614fc
Ordering Guide:
DEMO BOARD NUMBER PART NUMBER RESOLUTION SPEED INPUT FREQUENCY USB I/F BOARD
DC918C-A LTC2207CUK 16-Bit 105Msps 1MHz to 70MHz DC718
DC918C-B LTC2207CUK 16-Bit 105Msps 70MHz to 140MHz DC718
DC918C-C LTC2206CUK 16-Bit 80Msps 1MHz to 70MHz DC718
DC918C-D LTC2206CUK 16-Bit 80Msps 70MHz to 140MHz DC718
DC918C-E LTC2205CUK 16-Bit 65Msps 1MHz to 70MHz DC718
DC918C-F LTC2205CUK 16-Bit 65Msps 70MHz to 140MHz DC718
DC918C-G LTC2204CUK 16-Bit 40Msps 1MHz to 70MHz DC718
DC918C-H LTC2207CUK-14 14-Bit 105Msps 1MHz to 70MHz DC718
DC918C-I LTC2207CUK-14 14-Bit 105Msps 70MHz to 140MHz DC718
DC918C-J LTC2206CUK-14 14-Bit 80Msps 1MHz to 70MHz DC718
DC918C-K LTC2206CUK-14 14-Bit 80Msps 70MHz to 140MHz DC718
DC918C-L LTC2205CUK-14 14-Bit 65Msps 1MHz to 70MHz DC718
See Web site for ordering details or contact local sales.
APPLICATIONS INFORMATION
3.3V
NOT PROVIDED
BY DC718
CLOCK OUT
DITHER
SHUTDOWN
LSB ENABLE
MSB
CLOCK POLARITY0V
PGA
SENSE
ANALOG INPUT
(50Ω)
ENC CLOCK INPUT
(50Ω)
22076 DC918C
JUMPERS ARE SHOWN
IN DEFAULT POSITIONS
RANDOMIZER
(REQUIRES CHANGE IN
SELECTED DEVICE IN PSCOPE)
DIGITAL OUTPUTS TO
DC718 (2.5V CMOS)
LTC2207-14/LTC2206-14
30
220714614fc
APPLICATIONS INFORMATION
J3
JP5
SHDN
C15
0.1μF
C12
0.01μF
* VERSION TABLE
C8
2.2μF
C3
0.01μF
C9
0.01μF
C10
0.01μF
C6
0.01μF
C4
0.01μF
ANALOG
INPUT
C7
*
C28
*
R31
*
J2
* R30
* L1
R32
*
T2 3
1
2
4
5
MABA-007159-
000000
*T3 3
1
2
4
5
T1
MABA-
007159-
000000
3
1
2
4
5
ENCODE
INPUT
C30
0.01μF
C16
0.1μF
C17
0.1μF
R20
10k
R29
5.1Ω
R26
5.1Ω
R27
49.9Ω
R14
10Ω
R13
10Ω
R9
10Ω
R10
10Ω
R12
33.2Ω
R11
33.2Ω
C5
*
R8
100Ω
C11
8.2pF
R33
100Ω
R28
49.9Ω
R21, 10k
GND
VDD
GND
VDD
3
2
1
JP6
DITH
3
2
1
JP2
SHDN
3
2
1
OPEN
VDD
C2
2.2μF
C1
0.1μF
3
2
1
15
JP3
PGA
R1
10k
R2
10k
R3
1k
R4
OPEN
R6
OPEN
R7
1k
3
2
1
VDD
GND
JP4
RAND
3
3
4
2
1
VDD
GND
JP1 U4
NC7SV-
86P5X
OVP
GND
2
OVP
2
4
6
8
20
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
12
13
14
15
16
17
18
19
OVP
74VCX245BQX
3201S-40G1
RN1A 33
RN1B 33
RN1C 33
RN1D 33
RN2A 33
RN2B 33
RN2C 33
RN2D 33
RN3A 33
RN3B 33
RN3C 33
RN3D 33
RN4A 33
RN4B 33
RN4C 33
RN4D 33
20U2
33
OGND
R5
J1
9
8
7
6
5
4
3
2
1
10
13
14
15
16
17
18
19
20
21
22
23
24
11
12
13
14
15
16
17
18
19
OVP
74VCX245BQX
4
3
2
1
51
2
3
4
5
6
7
8
U5
NC7S-
V86P5X
U6
24LC025
C14
0.1μF
C19
0.1μF
C18
0.1μF
R17
10k
R18
10k
R19
10k
C13
0.1μF
20U2
9
8
7
6
5
4
3
2
1
10
VDD
B7
B6
B5
B4
B3
B2
B1
B0
OE
A7
A6
A5
A4
A3
A2
A1
A0
T/R
GND
VCC
B7
B6
B5
B4
B3
B2
B1
B0
OE
A7
A6
A5
A4
A3
A2
A1
A0
T/R
GND
VCC
U1*
SENSE
VCM
VDD
VDD
GND
AIN+
AIN–
GND
ENC+
ENC–
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
OVDD
D11
D10
D9
D8
OGND
CLKOUT+
CLKOUT–
D7
D6
D5
OVDD
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VDD
GND
SHDN
DITH
D0
D1
D2
D3
D4
OGND
OVDD
GND
PGA
RAND
MODE
OE
OF
D15
D14
D13
D12
OGND
OVDD
48
47
46
45
44
43
42
41
40
39
38
37
VDD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
20
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VCC
WP
SCL
SDA
A0
A1
A2
A3
5
6
7
8
4
3
2
1
R25
1Ω
VDD
LT1763
C22
1μFC21, 0.01μF
R22
105k
R23
100k
C20
10μF
6.3V
C23
4.7μF
C27
100μF
6.3V
OPT.
C25
0.1μF
C26
0.1μF
VDD
3.3V
GND
E3
E1
E4
OVP
OVP
VDD U7
OUT
ADJ
GND
BYP
IN
GND
GND
SHDN
2207614 F15
+
ASSEMBLY
TYPE U1 T3 C5
C7,
C28 R30
R31,
R32 L1 INPUT FREQUENCY BITS Msps
DC918C-A LTC2207CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 16 105
DC918C-B LTC2207CUK WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < A
IN
< 140MHz 16 105
DC918C-C LTC2206CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 16 80
DC918C-D LTC2206CUK WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < A
IN
< 140MHz 16 80
DC918C-E LTC2205CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 16 65
DC918C-F LTC2205CUK WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < A
IN
< 140MHz 16 65
DC918C-G LTC2204CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 16 40
DC918C-H LTC2207CUK-14 MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 14 105
DC918C-I LTC2207CUK-14 WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < A
IN
< 140MHz 14 105
DC918C-J LTC2206CUK-14 MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 14 80
DC918C-K LTC2206CUK-14 WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < A
IN
< 140MHz 14 80
DC918C-L LTC2205CUK-14 MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < A
IN
< 70MHz 14 65
LTC2207-14/LTC2206-14
31
220714614fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)
7.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1
CHAMFER
C = 0.35
0.40 p 0.10
4847
1
2
BOTTOM VIEW—EXPOSED PAD
5.50 REF
(4-SIDES)
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UK48) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
5.50 REF
(4 SIDES) 6.10 p0.05 7.50 p0.05
0.25 p0.05
0.50 BSC
PACKAGE OUTLINE
5.15 p 0.10
5.15 p 0.10
5.15 p 0.05
5.15 p 0.05
R = 0.10
TYP
PACKAGE DESCRIPTION
LTC2207-14/LTC2206-14
32
220714614fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0809 REV C • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1747 12-Bit, 80Msps ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LTC1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC1994 Low Noise, Low Distortion Fully Differential
Input/Output Amplifi er/Driver
Low Distortion: –94dBc at 1MHz
LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2205 16-Bit, 65Msps, 3.3V ADC 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2249 14-Bit, 80Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299 Dual 14-Bit, 80Msps ADC 230mW, 71.6dB SNR, 5mm x 5mm QFN Package
LTC5512 DC-3GHz High Signal Level
Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LTC5514 Ultralow Distortion IF Amplifi er/ADC Driver with
Digitally Controlled Gain
450 MHz to 1dB BW, 47dB OIP3,
Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
LTC5515 1.5 GHz to 2.5GHz Direct Conversion Quadrature
Demodulator
High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
LTC5516 800MHz to 1.5GHz Direct Conversion
Quadrature Demodulator
High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LTC5517 40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5522 600MHz to 2.7GHz High Linearity
Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
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