Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
0 12 24 36 48 60 72 84 96 108 120
0
1
2
3
4
5
6
7
8
9
10
D004
ID = 100 A
VDS = 50 V
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
0 2 4 6 8 10 12 14 16 18 20
0
1
2
3
4
5
6
7
8
D007
TC = 25° C, I D = 100 A
TC = 125° C, I D = 100 A
Gate
(Pin 1)
Drain (Pin 2)
Source (Pin 3)
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19536KTT
SLPS540B –MARCH 2015–REVISED AUGUST 2016
CSD19536KTT 100-V N-Channel NexFET™ Power MOSFET
1
1 Features
1• Ultra-Low Qgand Qgd
• Low Thermal Resistance
• Avalanche Rated
• Lead-Free Terminal Plating
• RoHS Compliant
• Halogen Free
• D2PAK Plastic Package
2 Applications
• Secondary Side Synchronous Rectifier
• Hot Swap
• Motor Control
3 Description
This 100-V, 2-mΩ, D2PAK (TO-263) NexFET™ power
MOSFET is designed to minimize losses in power
conversion applications.
SPACE
Pin Out
Product Summary
TA= 25°C TYPICAL VALUE UNIT
VDS Drain-to-Source Voltage 100 V
QgGate Charge Total (10 V) 118 nC
Qgd Gate Charge Gate-to-Drain 17 nC
RDS(on) Drain-to-Source On-Resistance VGS = 6 V 2.2 mΩ
VGS = 10 V 2
VGS(th) Threshold Voltage 2.5 V
Device Information(1)
DEVICE QTY MEDIA PACKAGE SHIP
CSD19536KTT 500 13-Inch
Reel D2PAK Plastic
Package Tape and
Reel
CSD19536KTTT 50
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA= 25°C VALUE UNIT
VDS Drain-to-Source Voltage 100 V
VGS Gate-to-Source Voltage ±20 V
ID
Continuous Drain Current
(Package Limited) 200
A
Continuous Drain Current (Silicon Limited),
TC= 25°C 272
Continuous Drain Current (Silicon Limited),
TC= 100°C 192
IDM Pulsed Drain Current(1) 400 A
PDPower Dissipation 375 W
TJ,
Tstg Operating Junction,
Storage Temperature –55 to 175 °C
EAS Avalanche Energy, Single Pulse
ID= 127 A, L = 0.1 mH, RG= 25 Ω806 mJ
(1) Max RθJC = 0.4°C/W, Pulse duration ≤100 µs, Duty cycle ≤
1%.
.
RDS(on) vs VGS Gate Charge
2
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SLPS540B –MARCH 2015–REVISED AUGUST 2016
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6 Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
6.2 Community Resources.............................................. 7
6.3 Trademarks............................................................... 7
6.4 Electrostatic Discharge Caution................................ 7
6.5 Glossary.................................................................... 7
7 Mechanical, Packaging, and Orderable
Information............................................................. 8
7.1 KTT Package Dimensions ........................................ 8
7.2 Recommended PCB Pattern..................................... 9
7.3 Recommended Stencil Opening ............................. 10
4 Revision History
Changes from Revision A (May 2015) to Revision B Page
• Added Receiving Notification of Documentation Updates section ......................................................................................... 7
• Updated package drawing...................................................................................................................................................... 8
• Updated PCB drawing............................................................................................................................................................ 9
• Updated stencil drawing....................................................................................................................................................... 10
Changes from Original (March 2015) to Revision A Page
• Added Community Resources section ................................................................................................................................... 7
• Added PCB and stencil drawings in Mechanical, Packaging, and Orderable Information .................................................... 8
3
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5 Specifications
5.1 Electrical Characteristics
TA= 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID= 250 μA 100 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 80 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID= 250 μA 2.1 2.5 3.2 V
RDS(on) Drain-to-source on-resistance VGS = 6 V, ID= 100 A 2.2 2.8 mΩ
VGS = 10 V, ID= 100 A 2 2.4
gfs Transconductance VDS = 10 V, ID= 100 A 329 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 50 V, ƒ = 1 MHz 9250 12000 pF
Coss Output capacitance 1820 2370 pF
Crss Reverse transfer capacitance 47 61 pF
RGSeries gate resistance 1.4 2.8 Ω
QgGate charge total (10 V)
VDS = 50 V, ID= 100 A
118 153 nC
Qgd Gate charge gate-to-drain 17 nC
Qgs Gate charge gate-to-source 37 nC
Qg(th) Gate charge at Vth 24 nC
Qoss Output charge VDS = 50 V, VGS = 0 V 335 nC
td(on) Turnon delay time
VDS = 50 V, VGS = 10 V,
IDS = 100 A, RG= 0 Ω
13 ns
trRise time 8 ns
td(off) Turnoff delay time 32 ns
tfFall time 6 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 100 A, VGS = 0 V 0.9 1.1 V
Qrr Reverse recovery charge VDS= 50 V, IF= 100 A,
di/dt = 300 A/μs548 nC
trr Reverse recovery time 103 ns
5.2 Thermal Information
TA= 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance 0.4 °C/W
RθJA Junction-to-ambient thermal resistance 62 °C/W
VGS - Gate-to-Source Voltage (V)
IDS - Drain-to-Source Current (A)
1 2 3 4 5 6 7
0
25
50
75
100
125
150
175
200
D003
TC = 125° C
TC = 25° C
TC = -55° C
VDS - Drain-to-Source Voltage (V)
IDS - Drain-to-Source Current (A)
0 0.1 0.2 0.3 0.4 0.5 0.6
0
25
50
75
100
125
150
175
200
D002
VGS = 6 V
VGS = 8 V
VGS = 10 V
4
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5.3 Typical MOSFET Characteristics
TA= 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
Figure 2. Saturation Characteristics
VDS = 5 V
Figure 3. Transfer Characteristics
VSD - Source-to-Drain Voltage (V)
ISD - Source-to-Drain Current (A)
0 0.2 0.4 0.6 0.8 1
0.0001
0.001
0.01
0.1
1
10
100
D009
TC = 25° C
TC = 125° C
TC - Case Temperature (° C)
Normalized On-State Resistance
-75 -50 -25 0 25 50 75 100 125 150 175 200
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
D008
VGS = 6 V
VGS = 10 V
TC - Case Temperature (° C)
VGS(th) - Threshold Voltage (V)
-75 -50 -25 0 25 50 75 100 125 150 175 200
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
D006
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
0 2 4 6 8 10 12 14 16 18 20
0
1
2
3
4
5
6
7
8
D007
TC = 25° C, I D = 100 A
TC = 125° C, I D = 100 A
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
0 12 24 36 48 60 72 84 96 108 120
0
1
2
3
4
5
6
7
8
9
10
D004
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
0 10 20 30 40 50 60 70 80 90 100
1
10
100
1000
10000
100000
D005
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
5
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Typical MOSFET Characteristics (continued)
TA= 25°C (unless otherwise stated)
VDS = 50 V ID= 100 A
Figure 4. Gate Charge Figure 5. Capacitance
ID= 250 µA
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
ID= 100 A
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
TC - Case Temperature (° C)
IDS - Drain-to-Source Current (A)
-50 -25 0 25 50 75 100 125 150 175 200
0
25
50
75
100
125
150
175
200
225
D012
VDS - Drain-to-Source Voltage (V)
IDS - Drain-to-Source Current (A)
0.1 1 10 100 1000
0.1
1
10
100
1000
D010
DC
10 ms 1 ms
100 µs
TAV - Time in Avalanche (ms)
IAV - Peak Avalanche Current (A)
0.01 0.1 1
10
100
500
D011
TC = 25q C
TC = 125q C
6
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SLPS540B –MARCH 2015–REVISED AUGUST 2016
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Typical MOSFET Characteristics (continued)
TA= 25°C (unless otherwise stated)
Single pulse, max RθJC = 0.4°C/W
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
7
CSD19536KTT
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Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
C
1.32
1.22
1.4
1.17
8.55
8.15
2X 5.08
2[.0]X 1.36
1.23
15.5
14.7
2[.0]X 0.9
0.77
4.7
4.4
0.25
00.25
GAGE PLANE
7.48
7.08
8
0
0.47
0.34
2.6
2
1.75 MAX
B
9.25
9.05
A
10.26
10.06
8°
0°
2.6
2
0.25
GAGE PLANE
4222117/A 08/2015
1
0.25 C A B
3
NOTE 3 EXPOSED
THERMAL PAD
OPTIONAL LEAD FORM
2
8
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SLPS540B –MARCH 2015–REVISED AUGUST 2016
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT Package Dimensions
Notes:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Features may not exist and shape may vary per different assembly sites.
Table 1. Pin Configuration
POSITION DESIGNATION
Pin 1 Gate
Pin 2 / Tab Drain
Pin 3 Source
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
(7.48)
(8.55)
2X (3.82)
2X (1.05)
(3.4) (6.9)
(5.08)
(R ) TYP0.05
4222117/A 08/2015
PKG
SYMM
PKG
OPENING
SOLDER MASK METAL
NON SOLDER MASK
DEFINED SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
9
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7.2 Recommended PCB Pattern
Note:
1. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas
Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
42X (0.97)
42X (0.95)
(1.17) TYP
(1.15) TYP
(0.48) TYP
(6.9)
(5.08)
(R ) TYP0.05
2X (3.82) 2X (1.05)
SYMM
PKG
10
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SLPS540B –MARCH 2015–REVISED AUGUST 2016
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7.3 Recommended Stencil Opening
Notes:
1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
2. Board assembly site may have different recommendations for stencil design.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jun-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD19536KTT ACTIVE DDPAK/
TO-263 KTT 3 500 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -55 to 175 CSD19536KTT
CSD19536KTTT ACTIVE DDPAK/
TO-263 KTT 3 50 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -55 to 175 CSD19536KTT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jun-2018
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CSD19536KTT DDPAK/
TO-263 KTT 3 500 330.0 24.4 10.8 16.3 5.11 16.0 24.0 Q2
CSD19536KTTT DDPAK/
TO-263 KTT 3 50 330.0 24.4 10.8 16.3 5.11 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Aug-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD19536KTT DDPAK/TO-263 KTT 3 500 340.0 340.0 38.0
CSD19536KTTT DDPAK/TO-263 KTT 3 50 340.0 340.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Aug-2016
Pack Materials-Page 2
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