Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD19536KTT SLPS540B - MARCH 2015 - REVISED AUGUST 2016 CSD19536KTT 100-V N-Channel NexFETTM Power MOSFET 1 Features * * * * * * * 1 Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Lead-Free Terminal Plating RoHS Compliant Halogen Free D2PAK Plastic Package TA = 25C TYPICAL VALUE Drain-to-Source Voltage 100 V Qg Gate Charge Total (10 V) 118 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage 17 nC VGS = 6 V 2.2 VGS = 10 V 2 m 2.5 V Device Information(1) 2 Applications * * * UNIT VDS Secondary Side Synchronous Rectifier Hot Swap Motor Control DEVICE QTY CSD19536KTT 500 CSD19536KTTT 50 MEDIA PACKAGE 13-Inch Reel 2 SHIP Tape and Reel D PAK Plastic Package (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description Absolute Maximum Ratings This 100-V, 2-m, D2PAK (TO-263) NexFETTM power MOSFET is designed to minimize losses in power conversion applications. TA = 25C SPACE VALUE UNIT VDS Drain-to-Source Voltage 100 V VGS Gate-to-Source Voltage 20 V Continuous Drain Current (Package Limited) 200 Continuous Drain Current (Silicon Limited), TC = 25C 272 Continuous Drain Current (Silicon Limited), TC = 100C 192 IDM Pulsed Drain Current(1) 400 A PD Power Dissipation 375 W TJ, Tstg Operating Junction, Storage Temperature -55 to 175 C EAS Avalanche Energy, Single Pulse ID = 127 A, L = 0.1 mH, RG = 25 806 mJ Pin Out ID Drain (Pin 2) Gate (Pin 1) Source (Pin 3) A (1) Max RJC = 0.4C/W, Pulse duration 100 s, Duty cycle 1%. . RDS(on) vs VGS Gate Charge 10 TC = 25 C, I D = 100 A TC = 125 C, I D = 100 A 7 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 8 6 5 4 3 2 1 0 ID = 100 A 9 VDS = 50 V 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 0 12 24 36 48 60 72 84 Qg - Gate Charge (nC) 96 108 120 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD19536KTT SLPS540B - MARCH 2015 - REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 6.5 7 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 KTT Package Dimensions ........................................ 8 7.2 Recommended PCB Pattern..................................... 9 7.3 Recommended Stencil Opening ............................. 10 4 Revision History Changes from Revision A (May 2015) to Revision B Page * Added Receiving Notification of Documentation Updates section ......................................................................................... 7 * Updated package drawing ...................................................................................................................................................... 8 * Updated PCB drawing ............................................................................................................................................................ 9 * Updated stencil drawing ....................................................................................................................................................... 10 Changes from Original (March 2015) to Revision A Page * Added Community Resources section ................................................................................................................................... 7 * Added PCB and stencil drawings in Mechanical, Packaging, and Orderable Information .................................................... 8 2 Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT CSD19536KTT www.ti.com SLPS540B - MARCH 2015 - REVISED AUGUST 2016 5 Specifications 5.1 Electrical Characteristics TA = 25C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 A IDSS Drain-to-source leakage current VGS = 0 V, VDS = 80 V 1 A IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 A 2.5 3.2 V 2.2 2.8 VGS = 10 V, ID = 100 A 2 2.4 VDS = 10 V, ID = 100 A 329 RDS(on) Drain-to-source on-resistance gfs Transconductance 100 2.1 VGS = 6 V, ID = 100 A V m S DYNAMIC CHARACTERISTICS Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (10 V) 118 Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source Qg(th) Gate charge at Vth Qoss Output charge td(on) Turnon delay time tr Rise time td(off) Turnoff delay time tf Fall time VGS = 0 V, VDS = 50 V, = 1 MHz VDS = 50 V, ID = 100 A VDS = 50 V, VGS = 0 V VDS = 50 V, VGS = 10 V, IDS = 100 A, RG = 0 9250 12000 pF 1820 2370 pF 47 61 pF 1.4 2.8 153 nC 17 nC 37 nC 24 nC 335 nC 13 ns 8 ns 32 ns 6 ns DIODE CHARACTERISTICS VSD Diode forward voltage ISD = 100 A, VGS = 0 V 0.9 1.1 V Qrr Reverse recovery charge nC Reverse recovery time VDS= 50 V, IF = 100 A, di/dt = 300 A/s 548 trr 103 ns 5.2 Thermal Information TA = 25C (unless otherwise stated) MAX UNIT RJC Junction-to-case thermal resistance THERMAL METRIC MIN TYP 0.4 C/W RJA Junction-to-ambient thermal resistance 62 C/W Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT 3 CSD19536KTT SLPS540B - MARCH 2015 - REVISED AUGUST 2016 www.ti.com 5.3 Typical MOSFET Characteristics TA = 25C (unless otherwise stated) 200 200 175 175 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) Figure 1. Transient Thermal Impedance 150 125 100 75 50 VGS = 6 V VGS = 8 V VGS = 10 V 25 0 TC = 125 C TC = 25 C TC = -55 C 150 125 100 75 50 25 0 0 0.1 0.2 0.3 0.4 0.5 VDS - Drain-to-Source Voltage (V) 0.6 1 D002 2 3 4 5 VGS - Gate-to-Source Voltage (V) 6 7 D003 VDS = 5 V Figure 2. Saturation Characteristics 4 Submit Documentation Feedback Figure 3. Transfer Characteristics Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT CSD19536KTT www.ti.com SLPS540B - MARCH 2015 - REVISED AUGUST 2016 Typical MOSFET Characteristics (continued) TA = 25C (unless otherwise stated) 100000 9 10000 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 1000 100 10 2 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1 1 0 0 12 24 36 48 60 72 84 Qg - Gate Charge (nC) VDS = 50 V 96 108 0 120 10 20 D004 100 D005 Figure 5. Capacitance 3.1 8 RDS(on) - On-State Resistance (m:) 2.9 VGS(th) - Threshold Voltage (V) 90 ID = 100 A Figure 4. Gate Charge 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 -75 30 40 50 60 70 80 VDS - Drain-to-Source Voltage (V) TC = 25 C, I D = 100 A TC = 125 C, I D = 100 A 7 6 5 4 3 2 1 0 -50 -25 0 0 25 50 75 100 125 150 175 200 TC - Case Temperature ( C) D006 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 ID = 250 A Figure 7. On-State Resistance vs Gate-to-Source Voltage Figure 6. Threshold Voltage vs Temperature 100 2.2 VGS = 6 V VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 2.4 2 1.8 1.6 1.4 1.2 1 0.8 TC = 25 C TC = 125 C 10 1 0.1 0.01 0.001 0.6 0.4 -75 0.0001 -50 -25 0 25 50 75 100 125 150 175 200 TC - Case Temperature ( C) D008 0 0.2 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 ID = 100 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT 5 CSD19536KTT SLPS540B - MARCH 2015 - REVISED AUGUST 2016 www.ti.com Typical MOSFET Characteristics (continued) TA = 25C (unless otherwise stated) 500 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 DC 10 ms 0.1 0.1 1 ms 100 s 1 10 100 VDS - Drain-to-Source Voltage (V) 1000 TC = 25q C TC = 125q C 100 10 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single pulse, max RJC = 0.4C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 225 200 175 150 125 100 75 50 25 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature ( C) 150 175 200 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT CSD19536KTT www.ti.com SLPS540B - MARCH 2015 - REVISED AUGUST 2016 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT 7 CSD19536KTT SLPS540B - MARCH 2015 - REVISED AUGUST 2016 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 KTT Package Dimensions 15.5 14.7 9.25 9.05 A B 3 10.26 10.06 2X 5.08 2 1 2[.0]X 1.36 1.23 2[.0]X 0.9 0.77 1.75 MAX 0.25 C A B 1.4 1.17 0.47 0.34 C 4.7 4.4 8 0 0.25 0 1.32 1.22 2.6 2 0.25 GAGE PLANE 7.48 7.08 8 0 8.55 8.15 2.6 2 0.25 GAGE PLANE NOTE 3 OPTIONAL LEAD FORM EXPOSED THERMAL PAD 4222117/A 08/2015 Notes: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Features may not exist and shape may vary per different assembly sites. Table 1. Pin Configuration POSITION 8 DESIGNATION Pin 1 Gate Pin 2 / Tab Drain Pin 3 Source Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT CSD19536KTT www.ti.com SLPS540B - MARCH 2015 - REVISED AUGUST 2016 7.2 Recommended PCB Pattern PKG (3.4) (6.9) (R0.05) TYP PKG SYMM (5.08) (8.55) 2X (1.05) 2X (3.82) (7.48) 0.07 MAX ALL AROUND SOLDER MASK OPENING 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED NON SOLDER MASK DEFINED 4222117/A 08/2015 Note: 1. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT 9 CSD19536KTT SLPS540B - MARCH 2015 - REVISED AUGUST 2016 www.ti.com 7.3 Recommended Stencil Opening (1.17) TYP 42X (0.97) (0.48) TYP 2X (3.82) 2X (1.05) 42X (0.95) (R0.05) TYP (1.15) TYP SYMM (5.08) (6.9) PKG Notes: 1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 2. Board assembly site may have different recommendations for stencil design. 10 Submit Documentation Feedback Copyright (c) 2015-2016, Texas Instruments Incorporated Product Folder Links: CSD19536KTT PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CSD19536KTT ACTIVE DDPAK/ TO-263 KTT 3 500 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -55 to 175 CSD19536KTT CSD19536KTTT ACTIVE DDPAK/ TO-263 KTT 3 50 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -55 to 175 CSD19536KTT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2018 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) CSD19536KTT DDPAK/ TO-263 KTT 3 500 330.0 24.4 CSD19536KTTT DDPAK/ TO-263 KTT 3 50 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 16.3 5.11 16.0 24.0 Q2 10.8 16.3 5.11 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD19536KTT DDPAK/TO-263 KTT 3 500 340.0 340.0 38.0 CSD19536KTTT DDPAK/TO-263 KTT 3 50 340.0 340.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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