PEMD10,115 - NXP - Datasheet.Technology

1. Product profile

1.1 General description

NPN/PNP Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic

packages.

1.2 Features and benefits

1.3 Applications

Low current peripheral driver

Control of IC inputs

Replaces general-purpose transistors in digital applications

1.4 Quick reference data

PEMD10; PUMD10

NPN/PNP resistor-equipped transistors;

R1 = 2.2 k, R2 = 47 k

Rev. 6 — 4 January 2012 Product data sheet

Table 1. Product overview

Type number Package PNP/PNP

complement NPN/NPN

complement Package

configuration

NXP JEITA

PEMD10 SOT666 - PEMB10 PEMH10 ultra small and flat lead

PUMD10 SOT363 SC-88 PUMB10 PUMH10 very small

100 mA output current capability Reduces component count

Built-in bias resistors Reduces pick and place costs

Simplifies circuit design AEC-Q101 qualified

Table 2. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

VCEO collector-emitter voltage open base - - 50 V

IOoutput current - - 100 m A

R1 bias resistor 1 (input) 1.54 2.20 2.86 k

R2/R1 bias resistor ratio 17 21 26

Product data sheet Rev. 6 — 4 January 2012 2 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

2. Pinning information

3. Ordering information

4. Marking

[1] * = placeholder for manufacturing site code.

Table 3. Pinning

Pin Description Simplified outline Graphic symbol

1 GND (emitter) TR1

2 input (base) TR1

3 output (collector) TR2

4 GND (emitter) TR2

5 input (base) TR2

6 output (collector) TR1

001aab555

6 45

1 32

65 4

123

TR1 TR2

R2 R1

006aaa143

Table 4. Orderin g information

Type number Package

Name Description Version

PEMD10 - plastic surface-mounted package; 6 leads SOT666

PUMD10 SC-88 plastic surface-mounted package; 6 leads SOT363

Table 5. Marking codes

Type number Marking code[1]

PEMD10 D1

PUMD10 D*0

Product data sheet Rev. 6 — 4 January 2012 3 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

5. Limiting values

[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

[2] Reflow soldering is the only recommended soldering method.

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

VCBO collector-base voltage open emitter - 50 V

VCEO collector-emitter voltage open base - 50 V

VEBO emitter-base voltage open collector - 5 V

VIinput voltage TR1

positive - +12 V

negative - 5V

input voltage TR2

positive - +5 V

negative - 12 V

IOoutput current - 100 mA

ICM peak collector current - 100 mA

Ptot total power dissipation Tamb 25 C[1]

PEMD10 (SOT666) [2] -200mW

PUMD10 (SOT363) - 200 mW

Per device

Ptot total power dissipation Tamb 25 C[1]

PEMD10 (SOT666) [2] -300mW

PUMD10 (SOT363) - 300 mW

Tjjunction temperature - 150 C

Tamb ambient temp erature 65 +150 C

Tstg storage temperature 65 +150 C

Product data sheet Rev. 6 — 4 January 2012 4 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

6. Thermal characteristics

[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.

[2] Reflow soldering is the only recommended soldering method.

SOT363 and SOT666; FR4 PCB, standard footprint

Fig 1. Per device: Power derating curve

Tamb (°C)

-75 17512525 75-25

006aac749

200

100

300

400

Ptot

(mW)

Table 7. Thermal characteris tics

Symbol Parameter Conditions Min Typ Max Unit

Per transis tor

Rth(j-a) thermal resistance from

junction to ambient in free air [1]

PEMD10 (SOT666) [2] --625K/W

PUMD10 (SOT363) - - 625 K/W

Per device

Rth(j-a) thermal resistance from

junction to ambient in free air [1]

PEMD10 (SOT666) [2] --417K/W

PUMD10 (SOT363) - - 417 K/W

Product data sheet Rev. 6 — 4 January 2012 5 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

FR4 PCB, standard footprint

Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration for

PEMD10 (SOT666); typical values

FR4 PCB, standard footprint

Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration for

PUMD10 (SOT363); typical values

006aac751

10-5 1010-2

10-4 102

10-1 tp (s)

10-3 103

102

103

Zth(j-a)

(K/W)

duty cycle = 1

0.75 0.5

0.33 0.2

0.1

0.05

0.02 0.01

006aac750

10-5 1010-2

10-4 102

10-1 tp (s)

10-3 103

102

103

Zth(j-a)

(K/W)

duty cycle = 1

0.75 0.5

0.33

0.2

0.1 0.05

0.02 0.01

Product data sheet Rev. 6 — 4 January 2012 6 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

7. Characteristics

[1] Characteristics of built-in transistor.

Table 8. Characteristics

Tamb =25



C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

ICBO collector-base

cut-off current VCB =50V; I

E= 0 A - - 100 nA

ICEO collector-emitter

cut-off current VCE =30V; I

B= 0 A - - 100 nA

VCE =30V; I

B=0A;

Tj= 150 C--5A

IEBO emitter-base

cut-off current VEB =5V; I

C= 0 A - - 180 A

hFE DC current gain VCE =5V; I

C= 10 mA 100 - -

VCEsat collector-emitter

saturation voltage IC=5mA; I

B= 0.25 mA - - 100 mV

VI(off) off-state input

voltage VCE =5V; I

C=100A-0.60.5V

VI(on) on-state input

voltage VCE = 0.3 V; IC=5mA 1.1 0.75 - V

R1 bias resistor 1 (inp u t) 1.54 2.20 2.86 k

R2/R1 bias resistor ratio 17 21 26

Cccollector capacitance VCB =10V; I

E=i

e=0A;

f=1MHz

TR1 (NPN) - - 2.5 pF

TR2 (PNP) - - 3 pF

fTtransition frequency VCB =5V; I

C=10mA;

f = 100 MHz [1]

TR1 (NPN) - 230 - MHz

TR2 (PNP) - 180 - MHz

Product data sheet Rev. 6 — 4 January 2012 7 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

VCE =5V

(1) Tamb = 100 C

(2) Tamb =25C

(3) Tamb =40 C

IC/IB=20

(1) Tamb = 100 C

(2) Tamb =25C

(3) Tamb =40 C

Fig 4. TR1 (NPN): DC current gain as a function of

collector current; typical valu es F ig 5. TR1 (NPN): Collector-emitter saturation

voltage as a fun ction of collect or cur r e nt;

typical values

VCE =0.3V

(1) Tamb =40 C

(2) Tamb =25C

(3) Tamb = 100 C

VCE =5V

(1) Tamb =40 C

(2) Tamb =25C

(3) Tamb = 100 C

Fig 6. TR1 (NPN): On-state input voltage as a

function of collector current; typical values Fig 7. TR1 (NPN): Off-state input voltage as a

function of collector current; typical values

IC (mA)

10-1 102

101

006aac805

102

103

hFE

(1)

(2)

(3)

006aac810

IC (mA)

10-1 102

101

10-1

VCEsat

(V)

10-2

(1)

(2)

(3)

006aac811

IC (mA)

10-1 102

101

VI(on)

(V)

10-1

(1)

(2)

(3)

006aac812

IC (mA)

10-1 101

VI(off)

(V)

10-1

(1)

(2)

(3)

Product data sheet Rev. 6 — 4 January 2012 8 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

f=1MHz; T

amb =25CV

CE =5V; T

amb =25C

Fig 8. TR1 (NPN): Collector capacit ance as a function

of collector-base voltag e; ty pic al values Fig 9. TR1 (NPN): Transition frequency as a function

of collector current; typical values of built-in

transistor

VCE =5V

(1) Tamb = 100 C

(2) Tamb =25C

(3) Tamb =40 C

IC/IB=20

(1) Tamb = 100 C

(2) Tamb =25C

(3) Tamb =40 C

Fig 10. TR2 (PNP): DC current gain as a function of

collector current; typical valu es Fig 11. TR2 (PNP): Collector-emitter saturation

voltage as a fun ction of collect or cur r e nt;

typical values

VCB (V)

0504020 3010

006aac813

(pF)

006aac757

IC (mA)

10-1 102

101

102

103

(MHz)

IC (mA)

-10-1 -102

-10-1

006aac814

102

103

hFE

(1)

(2)

(3)

006aac815

IC (mA)

-10-1 -102

-10-1

-1

VCEsat

(V)

-10-2

(1)

(2)

(3)

Product data sheet Rev. 6 — 4 January 2012 9 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

VCE =0.3 V

(1) Tamb =40 C

(2) Tamb =25C

(3) Tamb = 100 C

VCE =5V

(1) Tamb =40 C

(2) Tamb =25C

(3) Tamb = 100 C

Fig 12. TR2 (PNP): On-state input voltage as a

function of collector current; typical values Fig 13. TR2 (PNP): Off-state input voltage as a

function of collector current; typical values

f = 1 MHz; Tamb =25CV

CE =5V; T

amb =25C

Fig 14. TR2 (PNP): Collector capacit ance as a function

of collector-base voltag e; ty pic al values Fig 15. TR2 (PNP): Transition frequency as a function

of collector current; typical values of built-in

transistor

006aac816

IC (mA)

-10-1 -102

-10-1

-1

-10

VI(on)

(V)

-10-1

(1)

(2)

(3)

006aac817

IC (mA)

-10-1 -10-1

-1

VI(off)

(V)

-10-1

(1)

(2)

(3)

VCB (V)

0 -50-40-20 -30-10

006aac818

(pF)

006aac763

IC (mA)

-10-1 -102

-10-1

102

103

(MHz)

Product data sheet Rev. 6 — 4 January 2012 10 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

8. Test information

8.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is

suitable for use in automotive applications.

9. Package outline

Fig 16. Package outline PEMD10 (SOT666)

Fig 17. Package outline PUMD10 (SOT363/SC-88)

Dimensions in mm 04-11-08

1.7

1.5

1.7

1.5

1.3

1.1

0.18

0.08

0.27

0.17

0.5

pin 1 index

123

456

0.6

0.5

0.3

0.1

06-03-16Dimensions in mm

0.25

0.10

0.3

0.2

pin 1

index

1.3

0.65

2.2

2.0 1.35

1.15

2.2

1.8 1.1

0.8

0.45

0.15

132

465

Product data sheet Rev. 6 — 4 January 2012 11 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

10. Packing information

[1] For further information and the availability of packing methods, see Section 14.

[2] T1: normal taping

[3] T2: reverse taping

11. Soldering

Table 9. Packing methods

The indicated -xxx are the last thre e digits of the 12NC ordering code.[1]

Type number Package Description Packing quantity

3000 4000 8000 10000

PEMD10 SOT666 2 mm pitch, 8 mm tape and reel - - -315 -

4 mm pitch, 8 mm tape and reel - -115 - -

PUMD10 SOT363 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135

4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165

Reflow soldering is the only recommended soldering method.

Fig 18. Reflow soldering footprint PEMD10 (SOT666)

solder lands

placement area

occupied area

solder paste

sot666_fr

2.75

2.45

2.1

1.6

0.4

(6×)

0.55

(2×)

0.25

(2×)

0.6

(2×)

0.65

(2×)

0.3

(2×)

0.325

(4×)

0.45

(4×)

0.5

(4×)

0.375

(4×)

1.72

1.7

1.0750.538

Dimensions in mm

Product data sheet Rev. 6 — 4 January 2012 12 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

Fig 19. Reflow soldering footprint PUMD10 (SOT363/SC-88)

Fig 20. Wave soldering footprint PUMD10 (SOT363/SC-88)

solder lands

solder resist

occupied area

solder paste

sot363_fr

2.65

2.35 0.4 (2×)

0.6

(2×)

0.5

(4×)

0.5

(4×)

0.6

(4×)

0.6

(4×)

1.5

1.8

Dimensions in mm

sot363_fw

solder lands

solder resist

occupied area

preferred transport

direction during soldering

5.3

1.3 1.3

1.5

0.3

1.5

4.5

2.45

2.5

Dimensions in mm

Product data sheet Rev. 6 — 4 January 2012 13 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

12. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PEMD10_PUMD10 v.6 20120104 Product data sheet - PEMD10_PUMD10 v.5

Modifications: •The format of this document has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 1 “Product profile”: updated

•Section 4 “Marking”: updated

•Table 6 “Limiting values ”: Ptot updated according to the latest measurements

•Table 7 “Thermal characteristics”: updated according to the late st measurements

•Table 8 “Characteristics”: ICEO upd ated according to the latest measurements, fT added

•Figure 1 to 3, 8, 9, 14 and 15: added

•Figure 4 to 7 and Figure 10 to 13: updated

•Section 8 “Test information”: added

•Section 11 “Soldering”: added

•Section 13 “Legal information”: updated

PEMD10_PUMD10 v.5 20040415 Product data sheet - PEMD10_PUMD10 v.4

PEMD10_PUMD10 v.4 20031104 Product specification - PEMD10 v.2

PUMD10 v.3

Product data sheet Rev. 6 — 4 January 2012 14 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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Draft — The document is a draft version only. The content is still under

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full information. For detailed and full information see the relevant full data

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 6 — 4 January 2012 15 of 16

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

13.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

14. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PEMD10; PUMD10

NPN/PNP resistor-equipped transistors; R1 = 2.2 k, R2 = 47 k

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 January 2012

Document identifier: PEMD10_PUMD10

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15. Contents

1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4

7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 Test information. . . . . . . . . . . . . . . . . . . . . . . . 10

8.1 Quality information . . . . . . . . . . . . . . . . . . . . . 10

9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

10 Packing information . . . . . . . . . . . . . . . . . . . . 11

11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Contact information. . . . . . . . . . . . . . . . . . . . . 15

15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16