1
LT1963 Series
1963fc
TYPICAL APPLICATION
U
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
1.5A, Low Noise,
Fast Transient Response
LDO Regulators
■
Optimized for Fast Transient Response
■
Output Current: 1.5A
■
Dropout Voltage: 340mV
■
Low Noise: 40
µ
V
RMS
(10Hz to 100kHz)
■
1mA Quiescent Current
■
No Protection Diodes Needed
■
Controlled Quiescent Current in Dropout
■
Fixed Output Voltages: 1.5V, 1.8V, 2.5V, 3.3V
■
Adjustable Output from 1.21V to 20V
■
<1µA Quiescent Current in Shutdown
■
Stable with 10µF Output Capacitor
■
Reverse Battery Protection
■
No Reverse Current
■
Thermal Limiting
■
5-Lead TO-220, DD, 3-Lead SOT-223, 8-Lead SO
and 16-Lead TSSOP Packages
The LT
®
1963 series are low dropout regulators optimized
for fast transient response. The devices are capable of
supplying 1.5A of output current with a dropout voltage of
340mV. Operating quiescent current is 1mA, dropping to
<1µA in shutdown. Quiescent current is well controlled; it
does not rise in dropout as it does with many other
regulators. In addition to fast transient response, the
LT1963 regulators have very low output noise which
makes them ideal for sensitive RF supply applications.
Output voltage range is from 1.21V to 20V. The LT1963
regulators are stable with output capacitors as low as
10µF. Internal protection circuitry includes reverse battery
protection, current limiting, thermal limiting and reverse
current protection. The devices are available in fixed
output voltages of 1.5V, 1.8V, 2.5V, 3.3V and as an
adjustable device with a 1.21V reference voltage. The
LT1963 regulators are available in 5-lead TO-220, DD,
3-lead SOT-223, 8-lead SO, and Exposed Pad 16-lead
TSSOP packages.
3.3V to 2.5V Regulator
■
3.3V to 2.5V Logic Power Supplies
■
Post Regulator for Switching Supplies
IN
SHDN
10µF
1963 TA01
OUT
VIN > 3V
SENSE
GND
LT1963-2.5
2.5V
1.5A
10µF
++
OUTPUT CURRENT (A)
0
DROPOUT VOLTAGE (mV)
200
300
1.6
1963 TA02
100
00.4 0.8 1.2
0.2 0.6 1.0 1.4
400
150
250
50
350
Dropout Voltage
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 6118263, 6144250.
2
LT1963 Series
1963fc
(Note 1)
IN Pin Voltage ........................................................ ±20V
OUT Pin Voltage .................................................... ±20V
Input to Output Differential Voltage (Note 2) ......... ±20V
SENSE Pin Voltage ............................................... ±20V
ADJ Pin Voltage ...................................................... ±7V
SHDN Pin Voltage ................................................. ±20V
Output Short-Circuit Duration ......................... Indefinite
Operating Junction Temperature Range –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
LT1963ES8
LT1963ES8-1.5
LT1963ES8-1.8
LT1963ES8-2.5
LT1963ES8-3.3
ORDER PART NUMBER
LT1963EST-1.5
LT1963EST-1.8
LT1963EST-2.5
LT1963EST-3.3
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ST PART MARKING ORDER PART NUMBER S8 PART MARKING
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
196315
196318
196325
196333
1963
196315
196318
196325
196333
3
2
1
FRONT VIEW
TAB IS
GND
OUT
GND
IN
ST PACKAGE
3-LEAD PLASTIC SOT-223
T
JMAX
= 150°C, θ
JA
= 50°C/ W
1
2
3
4
8
7
6
5
TOP VIEW
IN
GND
GND
SHDN
OUT
SENSE/ADJ*
GND
NC
S8 PACKAGE
8-LEAD PLASTIC SO
*PIN 2 = SENSE FOR LT1963-1.5/LT1963-1.8/
LT1963-2.5/LT1963-3.3
= ADJ FOR LT1963
T
JMAX
= 150°C, θ
JA
= 70°C/ W
LT1963ET
LT1963ET-1.5
LT1963ET-1.8
LT1963ET-2.5
LT1963ET-3.3
ORDER PART NUMBER
LT1963EQ
LT1963EQ-1.5
LT1963EQ-1.8
LT1963EQ-2.5
LT1963EQ-3.3
ORDER PART NUMBER
T
JMAX
= 150°C, θ
JA
= 30°C/ W
*PIN 5 = SENSE FOR LT1963-1.5/LT1963-1.8/
LT1963-2.5/LT1963-3.3
= ADJ FOR LT1963
*PIN 5 = SENSE FOR LT1963-1.5/LT1963-1.8/
LT1963-2.5/LT1963-3.3
= ADJ FOR LT1963
T
JMAX
= 150°C, θ
JA
= 50°C/ W
Q PACKAGE
5-LEAD PLASTIC DD
TAB IS
GND
FRONT VIEW
SENSE/ADJ*
OUT
GND
IN
SHDN
5
4
3
2
1
T PACKAGE
5-LEAD PLASTIC TO-220
SENSE/
ADJ*
OUT
GND
IN
SHDN
FRONT VIEW
TAB IS
GND
5
4
3
2
1
LT1963EFE
LT1963EFE-1.5
LT1963EFE-1.8
LT1963EFE-2.5
LT1963EFE-3.3
ORDER PART NUMBER FE PART MARKING
1963EFE
1963EFE15
1963EFE18
1963EFE25
1963EFE33
T
JMAX
= 150°C, θ
JA
= 38°C/ W
*PIN 6 = SENSE FOR LT1963-1.5/
LT1963-1.8/LT1963-2.5/
LT1963-3.3
= ADJ FOR LT1963
FE PACKAGE
16-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17) IS GND. MUST BE
SOLDERED TO THE PCB.
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
NC
OUT
OUT
OUT
SENSE/ADJ*
GND
GND
GND
NC
IN
IN
IN
NC
SHDN
GND
17
3
LT1963 Series
1963fc
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Notes 4,12) I
LOAD
= 0.5A 1.9 V
I
LOAD
= 1.5A 2.5V < V
IN
< 20V, 1mA < I
LOAD
< 1.5A ●2.1 2.5 V
Regulated Output Voltage (Note 5) LT1963-1.5 V
IN
= 2.21V, I
LOAD
= 1mA 1.477 1.500 1.523 V
2.5V < V
IN
< 20V, 1mA < I
LOAD
< 1.5A ●1.447 1.500 1.545 V
LT1963-1.8 V
IN
= 2.3V, I
LOAD
= 1mA 1.773 1.800 1.827 V
2.8V < V
IN
< 20V, 1mA < I
LOAD
< 1.5A ●1.737 1.800 1.854 V
LT1963-2.5 V
IN
= 3V, I
LOAD
= 1mA 2.462 2.500 2.538 V
3.5V < V
IN
< 20V, 1mA < I
LOAD
< 1.5A ●2.412 2.500 2.575 V
LT1963-3.3 V
IN
= 3.8V, I
LOAD
= 1mA 3.250 3.300 3.350 V
4.3V < V
IN
< 20V, 1mA < I
LOAD
< 1.5A ●3.200 3.300 3.400 V
ADJ Pin Voltage LT1963 V
IN
= 2.21V, I
LOAD
= 1mA 1.192 1.210 1.228 V
(Notes 4, 5) 2.5V < V
IN
< 20V, 1mA < I
LOAD
< 1.5A ●1.174 1.210 1.246 V
Line Regulation LT1963-1.5 ∆V
IN
= 2.21V to 20V, I
LOAD
= 1mA ●2.0 10 mV
LT1963-1.8 ∆V
IN
= 2.3V to 20V, I
LOAD
= 1mA ●2.5 10 mV
LT1963-2.5 ∆V
IN
= 3V to 20V, I
LOAD
= 1mA ●3.0 10 mV
LT1963-3.3 ∆V
IN
= 3.8V to 20V, I
LOAD
= 1mA ●3.5 10 mV
LT1963 (Note 4) ∆V
IN
= 2.21V to 20V, I
LOAD
= 1mA ●1.5 10 mV
Load Regulation LT1963-1.5 V
IN
= 2.5V, ∆I
LOAD
= 1mA to 1.5A 2 9 mV
V
IN
= 2.5V, ∆I
LOAD
= 1mA to 1.5A ●18 mV
LT1963-1.8 V
IN
= 2.8V, ∆I
LOAD
= 1mA to 1.5A 2 10 mV
V
IN
= 2.8V, ∆I
LOAD
= 1mA to 1.5A ●20 mV
LT1963-2.5 V
IN
= 3.5V, ∆I
LOAD
= 1mA to 1.5A 2.5 15 mV
V
IN
= 3.5V, ∆I
LOAD
= 1mA to 1.5A ●30 mV
LT1963-3.3 V
IN
= 4.3V, ∆I
LOAD
= 1mA to 1.5A 3 20 mV
V
IN
= 4.3V, ∆I
LOAD
= 1mA to 1.5A ●35 mV
LT1963 (Note 4) V
IN
= 2.5V, ∆I
LOAD
= 1mA to 1.5A 2 8 mV
V
IN
= 2.5V, ∆I
LOAD
= 1mA to 1.5A ●15 mV
Dropout Voltage I
LOAD
= 1mA 0.02 0.06 V
V
IN
= V
OUT(NOMINAL)
I
LOAD
= 1mA ●0.10 V
(Notes 6, 7, 12) I
LOAD
= 100mA 0.10 0.17 V
I
LOAD
= 100mA ●0.22 V
I
LOAD
= 500mA 0.19 0.27 V
I
LOAD
= 500mA ●0.35 V
I
LOAD
= 1.5A 0.34 0.45 V
I
LOAD
= 1.5A ●0.55 V
GND Pin Current I
LOAD
= 0mA ●1.0 1.5 mA
V
IN
= V
OUT(NOMINAL)
+ 1V I
LOAD
= 1mA ●1.1 1.6 mA
(Notes 6, 8) I
LOAD
= 100mA ●3.8 5.5 mA
I
LOAD
= 500mA ●15 25 mA
I
LOAD
= 1.5A ●80 120 mA
Output Voltage Noise C
OUT
= 10µF, I
LOAD
= 1.5A, BW = 10Hz to 100kHz 40 µV
RMS
ADJ Pin Bias Current (Notes 4, 9) 3 10 µA
Shutdown Threshold V
OUT
= Off to On ●0.90 2 V
V
OUT
= On to Off ●0.25 0.75 V
SHDN Pin Current V
SHDN
= 0V 0.01 1 µA
(Note 10) V
SHDN
= 20V 3 30 µA
Quiescent Current in Shutdown V
IN
= 6V, V
SHDN
= 0V 0.01 1 µA
Ripple Rejection V
IN
– V
OUT
= 1.5V (Avg), V
RIPPLE
= 0.5V
P-P
,5563dB
f
RIPPLE
= 120Hz, I
LOAD
= 0.75A
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3)
ELECTRICAL CHARACTERISTICS
4
LT1963 Series
1963fc
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Limit V
IN
= 7V, V
OUT
= 0V 2 A
V
IN
= V
OUT(NOMINAL)
+ 1V, ∆V
OUT
= – 0.1V ●1.6 A
Input Reverse Leakage Current (Note 13) Q, T, S8 Packages V
IN
= – 20V, V
OUT
= 0V ●1mA
ST Package V
IN
= –20V, V
OUT
= 0V ●2mA
Reverse Output Current (Note 11) LT1963-1.5 V
OUT
= 1.5V, V
IN
< 1.5V 600 1200 µA
LT1963-1.8 V
OUT
= 1.8V, V
IN
< 1.8V 600 1200 µA
LT1963-2.5 V
OUT
= 2.5V, V
IN
< 2.5V 600 1200 µA
LT1963-3.3 V
OUT
= 3.3V, V
IN
< 3.3V 600 1200 µA
LT1963 (Note 4) V
OUT
= 1.21V, V
IN
< 1.21V 300 600 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Absolute maximum input to output differential voltage can not be
achieved with all combinations of rated IN pin and OUT pin voltages. With
the IN pin at 20V, the OUT pin may not be pulled below 0V. The total
measured voltage from IN to OUT can not exceed ±20V.
Note 3: The LT1963 regulators are tested and specified under pulse load
conditions such that T
J
≈ T
A
. The LT1963 is 100% tested at
T
A
= 25°C. Performance at –40°C and 125°C is assured by design,
characterization and correlation with statistical process controls.
Note 4: The LT1963 (adjustable version) is tested and specified for these
conditions with the ADJ pin connected to the OUT pin.
Note 5: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 6: To satisfy requirements for minimum input voltage, the LT1963
(adjustable version) is tested and specified for these conditions with an
external resistor divider (two 4.12k resistors) for an output voltage of
2.4V. The external resistor divider will add a 300µA DC load on the output.
Note 7: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: V
IN
– V
DROPOUT
.
Note 8: GND pin current is tested with V
IN
= V
OUT(NOMINAL)
+ 1V and a
current source load. The GND pin current will decrease at higher input
voltages.
Note 9: ADJ pin bias current flows into the ADJ pin.
Note 10: SHDN pin current flows into the SHDN pin.
Note 11: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 12. For the LT1963, LT1963-1.5 and LT1963-1.8 dropout voltage will
be limited by the minimum input voltage specification under some output
voltage/load conditions.
Note 13. For the ST package, the input reverse leakage current increases
due to the additional reverse leakage current for the SHDN pin, which is
tied internally to the IN pin.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3)
ELECTRICAL CHARACTERISTICS
5
LT1963 Series
1963fc
OUTPUT CURRENT (A)
0
DROPOUT VOLTAGE (mV)
500
450
400
350
300
250
200
150
100
50
0
0.4 0.8 1.0
1963 • G01
0.2 0.6 1.2 1.4 1.6
TJ = 125°C
TJ = 25°C
TEMPERATURE (°C)
–50
OUTPUT VOLTAGE (V)
100
1963 G07
050
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
–25 25 75 125
I
L
= 1mA
TEMPERATURE (°C)
–50
ADJ PIN VOLTAGE (V)
100
1963 G08
050
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
–25 25 75 125
I
L
= 1mA
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT1963-3.3 Output Voltage LT1963 ADJ Pin Voltage
TEMPERATURE (°C)
–50
OUTPUT VOLTAGE (V)
100
1963 G06
050
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
–25 25 75 125
I
L
= 1mA
LT1963-2.5 Output Voltage
OUTPUT CURRENT (A)
GUARANTEED DROPOUT VOLTAGE (mV)
600
500
400
300
200
100
000.4 0.8 1.0
1963 • G02
0.2 0.6 1.2 1.4 1.6
T
J
≤ 125°C
T
J
≤ 25°C
TEST POINTS
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (mV)
500
450
400
350
300
250
200
150
100
50
0050 75
1963 G03
–25 25 100 125
IL = 100mA
IL = 1mA
IL = 0.5A
IL = 1.5A
TEMPERATURE (°C)
–50
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
25 75
1963 G04
–25 0 50 100 125
QUIESCENT CURRENT (mA)
LT1963-1.5/-1.8/-2.5/-3.3
LT1963
V
IN
= 6V
R
L
= ∞, I
L
= 0
V
SHDN
= V
IN
TEMPERATURE (°C)
–50
OUTPUT VOLTAGE (V)
100
1963 G05
050
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
–25 25 75 125
IL = 1mA
Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
Quiescent Current LT1963-1.8 Output Voltage
TEMPERATURE (°C)
–50
OUTPUT VOLTAGE (V)
100
1963 G04i
050
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
–25 25 75 125
I
L
= 1mA
LT1963-1.5 Output Voltage
6
LT1963 Series
1963fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INPUT VOLTAGE (V)
0
GND PIN CURRENT (mA)
25
20
15
10
5
04
1963 G13
1231098765
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 1.8V
R
L
= 180, I
L
= 10mA*
R
L
= 18, I
L
= 100mA*
R
L
= 6, I
L
= 300mA*
INPUT VOLTAGE (V)
0
GND PIN CURRENT (mA)
25
20
15
10
5
04
1963 G14
1231098765
R
L
= 250, I
L
= 10mA*
R
L
= 25, I
L
= 100mA*
R
L
= 8.33, I
L
= 300mA*
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 2.5V
INPUT VOLTAGE (V)
0
GND PIN CURRENT (mA)
25
20
15
10
5
04
1963 G15
1231098765
R
L
= 330, I
L
= 100mA*
R
L
= 33, I
L
= 100mA*
R
L
= 11, I
L
= 300mA*
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 3.3V
LT1963-1.8 GND Pin Current LT1963-2.5 GND Pin Current LT1963-3.3 GND Pin Current
INPUT VOLTAGE (V)
0
QUIESCENT CURRENT (mA)
14
12
10
8
6
4
2
0
1963 G09
25678910
134
TJ = 25°C
RL = ∞
VSHDN = VIN
INPUT VOLTAGE (V)
0
QUIESCENT CURRENT (mA)
14
12
10
8
6
4
2
0
1963 G10
21056789
134
TJ = 25°C
RL = ∞
VSHDN = VIN
INPUT VOLTAGE (V)
0
QUIESCENT CURRENT (mA)
14
12
10
8
6
4
2
0
1963 G11
21056789
134
TJ = 25°C
RL = ∞
VSHDN = VIN
INPUT VOLTAGE (V)
0
QUIESCENT CURRENT (mA)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1963 G12
42010 12 14 16 18
268
T
J
= 25°C
R
L
= 4.3k
V
SHDN
= V
IN
LT1963-1.8 Quiescent Current LT1963-2.5 Quiescent Current
LT1963-3.3 Quiescent Current LT1963 Quiescent Current
INPUT VOLTAGE (V)
0
QUIESCENT CURRENT (mA)
14
12
10
8
6
4
2
0
1963 G08i
21098765
134
TJ = 25°C
RL = ∞
VSHDN = VIN
INPUT VOLTAGE (V)
0
GND PIN CURRENT (mA)
25
20
15
10
5
08
LT1963 G12i
246
19
35710
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.5V
RL = 5, IL = 300mA*
RL = 15, IL = 100mA*
RL = 150, IL = 10mA*
LT1963-1.5 Quiescent Current
LT1963-1.5 GND Pin Current
7
LT1963 Series
1963fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
OUTPUT CURRENT (A)
100
90
80
70
60
50
40
30
20
10
0
GND PIN CURRENT (mA)
1963 G21
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V
IN
=
V
OUT (NOMINAL)
+1V
GND Pin Current vs ILOAD
TEMPERATURE (°C)
–50
SHDN PIN THRESHOLD (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0050 75
1963 G23
–25 25 100 125
I
L
= 1mA
I
L
= 1.5A
TEMPERATURE (°C)
–50
SHDN PIN THRESHOLD (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0050 75
1963 G22
–25 25 100 125
IL = 1mA
SHDN Pin Threshold (On-to-Off) SHDN Pin Threshold (Off-to-On)
INPUT VOLTAGE (V)
0
GND PIN CURRENT (mA)
10
8
6
4
2
04
1963 G16
1231098765
R
L
= 121, I
L
= 10mA*
R
L
= 12.1, I
L
= 100mA*
R
L
= 4.33, I
L
= 300mA*
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 1.21V
INPUT VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
0
GND PIN CURRENT (mA)
1963 G17
012345678910
RL = 1.8, IL = 1A*
RL = 1.2, IL = 1.5A*
RL = 3.6, IL = 500mA*
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.8V
INPUT VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
0
GND PIN CURRENT (mA)
1963 G18
012345678910
R
L
= 2.5, I
L
= 1A*
R
L
= 1.67, I
L
= 1.5A*
R
L
= 5, I
L
= 500mA*
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 2.5V
INPUT VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
0
GND PIN CURRENT (mA)
1963 G19
012345678910
R
L
= 3.3, I
L
= 1A*
R
L
= 2.2, I
L
= 1.5A*
R
L
= 6.6, I
L
= 500mA*
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 3.3V
INPUT VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
0
GND PIN CURRENT (mA)
1963 G20
012345678910
R
L
= 1.21, I
L
= 1A*
R
L
= 0.81, I
L
= 1.5A*
R
L
= 2.42, I
L
= 500mA*
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 1.21V
LT1963 GND Pin Current LT1963-1.8 GND Pin Current
LT1963-2.5 GND Pin Current LT1963-3.3 GND Pin Current LT1963 GND Pin Current
INPUT VOLTAGE (V)
0
GND PIN CURRENT (mA)
100
90
80
70
60
50
40
30
20
10
08
1963 G16i
246
19
35710
T
J
= 25°C
V
SHDN
= V
IN
*FOR V
OUT
= 1.5V
R
L
= 1, I
L
= 1.5A*
R
L
= 1.5, I
L
= 1A*
R
L
= 3, I
L
= 500mA*
LT1963-1.5 GND Pin Current
8
LT1963 Series
1963fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
REVERSE OUTPUT CURRENT (mA)
050 75
1963 G30
–25 25 100 125
LT1963-1.5/-1.8/-2.5/-3.3
LT1963
V
IN
= 0V
V
OUT
= 1.21V (LT1963)
V
OUT
= 1.5V (LT1963-1.5)
V
OUT
= 1.8V (LT1963-1.8)
V
OUT
= 2.5V (LT1963-2.5)
V
OUT
= 3.3V (LT1963-3.3)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10 1k 10k 1M
1963 G31
100 100k
C
OUT
= 10µF TANTALUM
C
OUT
= 100µF TANTALUM
+10 × 1µF CERAMIC
I
L
= 0.75A
V
IN
= V
OUT(NOMINAL)
+1V + 50mV
RMS
RIPPLE
TEMPERATURE (°C)
–50
76
74
72
70
68
66
64
62
25 75
1963 G32
–25 0 50 100 125
RIPPLE REJECTION (dB)
I
L
= 0.75A
V
IN
= V
OUT(NOMINAL)
+1V + 0.5V
P-P
RIPPLE AT f = 120Hz
Reverse Output Current Ripple Rejection Ripple Rejection
SHDN Pin Input Current
TEMPERATURE (°C)
–50
7
6
5
4
3
2
1
0
25 75
1963 G25
–25 0 50 100 125
SHDN PIN INPUT CURRENT (µA)
V
SHDN
= 20V
TEMPERATURE (°C)
–50
ADJ PIN BIAS CURRENT (µA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0050 75
1963 G26
–25 25 100 125
INPUT/OUTPUT DIFFERENTIAL (V)
02 6 10 14 18
CURRENT LIMIT (A)
3.0
2.5
2.0
1.5
1.0
0.5
04 8 12 16
1963 G27
20
T
J
= 125°C
T
J
= 25°C
T
J
= –50°C
∆V
OUT
= 100mV
ADJ Pin Bias Current
Current Limit Current Limit
OUTPUT VOLTAGE (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
REVERSE OUTPUT CURRENT (mA)
1963 G29
012345678910
LT1963
LT1963-1.8
LT1963-1.5
LT1963-3.3
LT1963-2.5
CURRENT FLOWS INTO OUTPUT PIN
V
OUT
= V
ADJ
(LT1963)
V
OUT
= V
FB
(LT1963-1.5/-1.8/-2.5/-3.3)
T
J
= 25°C
V
IN
= 0V
TEMPERATURE (°C)
–50
CURRENT LIMIT (A)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
050 75
1963 G28
–25 25 100 125
V
IN
= 7V
V
OUT
= 0V
Reverse Output Current
SHDN PIN VOLTAGE (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SHDN PIN INPUT CURRENT (µA)
1963 G24
0246810 12 14 16 18 20
SHDN Pin Input Current
9
LT1963 Series
1963fc
TEMPERATURE (°C)
–50
MINIMUM INPUT VOLTAGE (V)
3.0
2.5
2.0
1.5
1.0
0.5
025 75
1963 G33
–25 0 50 100 125
I
L
= 1.5A I
L
= 500mA
I
L
= 100mA
TEMPERATURE (°C)
–50
LOAD REGULATION (mV)
10
5
0
–5
–10
–15
–20 25 75
1963 G34
–25 0 50 100 125
LT1963
LT1963-3.3
LT1963-2.5
V
IN
= V
OUT(NOMINAL)
+1V
(LT1963-1.5/-1.8/-2.5/-3.3)
V
IN
= 2.7V (LT1963)
∆I
L
= 1mA TO 1.5A
LT1963-1.5
LT1963-1.8
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
0.1
1.0
1k 100k
1963 G35
100 10k
COUT = 10µF
IL =1.5A
LT1963-3.3 LT1963-2.5
LT1963
LT1963-1.5
LT1963-1.8
LOAD CURRENT (A)
OUTPUT NOISE VOLTAGE (µVRMS)
50
45
40
35
30
25
20
15
10
5
0
0.0001 0.01 0.1 10
1063 G36
0.001 1
COUT = 10µF
LT1963-3.3
LT1963-2.5
LT1963-1.8
LT1963-1.5
LT1963
V
OUT
100µV/DIV
1ms/DIV
C
OUT
= 10µF
I
LOAD
= 1.5A
1963 G37
LT1963 Minimum Input Voltage Load Regulation Output Noise Spectral Density
RMS Output Noise vs Load
Current (10Hz to 100kHz) LT1963-3.3 10Hz to 100kHz Output Noise
TIME (µs)
200
150
100
50
0
–50
–100
0.6
0.4
0.2
0
OUTPUT VOLTAGE
DEVIATION (mV)
1963 G38
0246810 12 14 16 18 20
V
IN
= 4.3V
C
IN
= 3.3µF TANTALUM
C
OUT
= 10µF TANTALUM
LOAD
CURRENT (A)
TIME (µs)
150
100
50
0
–50
–100
–150
1.5
1.0
0.5
0
OUTPUT VOLTAGE
DEVIATION (mV)
LOAD
CURRENT (A)
1963 G39
0 50 100 150 250 300 350 400 450 500200
V
IN
= 4.3V
C
IN
= 33µF TANTALUM
C
OUT
= 100µF TANTALUM
+10 × 1µF CERAMIC
LT1963-3.3 Transient Response LT1963-3.3 Transient Response
TYPICAL PERFOR A CE CHARACTERISTICS
UW
10
LT1963 Series
1963fc
ADJ: Adjust. For the adjustable LT1963, this is the input to
the error amplifier. This pin is internally clamped to ±7V.
It has a bias current of 3µA which flows into the pin. The
ADJ pin voltage is 1.21V referenced to ground and the
output voltage range is 1.21V to 20V.
SHDN: Shutdown. The SHDN pin is used to put the LT1963
regulators into a low power shutdown state. The output
will be off when the SHDN pin is pulled low. The SHDN pin
can be driven either by 5V logic or open-collector logic
with a pull-up resistor. The pull-up resistor is required to
supply the pull-up current of the open-collector gate,
normally several microamperes, and the SHDN pin cur-
rent, typically 3µA. If unused, the SHDN pin must be
connected to V
IN
. The device will be in the low power
shutdown state if the SHDN pin is not connected.
IN: Input. Power is supplied to the device through the IN
pin. A bypass capacitor is required on this pin if the device
is more than six inches away from the main input filter
capacitor. In general, the output impedance of a battery
rises with frequency, so it is advisable to include a bypass
capacitor in battery-powered circuits. A bypass capacitor
in the range of 1µF to 10µF is sufficient. The LT1963 regu-
lators are designed to withstand reverse voltages on the IN
pin with respect to ground and the OUT pin. In the case of
a reverse input, which can happen if a battery is plugged
in backwards, the device will act as if there is a diode in
series with its input. There will be no reverse current flow
into the regulator and no reverse voltage will appear at the
load. The device will protect both itself and the load.
Exposed Pad: GND. The Exposed Pad (FE Package) is
ground and must be soldered to the PCB for rated thermal
performance.Figure 1. Kelvin Sense Connection
IN
SHDN
1963 F01
RP
OUT
VIN
SENSE
GND
LT1963
RP
+
+
LOAD
UU
U
PI FU CTIO S
OUT: Output. The output supplies power to the load. A
minimum output capacitor of 10µF is required to prevent
oscillations. Larger output capacitors will be
required for applications with large transient loads to limit
peak voltage transients. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
SENSE: Sense. For fixed voltage versions of the LT1963
(LT1963-1.5/LT1963-1.8/LT1963-2.5/LT1963-3.3), the
SENSE pin is the input to the error amplifier. Optimum
regulation will be obtained at the point where the SENSE
pin is connected to the OUT pin of the regulator. In critical
applications, small voltage drops are caused by the resis-
tance (R
P
) of PC traces between the regulator and the load.
These may be eliminated by connecting the SENSE pin to
the output at the load as shown in Figure 1 (Kelvin Sense
Connection). Note that the voltage drop across the exter-
nal PC traces will add to the dropout voltage of the regu-
lator. The SENSE pin bias current is 600µA at the nominal
rated output voltage. The SENSE pin can be pulled below
ground (as in a dual supply system where the regulator
load is returned to a negative supply) and still allow the
device to start and operate.
11
LT1963 Series
1963fc
Figure 2. Adjustable Operation
IN
1963 F02
R2
OUT
V
IN
V
OUT
ADJ
GND
LT1963
R1
+
VV
R
RIR
VV
IA
OUT ADJ
ADJ
ADJ
=+
⎛
⎝
⎜⎞
⎠
⎟+
()()
=
=°
121 1 2
12
121
3
.
.
µ AT 25 C
OUTPUT RANGE = 1.21V TO 20V
APPLICATIO S I FOR ATIO
WUUU
The LT1963 series are 1.5A low dropout regulators opti-
mized for fast transient response. The devices are capable
of supplying 1.5A at a dropout voltage of 350mV. The low
operating quiescent current (1mA) drops to less than 1µA
in shutdown. In addition to the low quiescent current, the
LT1963 regulators incorporate several protection features
which make them ideal for use in battery-powered sys-
tems. The devices are protected against both reverse input
and reverse output voltages. In battery backup applica-
tions where the output can be held up by a backup battery
when the input is pulled to ground, the LT1963-X acts like
it has a diode in series with its output and prevents reverse
current flow. Additionally, in dual supply applications
where the regulator load is returned to a negative supply,
the output can be pulled below ground by as much as 20V
and still allow the device to start and operate.
Adjustable Operation
The adjustable version of the LT1963 has an output
voltage range of 1.21V to 20V. The output voltage is set by
the ratio of two external resistors as shown in Figure 2. The
device servos the output to maintain the voltage at the ADJ
pin at 1.21V referenced to ground. The current in R1 is
then equal to 1.21V/R1 and the current in R2 is the current
in R1 plus the ADJ pin bias current. The ADJ pin bias
current, 3µA at 25°C, flows through R2 into the ADJ pin.
The output voltage can be calculated using the formula in
Figure 2. The value of R1 should be less than 4.17k to
minimize errors in the output voltage caused by the ADJ
pin bias current. Note that in shutdown the output is turned
off and the divider current will be zero.
The adjustable device is tested and specified with the ADJ
pin tied to the OUT pin for an output voltage of 1.21V.
Specifications for output voltages greater than 1.21V will
be proportional to the ratio of the desired output voltage to
1.21V: V
OUT
/1.21V. For example, load regulation for an
output current change of 1mA to 1.5A is –3mV typical at
V
OUT
= 1.21V. At V
OUT
= 5V, load regulation is:
(5V/1.21V)(–3mV) = –12.4mV
Output Capacitance and Transient Response
The LT1963 regulators are designed to be stable with a wide
range of output capacitors. The ESR of the output capacitor
affects stability, most notably with small capacitors. A mini-
mum output capacitor of 10µF with an ESR in the range of
50mΩ to 3Ω is recommended to prevent oscillations. Larger
values of output capacitance can decrease the peak devia-
tions and provide improved transient response for larger
load current changes. Bypass capacitors, used to decouple
individual components powered by the LT1963, will in-
crease the effective output capacitor value.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are specified with EIA temperature charac-
teristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V
dielectrics are good for providing high capacitances in a
small package, but they tend to have strong voltage and
temperature coefficients as shown in Figures 2 and 3.
When used with a 5V regulator, a 16V 10µF Y5V capacitor
can exhibit an effective value as low as 1µF to 2µF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is
available in higher values. Care still must be exercised
when using X5R and X7R capacitors; the X5R and X7R
codes only specify operating temperature range and maxi-
mum capacitance change over temperature. Capacitance
change due to DC bias with X5R and X7R capacitors is
better than Y5V and Z5U capacitors, but can still be
significant enough to drop capacitor values below appro-
priate levels. Capacitor DC bias characteristics tend to
12
LT1963 Series
1963fc
operating region for all values of input-to-output voltage.
The protection is designed to provide some output current
at all values of input-to-output voltage up to the device
breakdown.
When power is first turned on, as the input voltage rises,
the output follows the input, allowing the regulator to start
up into very heavy loads. During the start-up, as the input
voltage is rising, the input-to-output voltage differential is
small, allowing the regulator to supply large output
currents. With a high input voltage, a problem can occur
wherein removal of an output short will not allow the
output voltage to recover. Other regulators, such as the
LT1085, also exhibit this phenomenon, so it is not unique
to the LT1963-X.
The problem occurs with a heavy output load when the
input voltage is high and the output voltage is low. Com-
mon situations are immediately after the removal of a
short-circuit or when the shutdown pin is pulled high after
the input voltage has already been turned on. The load line
for such a load may intersect the output current curve at
two points. If this happens, there are two stable output
operating points for the regulator. With this double inter-
section, the input power supply may need to be cycled down
to zero and brought up again to make the output recover.
Output Voltage Noise
The LT1963 regulators have been designed to provide low
output voltage noise over the 10Hz to 100kHz bandwidth
while operating at full load. Output voltage noise is typi-
cally 40nV/√Hz over this frequency bandwidth for the
LT1963 (adjustable version). For higher output voltages
(generated by using a resistor divider), the output voltage
noise will be gained up accordingly. This results in RMS
noise over the 10Hz to 100kHz bandwidth of 14µV
RMS
for
the LT1963 increasing to 38µV
RMS
for the LT1963-3.3.
Higher values of output voltage noise may be measured
when care is not exercised with regards to circuit layout
and testing. Crosstalk from nearby traces can induce
unwanted noise onto the output of the LT1963-X. Power
supply ripple rejection must also be considered; the LT1963
regulators do not have unlimited power supply rejection
and will pass a small portion of the input noise through to
the output.
Figure 4. Ceramic Capacitor Temperature Characteristics
APPLICATIO S I FOR ATIO
WUUU
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
1963 F04
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
improve as component case size increases, but expected
capacitance at operating voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor the stress can be
induced by vibrations in the system or thermal transients.
Overload Recovery
Like many IC power regulators, the LT1963-X has safe
operating area protection. The safe area protection de-
creases the current limit as input-to-output voltage in-
creases and keeps the power transistor inside a safe
Figure 3. Ceramic Capacitor DC Bias Characteristics
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
1963 F03
20
0
–20
–40
–60
–80
–100 04810
26 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
13
LT1963 Series
1963fc
Table 2. SO-8 Package, 8-Lead SO
COPPER AREA THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
55°C/W
1000mm
2
2500mm
2
2500mm
2
55°C/W
225mm
2
2500mm
2
2500mm
2
63°C/W
100mm
2
2500mm
2
2500mm
2
69°C/W
Table 3. SOT-223 Package, 3-Lead SOT-223
COPPER AREA THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
42°C/W
1000mm
2
2500mm
2
2500mm
2
42°C/W
225mm
2
2500mm
2
2500mm
2
50°C/W
100mm
2
2500mm
2
2500mm
2
56°C/W
1000mm
2
1000mm
2
1000mm
2
49°C/W
1000mm
2
0mm
2
1000mm
2
52°C/W
Table 4. FE Package, 16-Lead TSSOP
COPPER AREA THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
38°C/W
1000mm
2
2500mm
2
2500mm
2
43°C/W
225mm
2
2500mm
2
2500mm
2
48°C/W
100mm
2
2500mm
2
2500mm
2
60°C/W
T Package, 5-Lead TO-220
Thermal Resistance (Junction-to-Case) = 4°C/W
Calculating Junction Temperature
Example: Given an output voltage of 3.3V, an input voltage
range of 4V to 6V, an output current range of 0mA to
500mA and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be?
The power dissipated by the device will be equal to:
I
OUT(MAX)
(V
IN(MAX)
– V
OUT
) + I
GND
(V
IN(MAX)
)
where,
I
OUT(MAX)
= 500mA
V
IN(MAX)
= 6V
I
GND
at (I
OUT
= 500mA, V
IN
= 6V) = 10mA
So,
P = 500mA(6V – 3.3V) + 10mA(6V) = 1.41W
APPLICATIO S I FOR ATIO
WUUU
Thermal Considerations
The power handling capability of the device is limited by the
maximum rated junction temperature (125°C). The power
dissipated by the device is made up of two components:
1. Output current multiplied by the input/output voltage
differential: (I
OUT
)(V
IN
– V
OUT
), and
2. GND pin current multiplied by the input voltage:
(I
GND
)(V
IN
).
The GND pin current can be found using the GND Pin
Current curves in the Typical Performance Characteris-
tics. Power dissipation will be equal to the sum of the two
components listed above.
The LT1963 series regulators have internal thermal lim-
iting designed to protect the device during overload
conditions. For continuous normal conditions, the maxi-
mum junction temperature rating of 125°C must not be
exceeded. It is important to give careful consideration to
all sources of thermal resistance from junction to ambi-
ent. Additional heat sources mounted nearby must also
be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 1/16" FR-4 board with one ounce
copper.
Table 1. Q Package, 5-Lead DD
COPPER AREA THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
23°C/W
1000mm
2
2500mm
2
2500mm
2
25°C/W
125mm
2
2500mm
2
2500mm
2
33°C/W
* Device is mounted on topside
* Device is mounted on topside
* Device is mounted on topside
* Device is mounted on topside
14
LT1963 Series
1963fc
device. If the input is left open circuit or grounded, the ADJ
pin will act like an open circuit when pulled below ground
and like a large resistor (typically 5k) in series with a diode
when pulled above ground.
In situations where the ADJ pin is connected to a resistor
divider that would pull the ADJ pin above its 7V clamp
voltage if the output is pulled high, the ADJ pin input
current must be limited to less than 5mA. For example, a
resistor divider is used to provide a regulated 1.5V output
from the 1.21V reference when the output is forced to 20V.
The top resistor of the resistor divider must be chosen to
limit the current into the ADJ pin to less than 5mA when the
ADJ pin is at 7V. The 13V difference between OUT and ADJ
pins divided by the 5mA maximum current into the ADJ pin
yields a minimum top resistor value of 2.6k.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage, or is left
open circuit. Current flow back into the output will follow
the curve shown in Figure 5.
When the IN pin of the LT1963 is forced below the OUT pin
or the OUT pin is pulled above the IN pin, input current will
typically drop to less than 2µA. This can happen if the
input of the device is connected to a discharged (low
voltage) battery and the output is held up by either a
backup battery or a second regulator circuit. The state of
the SHDN pin will have no effect on the reverse output
current when the output is pulled above the input.
Using a DD package, the thermal resistance will be in the
range of 23°C/W to 33°C/W depending on the copper
area. So the junction temperature rise above ambient will
be approximately equal to:
1.41W(28°C/W) = 39.5°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
JMAX
= 50°C + 39.5°C = 89.5°C
Protection Features
The LT1963 regulators incorporate several protection
features which make them ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
limiting and thermal limiting, the devices are protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal opera-
tion, the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages of
20V. Current flow into the device will be limited to less than
1mA (typically less than 100µA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
that can be plugged in backward.
The output of the LT1963 can be pulled below ground
without damaging the device. If the input is left open circuit
or grounded, the output can be pulled below ground by
20V. For fixed voltage versions, the output will act like a
large resistor, typically 5k or higher, limiting current flow
to typically less than 600µA. For adjustable versions, the
output will act like an open circuit; no current will flow out
of the pin. If the input is powered by a voltage source, the
output will source the short-circuit current of the device
and will protect itself by thermal limiting. In this case,
grounding the SHDN pin will turn off the device and stop
the output from sourcing the short-circuit current.
The ADJ pin of the adjustable device can be pulled above
or below ground by as much as 7V without damaging the
APPLICATIO S I FOR ATIO
WUUU
Figure 5. Reverse Output Current
OUTPUT VOLTAGE (V)
0
REVERSE OUTPUT CURRENT (mA)
3.0
4.0
5.0
8
1963 F05
2.0
1.0
2.5
3.5
4.5
1.5
0.5
02
13469
7
510
LT1963
V
OUT
= V
ADJ
T
J
= 25°C
V
IN
= 0V
CURRENT FLOWS
INTO OUTPUT PIN
LT1963-3.3
V
OUT
= V
FB
LT1963-1.5
V
OUT
= V
FB
LT1963-1.8
V
OUT
= V
FB
LT1963-2.5
V
OUT
= V
FB
15
LT1963 Series
1963fc
10VAC AT
115V
IN
10VAC AT
115V
IN
–
+
–
+
–
+
750Ω
+V
+V
+V
+V
+V
1/2
LT1018
1/2
LT1018
LT1006
10k
10k 10k
200k
0.1µF
22µF
1µF
0.033µF
1N4148
1N4148
LT1004
1.2V
750Ω
A1
C1A
C1B
34k*
12.1k*
3.3V
OUT
1.5A
L1
500µH
10000µF
TO ALL “+V”
POINTS
22µF
1N4002
1N4002 1N4002
1N4148
“SYNC”
1k
L2
90-140
VAC
1963 TA03
LT1963-3.3
IN
SHDN
OUT
FB
GND
2.4k
+
+
+
L1 = COILTRONICS CTX500-2-52
L2 = STANCOR P-8559
* = 1% FILM RESISTOR
= NTE5437
TYPICAL APPLICATIO S
U
SCR Pre-Regulator Provides Efficiency Over Line Variations
LT1963-3.3
IN
SHDN
OUT
FB
GND
LT1963
IN
SHDN
OUT
FB
GND
+
+
R1
0.01Ω
R2
0.01Ω
R3
2.2k
R4
2.2k
R5
1k
R6
6.65k
R7
4.12k
C1
100µF
C3
0.01µF
C2
22µF
V
IN
> 3.7V
SHDN
3.3V
3A
8
4
3
2
1
–
+
1/2
LT1366
1963 TA05
Paralleling of Regulators for Higher Output Current
16
LT1963 Series
1963fc
U
PACKAGE DESCRIPTIO
Q Package
5-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1461)
Q(DD5) 0502
.028 – .038
(0.711 – 0.965)
TYP
.143 +.012
–.020
()
3.632 +0.305
–0.508
.067
(1.702)
BSC
.013 – .023
(0.330 – 0.584)
.095 – .115
(2.413 – 2.921)
.004 +.008
–.004
()
0.102 +0.203
–0.102
.050 ± .012
(1.270 ± 0.305)
.059
(1.499)
TYP
.045 – .055
(1.143 – 1.397)
.165 – .180
(4.191 – 4.572)
.330 – .370
(8.382 – 9.398)
.060
(1.524)
TYP
.390 – .415
(9.906 – 10.541)
15° TYP
.420
.350
.565
.090
.042
.067
RECOMMENDED SOLDER PAD LAYOUT
.325
.205
.080
.565
.090
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
.042
.067
.420
.276
.320
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
.300
(7.620)
.075
(1.905)
.183
(4.648)
.060
(1.524)
.060
(1.524)
.256
(6.502)
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
17
LT1963 Series
1963fc
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
U
PACKAGE DESCRIPTIO
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
18
LT1963 Series
1963fc
ST Package
3-Lead Plastic SOT-223
(Reference LTC DWG # 05-08-1630)
.114 – .124
(2.90 – 3.15)
.248 – .264
(6.30 – 6.71)
.130 – .146
(3.30 – 3.71)
.264 – .287
(6.70 – 7.30)
.0905
(2.30)
BSC
.033 – .041
(0.84 – 1.04)
.181
(4.60)
BSC
.024 – .033
(0.60 – 0.84)
.071
(1.80)
MAX
10°
MAX
.012
(0.31)
MIN
.0008 – .0040
(0.0203 – 0.1016)
10° – 16°
.010 – .014
(0.25 – 0.36)
10° – 16°
RECOMMENDED SOLDER PAD LAYOUT
ST3 (SOT-233) 0502
.129 MAX
.059 MAX
.059 MAX
.181 MAX
.039 MAX
.248 BSC
.090
BSC
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
T5 (TO-220) 0399
0.028 – 0.038
(0.711 – 0.965)
0.067
(1.70) 0.135 – 0.165
(3.429 – 4.191)
0.700 – 0.728
(17.78 – 18.491)
0.045 – 0.055
(1.143 – 1.397)
0.095 – 0.115
(2.413 – 2.921)
0.013 – 0.023
(0.330 – 0.584)
0.620
(15.75)
TYP
0.155 – 0.195*
(3.937 – 4.953)
0.152 – 0.202
(3.861 – 5.131)
0.260 – 0.320
(6.60 – 8.13)
0.165 – 0.180
(4.191 – 4.572)
0.147 – 0.155
(3.734 – 3.937)
DIA
0.390 – 0.415
(9.906 – 10.541)
0.330 – 0.370
(8.382 – 9.398)
0.460 – 0.500
(11.684 – 12.700)
0.570 – 0.620
(14.478 – 15.748)
0.230 – 0.270
(5.842 – 6.858)
BSC
SEATING PLANE
* MEASURED AT THE
SEATING PLANE
U
PACKAGE DESCRIPTIO
19
LT1963 Series
1963fc
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
FE16 (BB) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.94
(.116)
0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.94
(.116)
3.58
(.141)
3.58
(.141)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
20
LT1963 Series
1963fc
LT 1105 • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2005
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO S
U
+
LT1004-1.2
VIN > 2.7V C1
10µF
R3
2k
R1
1k
R2
80.6k
R4
2.2k
R5
0.01Ω
R6
2.2k
LT1963-1.8
IN
SHDN
OUT
FB
GND
–
+
1/2
LT1366
R8
100k
LOAD
R7
470Ω
2
1
8
3
4
C3
1µF
C2
3.3µF
1963 TA04
NOTE: ADJUST R1 FOR
0A TO 1.5A CONSTANT CURRENT
Adjustable Current Source
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1129 700mA, Micropower, LDO V
IN
: 4.2V to 30V, V
OUT(MIN)
= 3.75V, V
DO
= 0.40V, I
Q
= 50µA, I
SD
= 16µA,
DD, SOT-223, S8, TO220, TSSOP20 Packages
LT1175 500mA, Micropower Negative LDO V
IN
: –20V to –4.3V, V
OUT(MIN)
= –3.8V, V
DO
= 0.50V, I
Q
= 45µA, I
SD
= 10µA,
DD, SOT-223, S8 Packages
LT1185 3A, Negative LDO V
IN
: –35V to –4.2V, V
OUT(MIN)
= –2.40V, V
DO
= 0.80V, I
Q
= 2.5mA, I
SD
<1µA,
TO220-5 Package
LT1761 100mA, Low Noise Micropower, LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 20µA, I
SD
<1µA,
ThinSOT Package
LT1762 150mA, Low Noise Micropower, LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 25µA, I
SD
<1µA, MS8 Package
LT1763 500mA, Low Noise Micropower, LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 30µA, I
SD
<1µA, S8 Package
LT1764/ 3A, Low Noise, Fast Transient Response, V
IN
: 2.7V to 20V, V
OUT(MIN)
= 1.21V, V
DO
= 0.34V, I
Q
= 1mA, I
SD
<1µA,
LT1764A LDO DD, TO220 Packages
LTC1844 150mA, Very Low Drop-Out LDO V
IN
: 6.5V to 1.6V, V
OUT(MIN)
= 1.25V, V
DO
= 0.08V, I
Q
= 40µA, I
SD
<1µA,
ThinSOT Package
LT1962 300mA, Low Noise Micropower, LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.27V, I
Q
= 30µA, I
SD
<1µA, MS8 Package
LT1963/ 1.5A, Low Noise, Fast Transient Response, V
IN
: 2.1V to 20V, V
OUT(MIN)
= 1.21V, V
DO
= 0.34V, I
Q
= 1mA, I
SD
<1µA,
LT1963A LDO DD, TO220, SOT Packages
LT1964 200mA, Low Noise Micropower, Negative V
IN
: –0.9V to –20V, V
OUT(MIN)
= –1.21V, V
DO
= 0.34V, I
Q
= 30µA, I
SD
= 3µA,
LDO ThinSOT Package
LT3020 100mA, Low Voltage V
LDO
V
IN
: 0.9V to 10V, V
OUT(MIN)
= 0.20, V
DO
= 0.15V, I
Q
= 120µA, I
SD
<3µA,
DFN, MS8 Packages
LT3023 Dual, 2x 100mA, Low Noise Micropower, V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 40µA, I
SD
<1µA,
LDO DFN, MS10 Packages
LT3024 Dual, 100mA/500mA, Low Noise Micropower, V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 60µA, I
SD
<1µA,
LDO DFN, TSSOP Package
LT3150 Fast Transient Response, Low Input Voltage V
IN
: –1.4V to 10V, V
OUT(MIN)
= 1.23V, V
DO
= 0.13V, I
Q
= 12mA, I
SD
= 25µA,
GN16 Package
