LF156QML
LF156QML JFET Input Operational Amplifiers
Literature Number: SNOSAN9
LF156QML
JFET Input Operational Amplifiers
General Description
This is the first monolithic JFET input operational amplifier to
incorporate well matched, high voltage JFETs on the same
chip with standard bipolar transistors (BI-FET™Technology).
This amplifier features low input bias and offset currents/low
offset voltage and offset voltage drift, coupled with offset
adjust which does not degrade drift or common-mode rejec-
tion. The device is also designed for high slew rate, wide
bandwidth, extremely fast settling time, low voltage and
current noise and a low 1/f noise corner.
Features
Advantages
nReplace expensive hybrid and module FET op amps
nRugged JFETs allow blow-out free handling compared
with MOSFET input devices
nExcellent for low noise applications using either high or
low source impedance — very low 1/f corner
nOffset adjust does not degrade drift or common-mode
rejection as in most monolithic amplifiers
nNew output stage allows use of large capacitive loads
(5,000 pF) without stability problems
nInternal compensation and large differential input voltage
capability
Applications
nPrecision high speed integrators
nFast D/A and A/D converters
nHigh impedance buffers
nWideband, low noise, low drift amplifiers
nLogarithmic amplifiers
nPhotocell amplifiers
nSample and Hold circuits
Common Features
nLow input bias current: 30pA
nLow Input Offset Current: 3pA
nHigh input impedance: 10
12
Ω
nLow input noise current:
nHigh common-mode rejection ratio: 100 dB
nLarge dc voltage gain: 106 dB
Uncommon Features
nExtremely fast settling
time to 0.01% 1.5µs
nFast slew rate 12V/µs
nWide gain bandwidth 5MHz
nLow input noise voltage 12
Ordering Information
NS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DISCRIPTION
LF156H/883 H08C 8LD Metal Can
Connection Diagrams
Metal Can Package (H)
20145914
Top View
See NS Package Number H08C
BI-FET™, BI-FET II™are trademarks of National Semiconductor Corporation.
March 2006
LF156QML JFET Input Operational Amplifiers
© 2006 National Semiconductor Corporation DS201459 www.national.com
Simplified Schematic
20145901
*3pF in LF357 series.
Detailed Schematic
20145913
*C = 3pF in LF357 series.
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Absolute Maximum Ratings (Note 1)
Supply Voltage ±22V
Differential Input Voltage ±40V
Input Voltage Range (Note 4) ±20V
Output Short Circuit Duration Continuous
T
Jmax
150˚C
Power Dissipation at T
A
= 25˚C (Notes 2, 3)
Still Air 560 mW
500 LF/Min Air Flow 1200 mW
Thermal Resistance
θ
JA
Still Air 162˚C/W
400 LF/Min Air Flow 89˚C/W
θ
JC
32˚C/W
Storage Temperature Range −65˚C ≤T
A
≤+150˚C
Lead Temperature (Soldering 10 sec.) 300˚C
ESD tolerance (Note 5) 1200V
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup Description Temp ( C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
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LF156 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
DC: V
CC
=±5V, V
CM
= 0V, R
S
=50Ω
Symbol Parameter Conditions Notes Min Max Unit
Sub-
groups
V
IO
Input Offset Voltage
-5.0 5.0 mV 1
-7.0 7.0 mV 2, 3
V
CC
=±20V -5.0 5.0 mV 1
-7.0 7.0 mV 2, 3
I
IO
Input Offset Current V
CC
=±20V -0.02 0.02 nA 1
-20 20 nA 2, 3
+I
IB
Input Bias Current V
CC
=±20V -0.1 0.1 nA 1
-10 50 nA 2, 3
V
CC
=±20V, V
CM
= -16V -0.1 0.1 nA 1
-10 50 nA 2, 3
V
CC
=±20V, V
CM
= 16V -0.1 3.5 nA 1
-10 60 nA 2, 3
-I
IB
Input Bias Current V
CC
=±20V -0.1 0.1 nA 1
-10 50 nA 2, 3
V
CC
=±20V, V
CM
= -16V -0.1 0.1 nA 1
-10 50 nA 2, 3
V
CC
=±20V, V
CM
= 16V -0.1 3.5 nA 1
-10 60 nA 2, 3
+PSRR Power Supply Rejection Ratio +V
CC
= 20V to 10V,
-V
CC
= -20V
85 dB 1, 2, 3
-PSRR Power Supply Rejection Ratio -V
CC
= -20V to -10V,
+V
CC
= 20V
85 dB 1, 2, 3
CMRR Common Mode Rejection Ratio V
CM
=±11V 85 dB 1, 2, 3
I
CC
Power Supply Current 7.0 mA 1
14 mA 2, 3
+I
OS
Short Circuit Current V
O
= 0V -45 -15 mA 1
-35 -10 mA 2
-65 -15 mA 3
-I
OS
Short Circuit Current V
O
=0V 15 45 mA 1
10 35 mA 2
15 65 mA 3
V
CM
Common Mode Voltage Range (Note 6) -11 11 V 1, 2, 3
+V
OP
Output Voltage Swing R
L
= 10KΩ12 V 4,5,6
R
L
=2KΩ(Note 6) 10 V 4, 5, 6
-V
OP
Output Voltage Swing R
L
= 10KΩ-12 V 4,5,6
R
L
=2KΩ(Note 6) -10 V 4, 5, 6
A
VS
Large Signal Voltage Gain R
L
=2KΩ,V
O
= 0 to 10V 50 V/mV 4
25 V/mV 5, 6
R
L
=2KΩ,V
O
= 0 to -10V 50 V/mV 4
25 V/mV 5, 6
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LF156 Electrical Characteristics (Continued)
AC Parameters
The following conditions apply, unless otherwise specified.
AC: V
CC
=±5V, V
CM
= 0V, R
S
=50Ω
Symbol Parameter Conditions Notes Min Max Unit
Sub-
groups
+SR Slew Rate
A
V
=1,R
LOAD
=2KΩ,
C
L
= 100pfd,
V
I
= -5V to +5V
7.5 V/µS 7
-SR Slew Rate A
V
=1,R
L
=2KΩ,
C
L
= 100pF,
V
I
= +5V to -5V
7.5 V/µS 7
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condition for which the device is
functional, but do not guarantee specific performance limits . For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax(maximum junction temperature), θJA(package junction
to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature is PD=(TJmax−TA)/θJA or the number
given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Maximum power dissipation (PDmax)is defined by the package characteristics. Operating the part near the PDmax may cause the part to operate outside
guaranteed limits.
Note 4: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 5: Human body model, 100pF discharged through 1.5KΩ.
Note 6: Parameter guaranteed by CMRR test.
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Typical DC Performance Characteristics
Input Bias Current Input Bias Current
20145937 20145938
Input Bias Current Voltage Swing
20145939 20145940
Supply Current Supply Current
20145941 20145942
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Typical DC Performance Characteristics (Continued)
Negative Current Limit Positive Current Limit
20145943 20145944
Positive Common-Mode
Input Voltage Limit
Negative Common-Mode
Input Voltage Limit
20145945
20145946
Open Loop Voltage Gain Output Voltage Swing
20145947 20145948
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Typical AC Performance Characteristics
Gain Bandwidth Normalized Slew Rate
20145950 20145951
Output Impedance Output Impedance
20145952 20145953
LF156 Small Signal Pulse
Response, A
V
=+1
LF156 Large Signal Puls
Response, A
V
=+1
20145906 20145909
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Typical AC Performance Characteristics (Continued)
Inverter Settling Time Open Loop Frequency Response
20145956 20145957
Bode Plot Common-Mode Rejection Ratio
20145959 20145961
Power Supply Rejection Ratio
20145963
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Typical AC Performance Characteristics (Continued)
Undistorted Output Voltage Swing Equivalent Input Noise Voltage
20145964
20145965
Equivalent Input Noise
Voltage (Expanded Scale)
20145966
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Application Hints
These are op amps with JFET input devices. These JFETs
have large reverse breakdown voltages from gate to source
and drain eliminating the need for clamps across the inputs.
Therefore large differential input voltages can easily be ac-
commodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
These amplifiers will operate with the common-mode input
voltage equal to the positive supply. In fact, the common-
mode voltage can exceed the positive supply by approxi-
mately 100 mV independent of supply voltage and over the
full operating temperature range. The positive supply can
therefore be used as a reference on an input as, for ex-
ample, in a supply current monitor and/or limiter.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
All of the bias currents in these amplifiers are set by FET
current sources. The drain currents for the amplifiers are
therefore essentially independent of supply voltage.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pickup” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3dB
frequency of the closed loop gain and consequently there is
negligible effect on stability margin. However, if the feedback
pole is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the output
to the input of the op amp. The value of the added capacitor
should be such that the RC time constant of this capacitor
and the resistance it parallels is greater than or equal to the
original feedback pole time constant.
Typical Circuit Connections
V
OS
Adjustment
20145967
•V
OS
is adjusted with a 25k potentiometer
•The potentiometer wiper is connected to V
+
•For potentiometers with temperature coefficient of 100
ppm/˚C or less the additional drift with adjust is ≈0.5µV/
˚C/mV of adjustment
•Typical overall drift: 5µV/˚C ±(0.5µV/˚C/mV of adj.)
Driving Capacitive Loads
20145968
* LF156R=5k
Due to a unique output stage design, these amplifiers
have the ability to drive large capacitive loads and still
maintain stability. C
L(MAX)
.0.01µF.
Overshoot ≤20%
Settling time (t
s
).5µs
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Typical Applications
Settling Time Test Circuit
20145916
•Settling time is tested with the LF156 connected as unity gain inverter.
•FET used to isolate the probe capacitance
•Output = 10V step
Large Signal Inverter Output, V
OUT
(from Settling Time Circuit)
LF356
20145918
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Typical Applications (Continued)
Low Drift Adjustable Voltage Reference
20145920
•∆V
OUT
/∆T=±0.002%/˚C
•All resistors and potentiometers should be wire-wound
•P1: drift adjust
•P2: V
OUT
adjust
Fast Logarithmic Converter
20145921
•Dynamic range: 100µA ≤I
i
≤1mA (5 decades), |V
O
| = 1V/decade
•Transient response: 3µs for ∆I
i
= 1 decade
•C1, C2, R2, R3: added dynamic compensation
•V
OS
adjust the LF156 to minimize quiescent error
•R
T
: Tel Labs type Q81 + 0.3%/˚C
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Typical Applications (Continued)
Precision Current Monitor
20145931
•V
O
= 5 R1/R2 (V/mA of I
S
)
•R1, R2, R3: 0.1% resistors
8-Bit D/A Converter with Symmetrical Offset Binary Operation
20145932
•R1, R2 should be matched within ±0.05%
•Full-scale response time: 3µs
E
O
B1 B2 B3 B4 B5 B6 B7 B8 Comments
+9.920 11111111 Positive Full-Scale
+0.040 10000000 (+)Zero-Scale
−0.040 01111111 (−)Zero-Scale
−9.920 00000000Negative Full-Scale
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Typical Applications (Continued)
Wide BW Low Noise, Low Drift Amplifier
20145970
•Parasitic input capacitance C1 .3pF interacts with feedback elements and creates undesirable high frequency pole. To
compensate add C2 such that: R2 C2 .R1 C1.
Boosting the LF156 with a Current Amplifier
20145973
•I
OUT(MAX)
.150mA (will drive R
L
≥100Ω)
•
•No additional phase shift added by the current amplifier
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Typical Applications (Continued)
3 Decades VCO
20145924
R1, R4 matched. Linearity 0.1% over 2 decades.
Isolating Large Capacitive Loads
20145922
•Overshoot 6%
•t
s
10µs
•When driving large C
L
, the V
OUT
slew rate determined by C
L
and I
OUT(MAX)
:
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Typical Applications (Continued)
Low Drift Peak Detector
20145923
•By adding D1 and R
f
,V
D1
=0 during hold mode. Leakage of D2 provided by feedback path through R
f
.
•Leakage of circuit is essentially I
b
plus capacitor leakage of Cp.
•Diode D3 clamps V
OUT
(A1) to V
IN
−V
D3
to improve speed and to limit reverse bias of D2.
•Maximum input frequency should be <<
1
⁄
2
πR
f
C
D2
where C
D2
is the shunt capacitance of D2.
High Impedance, Low Drift Instrumentation Amplifier
20145926
•System V
OS
adjusted via A2 V
OS
adjust
•Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift
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Typical Applications (Continued)
Fast Sample and Hold
20145933
•Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)
•Acquisition time T
A
, estimated by:
•LF156 develops full S
r
output capability for V
IN
≥1V
•Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop
•Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2
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Typical Applications (Continued)
High Accuracy Sample and Hold
20145927
•By closing the loop through A2, the V
OUT
accuracy will be determined uniquely by A1.
No V
OS
adjust required for A2.
•T
A
can be estimated by same considerations as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
•Overall system slower than fast sample and hold
•R1, C
C
: additional compensation
•Use LF156 for
jFast settling time
jLow V
OS
High Q Notch Filter
20145934
•2R1=R=10MΩ
2C = C1 = 300pF
•Capacitors should be matched to obtain high Q
•f
NOTCH
= 120 Hz, notch = −55 dB, Q >100
•Use LF155 for
jLow I
B
jLow supply current
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Revision History
Date
Released Revision Section Originator Changes
03/10/06 A
New Released, Corporate format.
Electrical Section Delete Drift Value
table.
R. Malone
New Release, Corporate format 1 MDS
data sheet converted into a Corp. data
sheet format. Following MDS data sheet
will be Archived MNLF156-X, Rev. 2A0.
Delete Drift Value table from Electrical
Section. Reson: Referenced product is
883 only.
LF156QML
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Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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2. A critical component is any component of a life support
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LF156QML JFET Input Operational Amplifiers
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