ee FAIRCHILD ee SEMICONDUCTOR m NDS355AN N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description SuperSOT-3 N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features January 1997 = 1.7A, 30V, Rogow = 0.125 Q @ Veg = 4.5 V Rogen = 0.085 Q @ Veg = 10 V. = Industry standard outline SOT-23 surface mount package using proprietary SuperSOT-3 design for superior thermal and electrical capabilities. = High density cell design for extremely low Rogioy)- = Exceptional on-resistance and maximum DC current capability. = Compact industry standard SOT-23 surface mount package. D at G 8 SuperSOT"-3 Absolute Maximum Ratings 1, =25c unless otherwise noted Symbol | Parameter NDS355AN Units Voss Drain-Source Voltage 30 Vv Vass Gate-Source Voltage - Continuous +20 Vv lp Maximum Drain Current - Continuous (Note 1a) 1.7 A - Pulsed 10 Py Maximum Power Dissipation (Note 1a) 0.5 Ww (Note 1b) 0.46 Ty Teste Operating and Storage Temperature Range -55 to 150 C THERMAL CHARACTERISTICS Rosa Thermal Resistance, Junction-to-Ambient (Note 1a) 250 C/W Rese Thermal Resistance, Junction-to-Case (Note 1) 75 C/W 1997 Fairchild Semiconductor Corporation NDSS55AN Rev.CElectrical Characteristics (T, = 25C unless otherwise noted) Symbol | Parameter Conditions | Min | Typ | Max | Units OFF CHARACTERISTICS BV ps5 Drain-Source Breakdown Voltage Veg = 0 V, p= 250 pA 30 Vv loss Zero Gate Voltage Drain Current Vos = 24 V, Veg= OV 1 HA T, =125C 10 pA lassr Gate - Body Leakage, Forward Veg = 20 Vg = OV 100 nA lassr Gate - Body Leakage, Reverse Veg = 20 V, V5, =0V -100 nA ON CHARACTERISTICS (note 2) Vestn) Gate Threshold Voltage Vog = Ves: |p = 250 PA 1 1.6 2 Vv | t,=125c | 05 | 12 | 15 Rosony Static Drain-Source On-Resistance Veg = 4.5V, 1, =1.7A 0.105 | 0.125 Q | T, =125C 0.16 | 0.23 Veg = 10 V,1,=1.9A 0.065 | 0.085 lcon On-State Drain Current Veg = 4.5 V, Vog = 5 V 6 A Ors Forward Transconductance Vog HOV, IDE 1.7 A 3.5 Ss DYNAMIC CHARACTERISTICS Css Input Capacitance Vpg= 15 V, Veg = OV, 195 pF Coss Output Capacitance f= 1.0 MHz 135 pF Cres Reverse Transfer Capacitance 48 pF SWITCHING CHARACTERISTICS (note 2) baton) Turn - On Delay Time Vpp = 10V,1,=1A, 10 20 ns t Turn - On Rise Time Ves = 10V, Ree= 6 @ 13 25 ns taco Turn - Off Delay Time 13 25 ns t Turn - Off Fall Time 4 10 ns baton) Turn - On Delay Time Vpp = OV, ID=1A, 10 20 ns t Turn - On Rise Time Ves =4.5V, Ram = 6 @ 32 60 ns taco Turn - Off Delay Time 10 20 ns t Turn - Off Fall Time 5 10 ns Q, Total Gate Charge Vpg = 10 V, 1, = 1.7A, 3.5 5 nc Qy. Gate-Source Charge Ves = 5 V 0.8 nc Qua Gate-Drain Charge 1.7 nc NDSS55AN Rev.CElectrical Characteristics (T, = 25C unless otherwise noted) Symbol | Parameter Conditions | Min | Typ | Max | Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS lg Maximum Continuous Drain-Source Diode Forward Current 0.42 A low Maximum Pulsed Drain-Source Diode Forward Current 10 A Vep Drain-Source Diode Forward Voltage Veg = OV, 1,=0.42 A (Note 2) 0.8 1.2 Vv Notes: 1. Ry, is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R,,, is guaranteed by design while R,,, is determined by the user's board design. Trl _ TTA p Pol) = aarp = Fas etc 1000) X Fos ow yary Typical R,,, using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250C/W when mounted on a 0.02 in? pad of 20z copper. b. 270C/W when mounted on a 0.001 in? pad of 20z copper. Scale 1:1 on letter size paper 2. Pulse Test: Pulse Width < 300p1s, Duty Cycle < 2.0%. NDSS55AN Rev.CTypical Electrical Characteristics 150 = b 2 Ww ac ac 2 Oo lu 9 c 2 9 wn Z < oc a 2 0 05 1 1.5 2 2.5 Vpg. DRAIN-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics. 1.6 T wu ID =1.6A A 3 Ves = 4.5V Z| a 214 8 ~ z a a & 12 yA 2% YY Ss w 62 1 g 2 e 3 zZ z 08 a | 0.6 -50 -25 0 25 50 75 100 125 y , JUNCTION TEMPERATURE (C) Figure 3. On-Resistance Variation with Temperature. T Vpg = 5.0V fy 4 = b = 3 oc 2 o Z> 4, T= 55C y / 0 // 4 ey Ly 125C 1 1.5 2 25 3 3.5 Vos , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. DRAIN-R pston), NORMALIZEDNCE ND % a BR iy 2S a o ms 0 2 4 6 8 Ib , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. ND foo} o foo} eS N wi 9 z a bi 16 No zis zz oO C12 2u - 0 $51 2Q & Los < Z 06 04 0 1 2 3 4 Ip: DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Drain Current and Temperature. 1.2 g a? aad Vos= Ves ag Ip =250HA Wa zo! 2 5 O 09 =e Sy oc 2 9 Ww Ee t o o 1o a o -25 0 25 50 75 100 125 Ty, JUNCTION TEMPERATURE (C) Figure 6. Gate Threshold Variation with Temperature. 150 NDSS55AN Rev.C( \ Typical Electrical Characteristics (continued) iD Ip = 250pA | \ Za -25 0 25 50 75 100 125 150 T, . JUNCTION TEMPERATURE (C) o o BVoss , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 5 z \ o S a Figure 7. Breakdown Voltage Variation with Temperature. 500 300 it 200 & WW oO z & 100 oO < 2 60 oO 40 Crss 20 01 02 05 1 2 5 10 20 30 \bs , DRAIN TO SOURCE VOLTAGE (V) Figure 9. Capacitance Characteristics. D' Vout N Ves _ R GEN ol DUT I) AD LN ' 4 Ss 1 Vop 7) C) Figure 11. Switching Test Circuit. 0.4 0.01 0.001 lg, REVERSE DRAIN CURRENT (A) 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 Vgp , BODY DIODE FORWARD VOLTAGE (V) Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 10 7 Ss | |p=1.6A Vos = 5V 8 8 10V Fi yy in 6 Ky 9 oc 3 fi. Oo 4 4 Ee | oO - 2 3 > 0 . . . . 0 2 4 6 8 Qg , GATE CHARGE (nC) Figure 10. Gate Charge Characteristics. * ton te tote tafony | t, ta (ott) | t; 90% N20 % OUT F 10% 10% INVERTED 90% Vin 50% 10% 5 PULSE WIDTH Figure 12. Switching Waveforms. NDSS55AN Rev.CTypical Electrical Characteristics (continued) NI V pg = 5.0V TJ = -85C oO 26C a 125C TRANSCONDUCTANCE (SIEMENS) nh wo rs Seg T h 4 6 8 10 |), DRAIN CURRENT (A) Figure 13. Transconductance Variation with Drain Current and Temperature. = z L Qo E 0.8 o ao L Q a tr 0.6 1a Ww 6 Vw 20.4 w < L nO y 0.2 4555" FR- ao 5"x5" FR-4 Board < L Ta = 25C = Still Air n 0 0 01 0.2 0.3 0.4 20z COPPER MOUNTING PAD AREA (in?) Figue 15. SuperSOT-3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 0.5 0.2 0.1 0.05 0.02 0.01 0.005 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.002 001 0. 0.0001 0.001 0.01 |p, DRAIN CURRENT (A) 30 10 5 3 1 0.3 0.1 Ves = 4.5V SINGLE PULSE 0.03 Feua =See Note1b Ty = 25C 0.01 01 0.2 05 1 2 5 10 20 30 50 Vos DRAI N-SOURCE VOLTAGE (V) Figure 14. Maximum Safe Operating Area. h o 4.5"x5" FR-4 Board Ta = 25C Still Air Vag = 4.5V 0 01 02 03 04 20z COPPER MOUNTING PAD AREA (in, ) iB > |p, STEADY-STATE DRAIN CURRENT (A) a io Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Rosa (t) = rt) * Reva R gga = See Note 1b + P(pk) Ke -to ! Ty-Ta =P * Rega (t) Duty Cycle, D =t1 A ty, TIME (sec) Figure 17. Transient Thermal Response Curve. Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. NDSS55AN Rev.C