74LVTH646MTCX_NL - Fairchild Semiconductor

November 1999

Revised November 2000

74LVTH646 Low Voltage Octal Transceiver/Register with 3- STATE Outputs

74LVTH646

Low Voltage Octal Transceiver/Register

with 3-STATE Outputs

General Description

The LVTH646 consists of registered bus transceiver cir-

cuits, D-type flip-flops, and contro l circuitry providing multi-

plexed transmission of data directly from the input bus or

from the inte rnal st orage regi sters. Data o n the A or B bus

will be loaded into the respective registers on the LOW-to-

HIGH transition of the appropriate clock pin (CPAB or

CPBA). (See Functional Description)

The LV TH646 data i nputs include b ushold, elim inating the

need for external pull-up resistors to hold unused inputs.

The bus transceivers are designed for low-voltage (3.3V)

VCC applications, but with the capability to provide a TTL

interface to a 5V environm ent. The LVTH646 is fabricated

with an advanced BiCMOS technology to achieve high

speed operation similar to 5V ABT while maintaining low

power dissipation.

Features

■Input and output interface capability to systems at

5V VCC

■Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs

■Live insertion /extracti on per mitt ed

■Power Up/Down high impedance provides glitch-free

bus loading

■Outputs source/sink −32 mA/+64 mA

■Functionally compatible with the 74 series 646

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human-body model > 2000V

Machine model > 200V

Charged-device model > 1000V

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing letter suffix “X” to the ordering co de.

Logic Symbols IEEE/IEC

Order Number Package Number Package Description

74LVTH646WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74LVTH646MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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74LVTH646

Connection Diagram Pin Descriptio ns

Tr uth Table

(Note 1)

H = HIGH Voltage Le ve l L = LOW Voltage Lev el X = Immaterial



= LOW-to-HIGH Transition

Note 1: The data o utput function s may be enabled or dis abled by various s ignals at the OE an d DIR in puts. D ata inpu t function s are alw ays ena bled; i. e.,

data at the bus pi ns w ill be stored on every LO W- to -H I GH t r ansition of th e appropr iat e c lock inputs.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names Description

A0–A7Data Register A Inputs

Data Register A Outputs

B0–B7Data Register B Inputs

Data Register B Outputs

CPAB, CPBA Clock Pulse Inputs

SAB, SBA Transmit/Receive Inputs

OE Output Enable Input

DIR Direction Control Input

Inputs Data I/O Function

OE DIR CPAB CPBA SAB SBA A0–A7B0–B7

H X H or L H or L X X Isolation



X X X Input Input Clock An Data into A Register

HX X



X X Clock Bn Data into B Register

LH X X LX A

n to Bn—Real Time (Transparent Mode)



XLX

Input Output Clock An Data into A Register

L H H or L X H X A Register to Bn (Stored Mode)



X H X Clock An Data into A Register and Output to Bn

LL X X XL B

n to An—Real Time (Transparent Mode)

LL X



Output Input Clock Bn Data into B Register

L L X H or L X H B Register to An (Stored Mode)

LL X



X H Clock Bn Data into B Register and Output to An

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74LVTH646

Functional Description

In the tran scei ve r m ode , da ta p re sent at th e H I GH i mped ance port m ay b e sto re d in e ithe r th e A or B re giste r or bo th. T he

select (SAB, SBA ) controls ca n multiplex stored and real-t ime. The examples below demonst rate the fo ur fundamenta l bus-

management functions that can be performed.

The direction control (DIR) deter mines which bus will receive data when OE is LOW. I n the isola tion mod e (OE HIGH), A

data may be store d in one register an d/or B data ma y be stored i n the othe r register. When an output fun ction is disabled ,

the input func tion is still ena bled and ma y be used to store and transm it data. Only one of the two busses, A or B, may be

driven at a ti me.

Real-Time Transfer

Bus B to Bus A Real-Time Transf er

Bus B to Bus A

Tr an sfe r Stor ag e

Data to A or B Storage

OE DIR CPAB CPBA SAB SBA

LLXXXL

OE DIR CPAB CPBA SAB SBA

LHXXLX

OE DIR CPAB CPBA SAB SBA

LLXH or LXH

LHH or LXHX

OE DIR CPAB CPBA SAB SBA



XLX

LLX



XXX

HXX



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74LVTH646

Absolute Maximum Ratings(No t e 2)

Recommended Operating Conditions

Note 2: Abso lut e Maxim um con t inuous rat ings a re those v alues bey ond whic h dam age to t he devic e m ay occ ur. Exposure to t hese co nditions or c onditions

beyo nd those in dic ated may adver s ely affec t device rel iability. Func tio nal opera ti on under ab s olute maximum rated con dit ions is not implied.

Note 3: IO Absolute Maximum Rating must be observed.

Symbol Parameter Value Conditions Units

VCC Supply Voltage −0.5 to +4.6 V

VIDC Input Voltage −0.5 to +7.0 V

VODC Output Voltage −0.5 to +7.0 Output in 3-STATE V

−0.5 to +7.0 Output in HIGH or LO W State (Note 3) V

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

IODC Output Current 64 VO > VCC Output at HIGH State mA

128 VO > VCC Output at LOW State

ICC DC Supply Current per Supply Pin ±64 mA

IGND DC Ground Current pe r Ground Pi n ±128 mA

TSTG Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

VCC Supply Voltage 2.7 3.6 V

VIInput Voltage 0 5.5 V

IOH HIGH Level Output Curr en t −32 mA

IOL LOW Level Output Current 64

TAFree-Ai r Operating Temp erature −40 85 °C

∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V

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74LVTH646

DC Electrical Characteristics

Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 5: An external driver mus t s ink at least the s pec if ied current to switc h f rom HIG H -t o-LOW.

Note 6: This is the incr eas e in sup ply c urrent for eac h input tha t is at t he specified voltag e level ra th er t han VCC or GND.

Dynamic Switching Characteristics (Note 7)

Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested.

Note 8: Ma x num ber of outpu t s defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.

Symbol Parameter VCC TA =−40°C to +85°CUnits Conditions

(V) Min Max

VIK Input Clamp Diode Voltage 2.7 −1.2 V II = −18 mA

VIH Input HIGH Voltage 2.7–3.6 2.0 VVO ≤ 0.1V or

VIL Input LOW Voltage 2.7 –3.6 0.8 VO ≥ VCC − 0.1V

VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA

2.7 2.4 V IOH = −8 mA

3.0 2.0 V IOH = −32 mA

VOL Output LOW Voltage 2.7 0.2 V IOL = 100 µA

2.7 0.5 V IOL = 24 mA

3.0 0.4 V IOL = 16 mA

3.0 0.5 V IOL = 32 mA

3.0 0.55 V IOL = 64 mA

II(HOLD) Bushold Input Minimum Drive 3.0 75 µAV

I = 0.8V

−75 µAV

I = 2.0V

II(OD) Bushold Input Over-Drive 3.0 500 µA (Note 4)

Current to Change State −500 µA (Note 5)

IIInput Current 3.6 10 µAV

I = 5.5V

Control Pins 3.6 ±1µAV

I = 0V or VCC

Data Pins 3.6 −5µAV

I = 0V

1µAV

I = VCC

IOFF Power Off Leakage Current 0 ±100 µA0V ≤ VI or VO ≤ 5.5V

IPU/PD Power up/down 3-STATE 0–1.5V ±100 µAVO = 0.5V to 3.0V

Output Current VI = GND or VCC

IOZL 3-STATE Output Leakage Current 3.6 −5µAV

O = 0.0V

IOZH 3-STATE Output Leakage Current 3.6 5 µAV

O = 3.6V

IOZH+3-STATE Output Leakage Current 3.6 10 µAV

CC < VO ≤ 5.5V

ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH

ICCL Power Supply Current 3.6 5 mA Outputs LOW

ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled

ICCZ+Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V

Outputs Disabled

∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V

(Note 6) Other Inputs at VCC or GND

Symbol Parameter VCC TA = 25°CUnits Conditions

(V) Min Typ Max CL = 50 pF, RL = 500Ω

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8)

VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8)

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74LVTH646

AC Electrical Characteristics

Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specif ic ation ap plies to an y o ut puts switc hing in the s am e directi on, eit her HIGH-to-L OW (t OSHL) or LOW-to-H I GH (tOSLH).

Capacitance (Note 10)

Note 10: Capacitance is m easured at f requency f = 1 MHz, pe r M IL -STD-88 3B, Met hod 3012.

Symbol Parameter

TA = −40°C to +85°C

Units

CL = 50 pF, RL = 500Ω

VCC = 3.3V ± 0.3V VCC = 2.7V

Min Max Min Max

fMAX Maximum Clock Frequency 150 150 MHz

tPLH Propagation Delay Data to Output 1.8 5.7 1.8 6.3 ns

tPHL Clock to A or B 1.8 5.0 1.8 5.6

tPLH Propagation Delay Data to Output 1.3 4.6 1.3 5.0 ns

tPHL Data to A or B 1.3 4.6 1.3 5.3

tPLH Propagation Delay Data to Output 1.5 5.5 1.5 6.5 ns

tPHL SBA or SAB to A or B 1.5 5.5 1.5 6.3

tPZH Output Enable Time 1.1 5.7 1.1 6.8 ns

tPZL OE to A or B 1.1 6.3 1.1 7.3

tPHZ Output Disable Time 1.9 5.7 2.3 6.1 ns

tPLZ OE to A or B 1.6 5.5 2.3 5.9

tPZH Output Enable Time 1.3 6.1 1.3 6.7 ns

tPZL DIR to A or B 1.3 6.7 1.3 7.7

tPHZ Output Disable Time 1.5 6.2 1.5 7.1 ns

tPLZ DIR to A or B 1.5 5.6 1.5 6.3

tWPulse Duration Clock HIGH or LOW 3.3 3.3 ns

tSSetup Time A or B Before Clock, Data HIGH 1.2 1.5 ns

A or B Before Clock, Data LOW 1.6 2.2

tHHold Time A or B after Clock 0.8 0.8 ns

tOSHL Output to Output Skew (Note 9) 1.0 1.0 ns

tOSLH 1.0 1.0

Symbol Parameter Conditions Typical Units

CIN Input Capacitance V CC = 0V, VI = 0V or VCC 4pF

CI/O Input/Output Capacitan ce VCC = 3.0V, VO = 0V or VCC 8pF

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74LVTH646

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

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74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

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user.

2. A critical compon ent i n any compon ent of a lif e supp ort

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