Voltage Regulators
1
AN8049FHN
1.8-volt 3-channel step-up, step-down, and polarity inverting
DC-DC converter control IC
■Overview
The AN8049FHN is a three-channel PWM DC-DC
converter control IC that features low-voltage operation.
This IC can form a power supply that provides two step-
up outputs and one step-down or polarity inverted output
with a minimal number of external components. Minimal
operating supply voltage of this IC is as low as 1.8 V, so
that it can operate from 2 dry-batteries.
And also, it is housed in an ultrathin, 4-directional-
lead SMD-package whose thickness is 0.8 mm maximum
and pin-pitch is 0.5 mm therefore it is most suitable for
making a power supply small and thin.
■Features
•Wide operating supply voltage range: 1.8 V to 14 V
•High-precision reference voltage circuit
— VREF pin voltage: ±1%
— Error amplifier: ±1.5%
•Ultrathin surface mounting package for miniaturized and thinner power supplies
Package: QFN-24
0.5-mm lead pitch
5.4 mm × 4.4 mm × t0.8 mm
•Supports control over a wide output frequency range: 20 kHz to 1 MHz
•On/off (sequence control) pins provided for each channel for easy sequence control setup
•The negative supply error amplifier supports 0-volt input.
Common-mode input voltage range: − 0.1 V to VCC −1.4 V
This allows the number of external components to be reduced by two resistors.
•Fixed duty factor: 86%
However, the duty can be adjusted to anywhere from 0% to 100% with an external resistor.
•Timer latch short-circuit protection circuit (charge current: 1.1 µA typical)
•Low input voltage malfunction prevention circuit (U.V.L.O.)
(operation start voltage: 1.67 V typical)
•Standby function (active-high control input, standby mode current: 1 µA maximum)
■Applications
•Electronic equipment that requires a power supply system
QFN024-P-0405
Unit: mm
;
;;
;
;;
5.0±0.1
3-C0.5
19 13
1
19
17
13
7
8
12
8
12
24
20
24
20
4.0±0.1
5.2±0.2 (1.10) 3.0±0.2
Seating plane
R0.3
4.0±0.1
2.0±0.2 (1.10)
4.2±0.2
3.0±0.1
A
B
0.2±0.1
0.80max.
S
0.50
0.2±0.1 0.10 S
S
A B
M
0.10
AN8049FHN Voltage Regulators
2
■Pin Descriptions
Pin No. Description
1 DT2
2 DT1
3 CTL3
4 CTL2
5 CTL1
6 Off
7V
REF
8 RB2
9 RB1
10 OUT1
11 OUT2
12 GND
Pin No. Description
13 OUT3
14 VCC
15 OSC
16 IN+3
17 IN−3
18 FB3
19 IN−2
20 FB2
21 IN−1
22 FB1
23 S.C.P.
24 DT3
■Block Diagram
IN-1
21
FB1
22
CTL1
5
VCC
14
DT1
2
VREF
7
OSC
15
Off
6
20 kΩ
1.1 mA
1.26 V
CTL3
DT3
IN−317
IN+3
FB3 18
S.C.P.
RB1
OUT1
OUT3
RB2
OUT2
GND
23
16
3
24
IN−219
FB2 20
1.26 V
Error
amplifier 3
CTL2
DT2
4
1
1.26 V
1.26 V
1.1 mA
1.1 mA
1.1 mA
0.9 V
Error
amplifier 1
Error
amplifier 2
50 kΩ50 kΩ
VREF
VCC
50 kΩ
50 kΩ
VCC
On/off
control
Reference voltage
supply
VREF
Triangular wave generator
1.26 V
(Allowance: ±1%)
S.C.P. comp.
Latch
U.V.L.O.
R
SQ
1.26 V
1.26 V
20 kΩ
20 kΩPWM2
PWM3
PWM1
VREF
50 kΩ
30 kΩ
30 kΩ
50 kΩ
9
10
VCC
11
8
13
12
0.7 V
0.3 V
Voltage Regulators AN8049FHN
3
Note) *1: Ta = 85°C. For the independent IC without a heat sink.
*2: When VCC is less than 6 V, VIN−1 and VIN+2 must be VCC .
■Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply voltage VCC 14.2 V
Off pin allowable application voltage VOFF 14.2 V
Error amplifier input allowable VIN VCC V
application voltage *2
OUT1 and OUT2 pin output ISO(OUT) −50 mA
source current
OUT3 pin output current ISI(OUT) +50 mA
Power dissipation *1 PD111 mW
Operating temperature Topr −30 to +85 °C
Storage temperature Tstg −55 to +150 °C
■Recommended Operating Range
Parameter Symbol Range Unit
Off pin application voltage VOFF 0 to 14 V
OUT1 and OUT2 pin output source current ISO(OUT) −40 (min.) mA
OUT3 pin output current ISI(OUT) 40 (max.) mA
Timing resistance RT3 to 33 kW
Timing capacitance CT100 to 1
000 pF
Oscillator frequency fOUT 20 to 1
000 kHz
Short-circuit protection time-constant setting capacitance CSCP 1
000 (min.) pF
Output current setting resistance RB750 to 15
000 Ω
AN8049FHN Voltage Regulators
4
Parameter Symbol Conditions Min Typ Max Unit
Reference voltage block
Reference voltage VREF IREF = − 0.1 mA 1.247 1.26 1.273 V
Line regulation with input fluctuation Line VCC = 1.8 V to 14 V 220mV
Load regulation Load IREF = − 0.1 mA to −1 mA −20 −3mV
VREF temperature characteristics VRFEdT Ta = −30°C to +85°C1%
VREF pin short-circuit current IOC −10 mA
U.V.L.O. block
Circuit operation start voltage VUON 1.59 1.67 1.75 V
Error amplifier 1 block
Input threshold voltage 1 VTH1 1.241 1.26 1.279 V
Input bias current 1 IB1 0.1 0.2 µA
High-level output voltage 1 VEH1 1.0 1.2 1.4 V
Low-level output voltage 1 VEL1 0.2
Output source current 1 ISO(FB)1 −38 −31 −24 µA
Output sink current 1 ISI(FB)1 0.5 mA
VTH temperature characteristics 1 VTHdT1 Ta = −30°C to +85°C1.5 %
Open-loop gain 1 AV1 80 dB
Error amplifier 2 block
Input threshold voltage 2 VTH2 1.241 1.26 1.279 V
Input bias current 2 IB2 0.1 0.2 µA
High-level output voltage 2 VEH2 1.0 1.2 1.4 V
Low-level output voltage 2 VEL2 0.2
Output source current 2 ISO(FB)2 −38 −31 −24 µA
Output sink current 2 ISI(FB)2 0.5 mA
VTH temperature characteristics 2 VTHdT2 Ta = −30°C to +85°C1.5 %
Open-loop gain 2 AV2 80 dB
Error amplifier 3 block
Input offset voltage VIO −66mV
Common-mode input voltage range VICR − 0.1 VCC V
−
1.4
Input bias current 3 IB3 − 0.6 − 0.3 µA
High-level output voltage 3 VEH3 1.0 1.2 1.4 V
Low-level output voltage 3 VEL3 0.2
Output source current 3 ISO(FB)3 −38 −31 −24 µA
Output sink current 3 ISI(FB)3 0.5 mA
Open-loop gain 3 AV3 80 dB
■Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C
Voltage Regulators AN8049FHN
5
■Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued)
Parameter Symbol Conditions Min Typ Max Unit
Oscillator block
Oscillator frequency fOUT RT = 7.5 kΩ, CT = 680 pF 170 190 210 kHz
Frequency supply voltage fDV RT = 7.5 kΩ, CT = 680 pF 1%
characteristics
Frequency temperature fDT RT = 7.5 kΩ, CT = 680 pF 3%
characteristics
Output 1 block
Output duty factor 1 Du1RT = 7.5 kΩ, CT = 680 pF 80 86 92 %
High-level output voltage 1 VOH1 IO = −10 mA, RB = 1 kΩVCC
−
1 V
Low-level output voltage 1 VOL1 IO = 10 mA, RB = 1 kΩ0.2 V
Output source current 1 ISO(OUT)1 VO = 0.7 V, RB = 1 kΩ−32 −27 −22 mA
Output sink current 1 ISI(OUT)1 VO = 0.7 V, RB = 1 kΩ40 mA
Pull-down resistor 1 RO1 20 30 40 kΩ
Output 2 block
Output duty factor 2 Du2RT = 7.5 kΩ, CT = 680 pF 80 86 92 %
High-level output voltage 2 VOH2 IO = −10 mA, RB = 1 kΩVCC
−
1 V
Low-level output voltage 2 VOL2 IO = 10 mA, RB = 1 kΩ0.2 V
Output source current 2 ISO(OUT)2 VO = 0.7 V, RB = 1 kΩ−32 −27 −22 mA
Output sink current 2 ISI(OUT)2 VO = 0.7 V, RB = 1 kΩ40 mA
Pull-down resistor 2 RO2 20 30 40 kΩ
Output 3 block
Output duty factor 3 Du3RT = 7.5 kΩ, CT = 680 pF 80 86 92 %
Output saturation voltage VO(SAT) 0.2 V
Short-circuit protection circuit block
Input standby voltage VSTBY 0.1 V
Input threshold voltage VTHPC 0.8 0.9 1.0 V
Input latch voltage VIN 0.1 V
Charge current ICHG VSCP = 0 V −1.3 −1.0 −0.7 µA
Comparator threshold voltage VTHL 1.26 V
On/off control block
Input threshold voltage VON(TH) 0.7 1.0 1.3 V
Off pin current IOFF VOFF = 5 V 35 µA
CTL block
Input threshold voltage VTHCTL 1.07 1.26 1.47 V
Charge current ICTL VCTL = 0 V −1.3 −1.0 −0.7 µA
Whole device
Average consumption current ICC(OFF) RB = 9.1 kΩ, duty = 50% 4.2 5.5 mA
Standby mode current ICC(SB) 1µA
AN8049FHN Voltage Regulators
6
Pin No. Equivalent circuit Description I/O
1 DT2: I
Sets the channel 2 soft start time.
Set the time by connecting a capacitor between
this pin and ground.
Note that although the channel 2 maximum on
duty is set internally to 86%, the maximum on
duty can be set to a value of 86% or less by
inserting a resistor between this pin and ground,
and can be set to a value of 86% or more by inse-
rting a resistor between this pin and the VREF pin.
2 DT1:
Sets the channel 1 soft start time.
Set the time by connecting a capacitor between
this pin and ground.
Note that although the channel 1 maximum on
duty is set internally to 86%, the maximum on
duty can be set to a value of 86% or less by
inserting a resistor between this pin and ground,
and can be set to a value of 86% or more by inse-
rting a resistor between this pin and the VREF pin.
3 CTL3: I
Controls the on/off state of channel 3.
A delay can be provided in the power supply
turn-on start time by connecting a capacitor
between this pin and ground.
tDLY3 = 1.26 (V) × CCTL3 (µF)/1.1 (µA) (s)
This pin can also be used to control the on/off
state with an external signal.
In that case, the allowable input voltage range is
from 0 V to VCC. Note that during U.V.L.O. and
timer latch operation, this pin is connected to
ground through a 20 kΩ resistor.
4 CTL2: I
Controls the on/off state of channel 2.
A delay can be provided in the power supply
turn-on start time by connecting a capacitor
between this pin and ground.
tDLY2 = 1.26 (V) × CCTL2 (µF)/1.1 (µA) (s)
This pin can also be used to control the on/off
state with an external signal.
In that case, the allowable input voltage range is
from 0 V to VCC. Note that during U.V.L.O. and
timer latch operation, this pin is connected to
ground through a 20 kΩ resistor.
■Terminal Equivalent Circuits
PWM2
50 kΩ
50 kΩ
1
7 1520
PWM1
50 kΩ
50 kΩ
15
227
2
1.26 V
VCC
20 kΩ1.1 µAHigh
channel 3 operation
is turned off.
3
1.26 V
VCC
20 kΩ1.1 µAHigh
channel 2 operation
is turned off.
4
Voltage Regulators AN8049FHN
7
Pin No. Equivalent circuit Description I/O
5 CTL1: I
Controls the on/off state of channel 1.
A delay can be provided in the power supply
turn-on start time by connecting a capacitor
between this pin and ground.
tDLY1 = 1.26 (V) × CCTL1 (µF)/1.1 (µA) (s)
This pin can also be used to control the on/off
state with an external signal.
In that case, the allowable input voltage range is
from 0 V to VCC. Note that during
U.V.L.O. and
timer latch operation, this pin is
connected to
ground through a 20 kΩ resistor.
6 Off: I
Controls the on/off state.
When the input is high: normal operation
(VOFF > 1.2 V)
When the input is low: standby mode
(VOFF < 0.6 V)
In standby mode, the total current consum-
ption is held to under 1 µA.
7V
REF:O
Outputs the internal reference voltage.
The reference voltage is 1.26 V (allowance:
±1%) when VCC is 2.4 V and IREF is − 0.1 mA.
Insert a capacitor of at least 0.1 µF between VREF
and ground for phase compensation.
8 RB2: I
Connection for a resistor that sets the channel 2
output source current.
Use a resistor in the range 750 Ω to 1.5 kΩ.
9 RB1: I
Connection for a resistor that sets the channel 1
output source current.
Use a resistor in the range 750 Ω to 1.5 kΩ.
■Terminal Equivalent Circuits (continued)
1.26 V
VCC
20 kΩ1.1 µAHigh
channel 1 operation
is turned off.
5
100 kΩ
Start and stop of
internal circuits.
6
VCC
7
V
CC
200 Ω30 kΩ
8
11
V
CC
200 Ω30 kΩ
9
10
AN8049FHN Voltage Regulators
8
Pin No. Equivalent circuit Description I/O
10 OUT1: O
Push-pull output.
The absolute maximum rating for the output
source current is −50 mA.
Connecting the external resistor to RB1 terminal
allows this circuit to provide an output source
current with excellent line regulation and minimal
sample-to-sample variations.
11 OUT2: O
Push-pull output.
The absolute maximum rating for the output
source current is −50 mA.
Connecting the external resistor to RB2 terminal
allows this circuit to provide an output source
current with excellent line regulation and minimal
sample-to-sample variations.
12 GND:
Ground.
13 OUT3: O
Open-collector output.
The absolute maximum rating for the output
current is +50 mA.
14 VCC:
Power supply terminal.
Provide the operating supply voltage in the range
1.8 V to 14 V.
15 OSC: O
Connection for the capacitor and resistor that
determine the oscillator frequency. Use a capa-
citor in the range 100 pF to 1
000 pF and a resistor
in the range 3 kΩ to 33 kΩ. Use an oscillator
frequency in the range 20 kHz to 1 MHz.
16 IN+3: I
Noninverting input to the error amplifier 3.
17 IN−3: I
Inverting input to the error amplifier 3.
■Terminal Equivalent Circuits (continued)
VCC
30 kΩ
ISO(OUT)1
9
10
VCC
30 kΩ
ISO(OUT)2
8
11
12
VCC
13
14
0.2 V
VCC
Latch
S
RQ
15
VCC
1.5 kΩ1.5 kΩ
1617
Voltage Regulators AN8049FHN
9
Pin No. Equivalent circuit Description I/O
18 FB3: O
Output from the error amplifier 3.
This circuit can provide a source current of −31
µA or a sink current of 0.5 mA (minimum).
19 IN−2: I
Inverting input to the error amplifier 2.
20 FB2: O
Output from the error amplifier 2.
This circuit can provide a source current of −31
µA or a sink current of 0.5 mA (minimum).
21 IN−1: I
Inverting input to the error amplifier 1.
22 FB1: O
Output from the error amplifier 1.
This circuit can provide a source current of −31
µA or a sink current of 0.5 mA (minimum).
■Terminal Equivalent Circuit (continued)
31 µA
0.5 mA
min.
OSC PWM3
16
17
18
7
1.26 V
1.5 kΩ
19
14
31 µA
0.5 mA
min.
VCC
1.26 V
OSC PWM2
20
19
1.26 V
1.5 kΩ
14
21
31 µA
VCC
1.26 V
OSC PWM1
21
22
0.5 mA
min.
AN8049FHN Voltage Regulators
10
Pin No. Equivalent circuit Description I/O
23 S.C.P.: O
Connection for the capacitor that sets the timer
latch short-circuit protection circuit time
constant. Use a capacitor with a value of 1 000
pF or higher.
The charge current ICHG is 1.1 µA typical.
24 DT3: I
Sets the channel 3 soft start time.
Set the time by connecting a capacitor between
this pin and ground. Note that although the
channel 3 maximum on duty is set internally to
86%, the maximum on duty can be set to a value
of 86% or less by inserting a resistor between
this pin and ground, and can be set to a value of
86% or more by inserting a resistor between this
pin and the VREF pin.
■Terminal Equivalent Circuits (continued)
1.26 V
V
CC
Latch
S
RQ
1.1 µA
1.5 kΩ
Output
shutoff
23
50 kΩ
50 kΩ
PWM3
24
718 15
■Usage Notes
[1] Allowable power dissipation
Since the power dissipation (P) in this IC increases proportionally with the supply voltage, applications must be
careful to operate so that the loss does not exceed the allowable power dissipation, PD , for the package.
Reference formula:
P = (VCC − VBEQ1) × ISO(OUT)1 × Du1← Power dissipation in the channel 1 output stage
+ (VCC − VBEQ2) × ISO(OUT)2 × Du2← Power dissipation in the channel 2 output stage
+ VO(SAT)3 × IOUT3 × Du3← Power dissipation in the channel 3 output stage
+ VCC × ICC ← Power dissipation between VCC and ground
< PD
VBEQ1 : The voltage between the base and emitter of the npn transistor Q1
ISO(OUT)1 : The OUT1 pin output source current
(When RRB1 is 1 kΩ, ISO(OUT)1 will be 38 mA, maximum.)
Du1: The output 1 duty factor
VBEQ2 : The voltage between the base and emitter of the npn transistor Q2
ISO(OUT)2 : The OUT2 pin output source current
(When RRB2 is 1 kΩ, ISO(OUT)2 will be 38 mA, maximum.)
Du2: The output 2 duty factor
VO(SAT)3 : The OUT3 pin saturation voltage (0.5 V maximum when OUT1 is 40 mA.)
IOUT3 : The OUT3 pin current (This will be {VCC − VBEQ3 − VO(SAT)3}/RO3 .)
Du3: The output 3 duty factor
ICC : The VCC pin current
Voltage Regulators AN8049FHN
11
■Usage Notes (continued)
[2] Allowable VCC ripple
VCC ripple due to the switching transistor being turned on and off can cause this IC's U.V.L.O. circuit, which is
biased by VCC , to operate incorrectly, and can cause the S.C.P. capacitor charging operation to fail to start when the
output is shorted.
The figure shows the allowable range for VCC ripple. Applications should reduce VCC ripple to be within this range,
either by inserting a ripple filter in the VCC line or by inserting a capacitor between the IC GND and VCC pins and
locating that capacitor as close to the IC as possible.
Note that the allowable range shown here is the result of testing the IC alone and that the allowable range may
differ depending on the actual structure of the power supply circuit. Also note that this allowable range is a design
target, and is not guaranteed by testing of all samples.
Allowable VCC ripple
Ripple frequency (Hz)
10M
1M
100k
10k
V
CC
ripple voltage V
CC
(AC) (V[p-p])
012345678
Allowable range
when V
CC
is 3 V.
Allowable range
when V
CC
is 10 V.
■Application Notes
[1] PD Ta curves of QFN024-P-0405
PD Ta
Power dissipation PD (W)
Ambient temperature Ta (°C)
0.000 0 25 50 75 85 100 125
1.200
1.075
1.000
0.800
0.600
0.660
0.400
0.200
0.279
Independent IC
without a heat sink
R
th(j−a)
= 357.4°C/W
When mounted on a 4-layer printed
circuit board (50 × 50 × t0.8 mm
3
)
R
th(j−a)
= 93.0°C/W
When mounted on a standard
printed circuit board
(glass epoxy: 50 × 50 × t0.8 mm
3
)
R
th(j−a)
= 151.5°C/W
AN8049FHN Voltage Regulators
12
■Application Notes (continued)
[2] Main characteristics
Timing capacitance Oscillator frequency fOSC Maximum output duty
10k
1M
10p 1n 10n
CT (F)
fOUT (Hz)
100k
RT = 3 kΩ
RT = 33 kΩ
RT = 7.5 kΩ
95
90
85
80
75 1M100k10k
f
OSC
(Hz)
Du
1
, Du
2
, Du
3
(%)
Du
1
, Du
2
Du
3
R
T
= 3 kΩ
95
90
85
80
75 1M100k10k
f
OSC
(Hz)
Du
1
, Du
2
, Du
3
(%)
Du
1
, Du
2
Du
3
R
T
= 7.5 kΩ
95
90
85
80
75 1M100k10k
fOSC (Hz)
Du1 , Du2 , Du3 (%)
Du3
Du1
Du2
RT = 33 kΩ
100
90
80
70
60
50
40
30
20
10
0100k10k1k100
RB (Ω)
ISI(OUT) (mA)
1.8 V, 2.4 V
8 V
V
CC
= 14 V
0
−10
−20
−30
−40
−50
−60
−70
−80 100k10k1k100
R
B
(Ω)
I
SO(OUT)
(mA)
V
CC
= 1.8 V
2.4 V
14 V
8 V
fOSC Maximum output duty fOSC Maximum output duty
RB ISO(OUT) RB ISI(OUT)
Voltage Regulators AN8049FHN
13
■Application Notes (continued)
[3] Timing charts
Output short
1.26 V
0.9 V
FB OSC DT
1.67 V
1.26 V
VCC pin voltage
waveform
S.C.P. pin
voltage
waveform
CTL pin
voltage
waveform
OUT1/2 pin voltage waveform
Totem pole circuit
output (Step-up output)
OUT3 pin voltage waveform
Open-collector output
(Inverting or step-down output)
AN8049FHN Voltage Regulators
14
■Application Notes (continued)
[4] Function descriptions
1. Reference voltage block
This circuit is composed of a band gap circuit, and outputs a 1.26 V (typical) reference voltage that is
temperature compensated to a precision of ±1%. This reference voltage is stabilized when the supply voltage is 1.8
V or higher. This reference voltage is used by error amplifiers 1 and 2.
2. Triangular wave generator
This circuit generates a triangular wave like a sawtooth
with a peak of 0.7 V and a trough of 0.2 V using a capacitor
CT (for the time constant) and resistor RT connected to the OSC
pin (pin 15). The oscillator frequency can be set to an arbi-
trary value by selecting appropriate values for the external ca-
pacitor and resistor, CT and RT . This IC can use an oscillator
frequency in the range 20 kHz to 1 MHz. The triangular wave
signal is provided to the noninverting input of the PWM com-
parator in each channel internally to the IC. Use the formulas
below for rough calculation of the oscillator frequency.
fOSC ≈ −1≈ 0.8 ×1(Hz)
CT × RT × ln VOSCL CT × RT
VOSCH
Note, however, that the above formulas do not take the rapid charge time, overshoot, and undershoot into
account. See the experimentally determined graph of the oscillator frequency vs. timing capacitance value pro-
vided in the main characteristics section.
3. Error amplifier 1
This circuit is an npn-transistor input error amplifier
that detects and amplifies the DC-DC converter output
voltage, and inputs that signal to a PWM comparator.
The 1.26 V internal reference voltage is applied to the
noninverting input. Arbitrary gain and phase compensa-
tion can be set up by inserting a resistor and capacitor in
series between the FB1 pin (pin 22) and the IN−1 pin
(pin 21). The output voltage VOUT1 can be set using the
circuit shown in the figure.
4. Error amplifier 2
This circuit is an npn-transistor input error amplifier
that detects and amplifies the DC-DC converter output
voltage, and inputs that signal to a PWM comparator.
The 1.26 V internal reference voltage is applied to the
noninverting input. Arbitrary gain and phase compensa-
tion can be set up by inserting a resistor and capacitor in
series between the FB2 pin (pin 20) and the IN−2 pin
(pin 19). The output voltage VOUT2 can be set using the
circuit shown in the figure.
t
2
t
1
T
V
OSCH
≈ 0.7 V
V
OSCL
≈ 0.2 V
Discharge
Figure 1. Triangular oscillator waveform
Rapid
charge
21
22
1.26 V
IN−1To the PWM
comparator input
R2
R1
FB1
V
OUT1
Error
amplifier 1
V
OUT1
= 1.26 × R
1
+ R
2
R
2
Figure 2. Connection method of error amplifier 1
(Step-up output)
19
20
1.26 V
IN−2To the PWN
comparator input
R2
R1
FB2
VOUT2
Error
amplifier 2
VOUT2 = 1.26 × R1 + R2
R2
Figure 3. Connection method of error amplifier 2
(Step-up output)
Voltage Regulators AN8049FHN
15
■Application Notes (continued)
[4] Function descriptions (continued)
5. Error amplifier 3
This circuit is a pnp-transistor input error amplifier that detects and amplifies the DC-DC converter output
voltage and inputs that signal to a PWM comparator. Arbitrary gain and phase compensation can be set up by
inserting a resistor and capacitor in series between the FB3 pin (pin 18) and the IN−3 pin (pin 17). The output voltage
VOUT3 can be set using the circuit shown in the figure.
Step-down output Inverting output
6. Timer latch short-circuit protection circuit
This circuit protects the external main switching elements, flywheel diodes, choke coils, and other components
against degradation or destruction if an excessive load or a short circuit of the power supply output continues for
longer than a certain fixed period.
The timer latch short-circuit protection circuit detects the output of the error amplifiers. If the DC-DC converter
output voltage drops and an FB pin (pins 18, 20, or 22) voltage exceeds 0.9 V, the S.C.P. comparator outputs a low
level and the timer circuit starts. This starts charging the external protection circuit delay time capacitor.
If the error amplifier output does not return to the normal voltage range before that capacitor reaches 1.26 V,
the latch circuit latches, the output drive transistors are turned off, and the dead-time is set to 100%.
7. Low input voltage malfunction prevention circuit (U.V.L.O.)
This circuit protects the system against degradation or destruction due to incorrect control operation when the
power supply voltage falls during power on or power off.
The low input voltage malfunction prevention circuit detects the internal reference voltage that changes with
the supply voltage level. While the supply voltage is rising, this circuit cuts off the output drive transistor until the
reference voltage reaches 1.67 V. It also sets the dead-time to 100% and at the same time holds the S.C.P. pin (pin
23) and the DT pins (pins 1, 2, and 24) at 0 V, and the OSC pin (pin 15) at about 1.2 V.
8. PWM comparators
The PWM comparators control the on-period of the output pulse according to their input voltage.
The output transistors are turned on during periods when the OSC pin (pin 15) triangular wave is lower than
both of the corresponding FB pin (pins 18, 20, or 22) and the corresponding DT pin (pins 1, 2, or 24).
The PWM 2 circuit turns the output transistor on during periods when OSC pin (pin 15) triangular wave is at
a higher level than both of the FB2 pin (pin 20) and the DT2 pin (pin 1).
The maximum duty is set to 86% internally, but it can be set to a value lower than 86% by inserting a resistor
between the corresponding DT pin and ground, and can be set to a value higher than 86% by inserting a resistor
between the corresponding DT pin and the VREF pin.
The IC's soft start function operates to gradually increase the width of the output pulse on-period during
startup if a capacitor is inserted between the DT pin and ground.
IN−3
IN+3
To the PWM
comparator input
R4
R3
R2
R1
FB3
VOUT3
VREF
Error
amplifier 3
VOUT3 = R1 + R2 × R3 + R4 × VREF
R4
R2
16
18
17
IN−3
IN+3
To the PWM
comparator input
R2
R1
FB3
VREF
VOUT3
Error
amplifier 3
VOUT3 = −VREF × R2
R1
16
18
17
Figure 4. Connection method of error amplifier 3
AN8049FHN Voltage Regulators
16
■Application Notes (continued)
[4] Function descriptions (continued)
9. Output 1 and output 2 blocks
These output circuits have a totem pole structure. A constant-current source output with good line regulation
can be set up freely by connecting current setting resistors to the RB pins.
These circuits can provide a constant-current source output of up to 50 mA.
10. Output 3 block
This output circuit has an open collector structure.
An output current of up to 50 mA can be provided, and the output pin has a breakdown voltage of 15 V.
11. CTL block
The CTL block output circuit also has a totem pole structure. A constant-current source output with good line
regulation can be set up freely by connecting current setting resistors to the RB2 pin.
The CTL block can provide a constant-current source output of up to 50 mA.
[5] Time constant setup for the timer latch short-circuit protection circuit
Figure 6 shows the structure of the timer latch short-circuit protection circuit. The short-circuit protection
comparator continuously compares a 0.9 V reference voltage with the FB1, FB2, and FB3 error amplifier outputs.
When the DC-DC converter output load conditions are stable, the short-circuit protection comparator holds its
average value since there are no fluctuations in the error amplifier outputs. At this time, the output transistor Q1 will
be in the conducting state, and the S.C.P. pin will be held at 0 V.
If the output load conditions change rapidly and a high-level signal (0.9 V or higher) is input to the short-circuit
protection comparator from the error amplifier output, the short-circuit protection comparator will output a low level
and the output transistor Q1 will shut off. Then, the capacitor CSCP connected to the S.C.P. pin will start to charge. When
the external capacitor CSCP is charged to about 1.26 V by the constant current of about 1.1 mA, the latch circuit will
latch and the dead-time will be set to 100% with the output held fixed at the low level. Once the latch circuit has
latched, the S.C.P. pin capacitor will be discharged to about 0 V, but the latch circuit will not reset unless either power
is turned off or the power supply is restarted using on/off control.
1.26 V = ICHG ×tPE
CSCP
∴ tPE (s) = 1.15 × CSCP (µF)
At power supply startup, the output appears to be in the shorted
state, and the IC starts to charge the S.C.P. pin capacitor. Therefore,
users must select an external capacitor that allows the DC-DC con-
verter output voltage to rise before the latch circuit in the later stage
latches. In particular, care is required if the soft start function is used,
since that function makes the startup time longer.
Short-circuit detection time tPE
t (s)
0
1.26
VSCP (V)
Figure 5. S.C.P. pin charging waveform
FB2
FB3
FB1
0.9 V
S.C.P. comp.
S.C.P.
High level detection comparator
VREF
VCC
Q1
On/off control
1.1 µA
U.V.L.O.
R
SQ
Latch
1.26 V
Output shutoff
22
18
20
23
Figure 6. Short-circuit protection circuit
Voltage Regulators AN8049FHN
17
■Application Notes (continued)
[6] Parallel synchronous operation of multiple ICs
Multiple instances of this IC can be operated in parallel. If the OSC pins (pin 15) and Off pins (pin 6) are connected
to each other as shown in figure 7, the ICs will operate at the same frequency.
It is also possible to operate a one-channel control IC (e.g. the AN8016SH or AN8016NSH) and a two-channel
control IC (e.g. the AN8017SA or AN8018SA) in this parallel synchronous mode. In this case, short the OSC and Off
pins together.
Note that it is not possible to control the on/off states of each IC operating in this mode independently. It is only
possible to turn all the ICs on or off at the same time remotely.
7
6
2
15
S.C.P.
Off
OSC
OSC
V
REF
7
6
2
15
S.C.P.
Off
V
REF
Off pins
connected
together
OSC pins
connected
together
H
L
AN8049FHN AN8049FHN
Figure 7. Slave operation circuit example
AN8049FHN Voltage Regulators
18
■Application Notes (continued)
[7] Sequential operation
Delays can be provided in the startup times by inserting capacitors (CCTL) between the CTL pins and ground.
Delay time: tDLY = 1.26 (V) × CCTL (µF)/1.1 (µA) (s)
Note that the individual channels can also be turned on or off independently by external signals. These external
signals may have voltages in the range 0 V to VCC.
Figure 8. Sequential operation
3
CCTL3
CCTL2
CCTL1
CTL3
CTL2
CTL1
4
5
AN8049FHN
CCTL1 < CCTL2 < CCTL3
U.V.L.O. cleared
1.26 V
OUT1
OUT2
OUT3
CTL1 CTL2 CTL3
Voltage Regulators AN8049FHN
19
■Application Notes (continued)
[8] Differences between this IC and the AN8049SH
The pin arrangements differ. The AN8049SH is an alternative package version of this IC.
CTL1
Off
VREF
RB2
RB1
OUT1
CTL2
CTL3
DT1
DT2
DT3
S.C.P.
6
5
4
3
2
1
IN+3
OSC
VCC
OUT3
GND
OUT2
18
19
20
21
22
23
24
IN−3
FB3
IN−2
FB2
IN−1
FB1
7
8
9
10
11
12
17
16
15
14
13
AN8049SH
IN−2
FB3
IN−3
IN+3
OSC
VCC
OUT3
19
18
17
16
15
14
13
DT2 1
2
3
4
5
6
7
DT1
CTL3
CTL2
CTL1
Off
VREF
12
11
10
RB1
OUT1
OUT2
GND
9
RB2
8
FB2
IN−1
20
21
FB1 22
S.C.P. 23
DT3 24
AN8049FHN
AN8049FHN Voltage Regulators
20
0
−45
−135
−180
−90
−225
Phase (°)
Frequency (Hz)
100M100k 1M 10M10k1k
40
30
10
−10
20
0
−20
Gain (dB)
Amp.3
1 kW
100 kΩ
1 kΩ
1 kΩ
10 µF
10 µF
FB3
VOUT
1 V
VIN
4 mV[p-p]
IN−3
IN+3
■Application Notes (continued)
[9] Error amplifier frequency characteristics
1. Error amplifiers 1 and 2
(Test circuit)
180
135
45
0
90
−45
Phase (°)
Frequency (Hz)
100M100k 1M 10M10k1k
40
30
10
−10
20
0
−20
Gain (dB)
Amp.1
VREF
1.26 V
100 kΩ
100 kΩ
1 kΩ10 µF
FB1
VOUT
2.3 V
VIN
4 mV[p-p] IN−1
2. Error amplifier 3
(Test circuit)
AN8049FHN Voltage Regulators
22
■Evaluation Board
1. The element numbers of the board pair with the ones of the circuit.
2. "JP" of the board shows the jumper. Short circuit.
•Circuit
IN−2
FB3
IN−3
IN+3
OSC
V
CC
OUT3
19
18
17
16
15
14
13
DT2 1
C1 0.012 µFC18
1 000 pF
2
3
4
5
6
7
DT1
CTL3
CTL2
CTL1
Off
V
REF
12
11
10 OUT1
RB1
RB2
OUT2 Step-up
V
OUT1
+7.5 V
GND
9
8
FB2
IN−1
20
21
FB1 22
S.C.P. 23
DT3 24
C23
R22
R20
1 MΩ
C22
1 000 pF
C20 1
000 pF CIN2
1 MΩ
C24
0.012 µF
0.012 µF
On/Off
LA1
47 µH
RA1
640 kΩ
RA2
130 kΩ
DA1
CA1
CA2
33 µFCA3
QA1
C2 0.012 µF
C3
C4
C5
C7 0.1 µF
R8 3 kΩ
R15
3 kΩ
C15 680 pF
RIN1
GND
R9 1 kΩ
Step-up
V
OUT2
+10 V
V
REF
LB1
100 µH
LC1
RB1
910 kΩ
RB2
130 kΩ
DB1
DC1
CB1
0.012 µF
CB2
10 µF
QB1
QC2
Inverting
V
OUT3
−10 V
Input
V
IN
3 V ∼ 7 V
RC1
100 kΩ
RC3
10 kΩ
RC4
10 kΩ
RC5
1 kΩ
RC2
13 kΩ
CC1
1
000 pF
CC2
1
000 pF
CC3
10 µF
CIN1
1 µF
QC1
CC4
0.47 µF
Input filter
(When no using, short circuit
the both ends of RIN1)
0.47 µF
CB3
0.47 µF
•Board
DA1
CA3
CA2
OUT1
DB1
RC5
QC2
QC1
CC2
RC4
RC3
CIN1
CIN2
RC2
RB2
C18
QB1
LB1
JP
JP
CB3
CB2
C22
C5 C4 C3 C2 C1 C24 C23C7R8R9
C20 CA1
RA1
CB1
RB1
JP
JP
JP
R22
R20
8049
RA2
On/Off
RIN1
C15
R15
DC1 LC1
CC4 CC3
OUT2
OUT3
GND
GND
JP
JP LA1
AN8049FHN
QA1
CC1
RC1
V
IN
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2001 MAR
