LTC1863/LTC1867
1
18637fa
BLOCK DIAGRAM
DESCRIPTION
12-/16-Bit, 8-Channel
200ksps ADCs
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
FEATURES
APPLICATIONS
n Industrial Process Control
n High Speed Data Acquisition
n Battery Operated Systems
n Multiplexed Data Acquisition Systems
n Imaging Systems
n Sample Rate: 200ksps
n 16-Bit No Missing Codes and ±2LSB Max INL
n 8-Channel Multiplexer with:
Single Ended or Differential Inputs and
Unipolar or Bipolar Conversion Modes
n SPI/MICROWIRE™ Serial I/O
n Signal-to-Noise Ratio: 89dB
n Single 5V Operation
n On-Chip or External Reference
n Low Power: 1.3mA at 200ksps, 0.76mA at 100ksps
n Sleep Mode
n Automatic Nap Mode Between Conversions
n 16-Pin Narrow SSOP Package
The LTC
®
1863/LTC1867 are pin-compatible, 8-channel
12-/16-bit A/D converters with serial I/O, and an internal
reference. The ADCs typically draw only 1.3mA from a
single 5V supply.
The 8-channel input multiplexer can be confi gured for
either single-ended or differential inputs and unipolar
or bipolar conversions (or combinations thereof). The
automatic nap and sleep modes benefi t power sensitive
applications.
The LTC1867’s DC performance is outstanding with a
±2LSB INL specifi cation and no missing codes over tem-
perature. The signal-to-noise ratio (SNR) for the LTC1867
is typically 89dB, with the internal reference.
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863/LTC1867 can be used in space-sensitive as well
as low-power applications.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
18637 BD
12-/16-BIT
200ksps
ADC
+
–
SERIAL
PORT
ANALOG
INPUT
MUX
REFCOMP
9
INTERNAL
2.5V REF
LTC1863/LTC1867
OUTPUT CODE
0
INL (LSB)
49152
18637 GO1
16384 32768 65536
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Integral Nonlinearity vs Output Code
(LTC1867)
LTC1863/LTC1867
2
18637fa
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
(Note 1, 2)
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
REFCOMP
TJMAX = 110°C, θJA = 95°C/W
CONVERTER CHARACTERISTICS
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1863CGN#PBF LTC1863CGN#TRPBF 1863 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1863IGN#PBF LTC1863IGN#TRPBF 1863 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC1867CGN#PBF LTC1867CGN#TRPBF 1867 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1867IGN#PBF LTC1867IN#TRPBF 1867 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC1867ACGN#PBF LTC1867ACGN#TRPBF 1867 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1867AIGN #PBF LTC1867AIGN#TRPBF 1867 16-Lead Narrow Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Supply Voltage (VDD) ................................... –0.3V to 6V
Analog Input Voltage
CH0-CH7/COM (Note 3) ...........– 0.3V to (VDD + 0.3V)
V
REF, REFCOMP (Note 4) ......... –0.3V to (VDD + 0.3V)
Digital Input Voltage (SDI, SCK, CS/CONV)
(Note 4) ................................................. –0.3V to 10V
Digital Output Voltage (SDO) ....... –0.3V to (VDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1863C/LTC1867C/LTC1867AC ............ 0°C to 70°C
LTC1863I/LTC1867I/LTC1867AI ...........–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. With external reference (Notes 5, 6)
PARAMETER CONDITIONS
LTC1863 LTC1867 LTC1867A
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution l12 16 16 Bits
No Missing Codes l12 15 16 Bits
Integral Linearity Error Unipolar (Note 7)
Bipolar
l
l
±1
±1
±4
±4
±2
±2.5
LSB
LSB
Differential Linearity Error l±1 –2 3 –1 1.75 LSB
Transition Noise 0.1 0.74 0.74 LSBRMS
Offset Error Unipolar (Note 8)
Bipolar
l
l
±3
±4
±32
±64
±32
±64
LSB
LSB
Offset Error Match Unipolar
Bipolar
±1
±1
±2
±2
±2
±2
LSB
LSB
Offset Error Drift ±0.5 ±0.5 ±0.5 ppm/°C
Gain Error Unipolar
Bipolar
±6
±6
±96
±96
±64
±64
LSB
LSB
LTC1863/LTC1867
3
18637fa
SYMBOL PARAMETER CONDITIONS
LTC1863 LTC1867/LTC1867A
UNITSMIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 1kHz Input Signal 73.6 89 dB
S/(N+D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 73.5 88 dB
THD Total Harmonic Distortion 1kHz Input Signal, Up to 5th Harmonic –94.5 –95 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –94.5 –95 dB
Channel-to-Channel Isolation 100kHz Input Signal –100 –117 dB
Full Power Bandwidth –3dB Point 1.25 1.25 MHz
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS
LTC1863/LTC1867/LTC1867A
UNITSMIN TYP MAX
Analog Input Range Unipolar Mode (Note 9)
Bipolar Mode
l
l
0-4.096
±2.048
V
V
CIN Analog Input Capacitance for CH0 to
CH7/COM
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
32
4
pF
pF
tACQ Sample-and-Hold Acquisition Time l1.5 1.1 μs
Input Leakage Current On Channels, CHX = 0V or VDD l±1 μA
ANALOG INPUT
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
LTC1863/LTC1867/LTC1867A
UNITSMIN TYP MAX
VREF Output Voltage IOUT = 0 2.48 2.5 2.52 V
VREF Output Tempco IOUT = 0 ±15 ppm/°C
VREF Line Regulation 4.75V ≤ VDD ≤ 5.25V 0.43 mV/V
VREF Output Resistance ⏐IOUT ⏐ ≤0.1mA 6 kΩ
REFCOMP Output Voltage IOUT = 0 4.096 V
INTERNAL REFERENCE CHARACTERISTICS
(Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1863/LTC1867/LTC1867A
UNITSMIN TYP MAX
VIH High Level Input Voltage VDD = 5.25V l2.4 V
VIL Low Level Input Voltage VDD = 4.75V l0.8 V
IIN Digital Input Current VIN = 0V to VDD l±10 μA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5)
CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. With external reference (Notes 5, 6)
PARAMETER CONDITIONS
LTC1863 LTC1867 LTC1867A
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Gain Error Match ±1 ±4 ±2 LSB
Gain Error Tempco Internal Reference
External Reference
±15
±2.7
±15
±2.7
±15
±2.7
ppm/°C
ppm/°C
Power Supply Sensitivity VDD = 4.75V – 5.25V ±1 ±5 ±5 LSB
(Note 5)
LTC1863/LTC1867
4
18637fa
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5)
POWER REQUIREMENTS
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1863/LTC1867/LTC1867A
UNITSMIN TYP MAX
VDD Supply Voltage (Note 9) 4.75 5.25 V
IDD Supply Current fSAMPLE = 200ksps
NAP Mode
SLEEP Mode
l
l
1.3
150
0.2
1.8
3
mA
μA
μA
PDISS Power Dissipation l6.5 9 mW
SYMBOL PARAMETER CONDITIONS
LTC1863/LTC1867/LTC1867A
UNITSMIN TYP MAX
fSAMPLE Maximum Sampling Frequency l200 kHz
tCONV Conversion Time l33.5 μs
tACQ Acquisition Time l1.5 1.1 μs
fSCK SCK Frequency 40 MHz
t1CS/CONV High Time Short CS/CONV Pulse Mode l40 100 ns
t2SDO Valid After SCK↓CL = 25pF (Note 11) l13 22 ns
t3SDO Valid Hold Time After SCK↓CL = 25pF l511 ns
t4SDO Valid After CS/CONV↓CL = 25pF l10 30 ns
t5SDI Setup Time Before SCK↑l15 –6 ns
t6SDI Hold Time After SCK↑l10 4 ns
t7SLEEP Mode Wake-Up Time CREFCOMP = 10μF, CVREF = 2.2μF 60 ms
t8Bus Relinquish Time After CS/CONV↑CL = 25pF l20 40 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime
Note 2: All voltage values are with respect to GND (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
SYMBOL PARAMETER CONDITIONS
LTC1863/LTC1867/LTC1867A
UNITSMIN TYP MAX
CIN Digital Input Capacitance 2pF
VOH High Level Output Voltage (SDO) VDD = 4.75V, IO = –10μA
VDD = 4.75V, IO = –200μA l4
4.75
4.74
V
V
VOL Low Level Output Voltage (SDO) VDD = 4.75V, IO = 160μA
VDD = 4.75V, IO = 1.6mA l
0.05
0.1 0.4
V
V
ISOURCE Output Source Current SDO = 0V –32 mA
ISINK Output Sink Current SDO = VDD 19 mA
Hi-Z Output Leakage
Hi-Z Output Capacitance
CS/CONV = High, SDO = 0V or VDD
CS/CONV = High (Note 10)
l
l
±10
15
μA
pF
Data Format Unipolar
Bipolar
Straight Binary
Two’s Complement
LTC1863/LTC1867
5
18637fa
TIMING CHARACTERISTICS
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 200ksps at 25°C, tr = tf = 5ns and
VIN– = 2.5V for bipolar mode unless otherwise specifi ed.
Note 6: Linearity, offset and gain error specifi cations apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
Note 7: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code Histogram for 4096 Conversions
4096 Points FFT Plot (fIN = 1kHz)
4096 Points FFT Plot (fIN = 1kHz,
REFCOMP = External 5V) Crosstalk vs Input Frequency
FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140
75
18637 G04
25 50 100
AMPLITUDE (dB)
FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140
75
18637 G05
25 50 100
AMPLITUDE (dB)
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
1
RESULTING AMPLITUDE ON
SELECTED CHANNEL (dB)
–80
–90
–100
–110
–120
–130
–140 10 100 1000
18637 G06
ADJACENT PAIR
NONADJACENT PAIR
SNR = 88.8dB
SINAD = 87.9dB
THD = 95dB
fSAMPLE = 200ksps
INTERNAL REFERENCE
SNR = 90dB
SINAD = 88.5dB
THD = 94dB
fSAMPLE = 200ksps
VREF = 0V
REFCOMP = EXT 5V
OUTPUT CODE
0
INL (LSB)
49152
18637 GO1
16384 32768 65536
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
OUTPUT CODE
0
DNL (LSB)
4915216384 32768 65536
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
18637 GO2
CODE
–4
COUNTS
4
18637 GO3
–2–3 0–1 321
2500
2000
1500
1000
500
0126
276
2152
579
122 50
935
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1867)
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code fl ickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and
0000 0000 0001 for LTC1863. Bipolar offset is the offset voltage measured
from –1/2LSB when output code fl ickers between 0000 0000 0000 0000
and 1111 1111 1111 1111 for LTC1867, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863.
Note 9: Recommended operating conditions. The input range of ±2.048V
for bipolar mode is measured with respect to VIN– = 2.5V.
Note 10: Guaranteed by design, not subject to test.
Note 11: t2 of 25ns maximum allows fSCK up to 20MHz for rising capture
with 50% duty cycle and fSCK up to 40MHz for falling capture (with 3ns
setup time for the receiving logic).
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
LTC1863/LTC1867
6
18637fa
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1863/LTC1867)
f
SAMPLE
(ksps)
1
SUPPLY CURRENT (mA)
2.0
1.5
1.0
0.5
010 100 1000
18637 G10
SUPPLY VOLTAGE (V)
4.5
SUPPLY CURRENT (mA)
5.5
18637 G11
4.75 5.0 5.25
1.5
1.4
1.3
1.2
1.1
1.0
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
1.5
1.4
1.3
1.2
1.1
1.0
–25 02550
18637 G12
75 100
V
DD
= 5V V
DD
= 5V
f
SAMPLE
= 200ksps
V
DD
= 5V
f
SAMPLE
= 200ksps
OUTPUT CODE
0
INL (LBS)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1024 2048 2560
18637 G13
512 1536 3072 3584 4096
OUTPUT CODE
0
DNL (LBS)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1024 2048 2560
18637 G14
512 1536 3072 3584 4096
Supply Current vs fSAMPLE Supply Current vs Supply Voltage Supply Current vs Temperature
Differential Nonlinearity vs
Output Code (LTC1863)
Integral Nonlinearity vs Output
Code (LTC1863)
Signal-to-Noise Ratio vs
Frequency
Signal-to-(Noise + Distortion) vs
Input Frequency
Total Harmonic Distortion vs
Input Frequency
INPUT FREQUENCY (kHz)
1
AMPLITUDE (dB)
100
90
80
70
60
50
40
30
20
10 100
18637 G07
INPUT FREQUENCY (kHz)
1
AMPLITUDE (dB)
100
90
80
70
60
50
40
30
20
10 100
18637 G08
INPUT FREQUENCY (kHz)
1
AMPLITUDE (dB)
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100
18637 G09
(LTC1867)
LTC1863/LTC1867
7
18637fa
PIN FUNCTIONS
TYPICAL CONNECTION DIAGRAM
TEST CIRCUITS
3k
(A) Hi-Z TO VOH AND VOL TO VOH
CL
3k
5V
DNDN
(B) Hi-Z TO VOL AND VOH TO VOL
CL
18637 TC01
3k
(A) VOH TO Hi-Z
C
L
3k
5V
DNDN
(B) VOL TO Hi-Z
C
L
18637 TC02
Load Circuits for Access Timing Load Circuits for Output Float Delay
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
REFCOMP
LTC1863/
LTC1867
–
+
+
DIGITAL
I/O
5V
4.096V
10μF
2.2μF
2.5V
±2.048V
DIFFERENTIAL
INPUTS
4.096V
SINGLE-ENDED
INPUT
18637 TCD
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
i n p u t s m u s t b e f r e e o f n o i s e w i t h r e s p e c t t o G N D. C H 7/ C O M
can be either a separate channel or the common minus
input for the other channels.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass
to GND with 10μF tantalum capacitor in parallel with
0.1μF ceramic capacitor (4.096V Nominal). To overdrive
REFCOMP, tie VREF to GND.
VREF (Pin 10): 2.5V Reference Output. This pin can also
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2μF tantalum
capacitor in parallel with 0.1μF ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
SDI (Pin 14): Digital Data Input Pin. The A/D confi guration
word is shifted into this input.
GND (Pin 15): Analog and Digital GND.
VDD (Pin 16): Analog and Digital Power Supply. Bypass to
GND with 10μF tantalum capacitor in parallel with 0.1μF
ceramic capacitor.
LTC1863/LTC1867
8
18637fa
TIMING DIAGRAMS
t
5
(SDI Setup Time Before SCK↑),
t
6
(SDI Hold Time After SCK↑)
50%
50%
t
3
0.4V
t
7
(SLEEP Mode Wake-Up Time)
t
7
SCK
CS/CONV
t
8
(BUS Relinquish Time)
t
8
CS/CONV
SDO
2.4V
t
4
(SDO Valid After CONV↓)
t
4
CS/CONV
SDO 2.4V
0.4V
0.4V
t
6
2.4V
0.4V
t
5
SCK
SDI 2.4V
2.4V
0.4V
2.4V
0.4V
SDO
1867 TD
SLEEP BIT (SLP = 0)
READ-IN
10%
90% Hi-Z
Hi-Z
t1
(For Short Pulse Mode) t
2
(SDO Valid Before SCK↑),
t
3
(SDO Valid Hold Time After SCK↓)
t
1
CS/CONV
t
2
SCK
50%
50%
Overview
The LTC1863/LTC1867 are complete, low power multi-
plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a confi gurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 1.5μs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most signifi cant bit (MSB) to the least signifi cant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
APPLICATIONS INFORMATION
LTC1863/LTC1867
9
18637fa
APPLICATIONS INFORMATION
Examples of Multiplexer Options
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
GND (
–
)
8 Single-Ended
+
+
+
+
+
+
+
4 Differential
+
(
–
)
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM (
–
)
7 Single-Ended
to CH7/COM
+
+
+
+
+
+
+
+
(
–
)
+
(
–
)
+
(
–
)
–
(
+
)
–
(
+
)
–
(
+
)
–
(
+
)
GND (
–
)
Combinations of Differential
and Single-Ended
+
+
+
+
+
+
–
–
{
{
{
{
{
{
18637 AI01
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
Analog Input Multiplexer
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defi ned as follows:
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Tables 1 and 2 show the confi gurations when COM = 0,
and COM = 1.
Table 1. Channel Confi guration (When COM = 0, CH7/COM Pin
Is Used as CH7)
Channel Confi guration
SD OS S1 S0 COM “+” “–”
00000 CH0 CH1
00010 CH2 CH3
00100 CH4 CH5
00110 CH6 CH7
01000 CH1 CH0
01010 CH3 CH2
01100 CH5 CH4
01110 CH7 CH6
10000 CH0 GND
10010 CH2 GND
10100 CH4 GND
10110 CH6 GND
11000 CH1 GND
11010 CH3 GND
11100 CH5 GND
11110 CH7 GND
Table 2. Channel Confi guration (When COM = 1, CH7/COM Pin
Is Used as COMMON)
Channel Confi guration
SD OS S1 S0 COM “+” “–”
10001 CH0 CH7/COM
10011 CH2 CH7/COM
10101 CH4 CH7/COM
10111 CH6 CH7/COM
11001 CH1 CH7/COM
11011 CH3 CH7/COM
11101 CH5 CH7/COM
Changing the MUX Assignment “On the Fly”
CH7/COM
(UNUSED) CH7/COM (–)
1st Conversion 2nd Conversion
+
–
+
–
+
–
+
+
{
{
{
{
CH2
CH3
CH4
CH5
CH2
CH3
CH4
CH5
18637 AI02
LTC1863/LTC1867
10
18637fa
Driving the Analog Inputs
The analog inputs of the LTC1863/LTC1867 are easy to
drive. Each of the analog inputs can be used as a single-
ended input relative to the GND pin (CH0-GND, CH1-GND,
etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5,
CH6 and CH7) for differential inputs. In addition, CH7 can
act as a COM pin for both single-ended and differential
modes if the COM bit in the input word is high. Regard-
less of the MUX confi guration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the com-
mon mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors during the acquire mode.
In conversion mode, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low then the LTC1863/LTC1867 inputs can be
driven directly. More acquisition time should be allowed
for a higher impedance source.
The following list is a summary of the op amps that are
suitable for driving the LTC1863/LTC1867. More detailed
information is available in the Linear Technology data
books or Linear Technology website.
LT1007 - Low noise precision amplifi er. 2.7mA supply
current ± 5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifi er. 300μA
supply current. ±5V to ± 15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifi er. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifi er. 3.8mA supply
current. ±5V to ±15V supplies. Good AC/DC specs.
LT1363 - 50MHz voltage feedback amplifi er. 6.3mA supply
current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifi ers. 6.3mA supply current per amplifi er. Good
AC/DC specs.
LT1468 - 90MHz, 22V/μs 16-bit accurate amplifi er
LT1469 - Dual LT1468
Input Filtering
The noise and the distortion of the input amplifi er and
other circuitry must be considered since they will add to
the LTC1863/LTC1867 noise and distortion. Noisy input
circuitry should be fi ltered prior to the analog inputs to
minimize noise. A simple 1-pole RC fi lter is suffi cient for
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal fi lm surface mount resistors
are much less susceptible to both problems.
APPLICATIONS INFORMATION
LTC1863/LTC1867
11
18637fa
APPLICATIONS INFORMATION
DC Performance
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the ADC and the
resulting output codes are collected over a large number
of conversions. For example, in Figure 2 the distribution
of output codes is shown for a DC input that had been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition noise is about 0.74LSB.
1867 F01a
CH0
GND
LTC1863/
LTC1867
REFCOMP
2000pF
10μF
50Ω
ANALOG
INPUT
Figure 1a. Optional RC Input Filtering for Single-Ended Input
Figure 1b. Optional RC Input Filtering for Differential Inputs
Figure 2. LTC1867 Histogram for 4096 Conversions
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 3 shows a typical SINAD of 87.9dB
with a 200kHz sampling rate and a 1kHz input. When an
external 5V is applied to REFCOMP (tie VREF to GND), a
signal-to-noise ratio of 90dB can be achieved.
CODE
–4
COUNTS
4
18637 GO3
–2–3 0–1 321
2500
2000
1500
1000
500
0126
276
2152
579
122 50
935
Figure 3. LTC1867 Nonaveraged 4096 Point FFT Plot
FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140
75
18637 G04
25 50 100
AMPLITUDE (dB)
SNR = 88.8dB
SINAD = 87.9dB
THD = 95dB
f
SAMPLE
= 200ksps
INTERNAL REFERENCE
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD VVV V
V
N
=++ +
20 2232422
1
log ...
LTC1863/LTC1867
12
18637fa
APPLICATIONS INFORMATION
Digital Interface
The LTC1863/LTC1867 have very simple digital interface
that is enabled by the control input, CS/CONV. A logic
rising edge applied to the CS/CONV input will initiate a
conversion. After the conversion, taking CS/CONV low will
enable the serial port and the ADC will present digital data
in two’s complement format in bipolar mode or straight
binary format in unipolar mode, through the SCK/SDO
serial port.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3μs and a maximum conversion time,
3.5μs, over the full operating temperature range. The typi-
cal acquisition time is 1.1μs, and a throughput sampling
rate of 200ksps is tested and guaranteed.
Automatic Nap Mode
The LTC1863/LTC1867 go into automatic nap mode when
CS/CONV is held high after the conversion is complete.
With a typical operating current of 1.3mA and automatic
150μA nap mode between conversions, the power dis-
sipation drops with reduced sample rate. The ADC only
keeps the VREF and REFCOMP voltages active when
the part is in the automatic nap mode. The slower the
sample rate allows the power dissipation to be lower (see
Figure 5).
R2
R3
REFERENCE
AMP
10μF
2.2μF
REFCOMP
GND
V
REF
R1
6k
10
9
15
2.5V
4.096V
LTC1863/LTC1867
1867 F04a
BANDGAP
REFERENCE
10
0.1μF10μF
1867 F04b
LT1019A-2.5
VOUT
VIN
5V
VREF
LTC1863/
LTC1867
GND
REFCOMP
15
9
+
2.2μF
Figure 4b. Using the LT1019-2.5 as an External Reference
Figure 4a. LT1867 Reference Circuit
fSAMPLE (ksps)
1
SUPPLY CURRENT (mA)
2.0
1.5
1.0
0.5
010 100 1000
18637 G10
VDD = 5V
Figure 5. Supply Current vs fSAMPLE
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Reference
The LTC1863/LTC1867 has an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.5V. It is internally connected
to a reference amplifi er and is available at VREF (Pin 10).
A 6k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
reference amplifi er gains the VREF voltage by 1.638V to
4.096V at REFCOMP (Pin 9). This reference amplifi er
compensation pin, REFCOMP, must be bypassed with a
10μF ceramic or tantalum in parallel with a 0.1μF ceramic
for best noise performance.
LTC1863/LTC1867
13
18637fa
APPLICATIONS INFORMATION
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONV returns low either within 100ns after the conver-
sion starts (i.e. before the fi rst bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC
will enter SLEEP mode and draw only leakage current
(provided that all the digital inputs stay at GND or VDD).
After release from the SLEEP mode, the ADC need 60ms
to wake up (2.2μF/10μF bypass capacitors on V
REF/
REFCOMP pins).
Broad Layout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside
an analog signal.
All analog inputs should be screened by GND. V
REF,
REFCOMP and VDD should be bypassed to this ground
plane as close to the pin as possible; the low impedance
of the common return for these bypass capacitors is es-
sential to the low noise operation of the ADC. The width
for these tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital in-
put. The rising edge transition of the CS/CONV will start a
conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Example 1 (Figure 6) shows the LTC1863/LTC1867 operat-
ing in automatic nap mode with CS/CONV signal staying
HIGH after the conversion. Automatic nap mode provides
power reduction at reduced sample rate. The ADCs can also
operate with the CS/CONV signal returning LOW before
the conversion ends. In this mode (Example 2, Figure 7),
the ADCs remain powered up.
F o r b e s t p e r f o r m a n c e , i t i s r e c o m m e n d e d t o k e e p S C K , S D I ,
and SDO at a constant logic high or low during acquisition
and conversion, even though these signals may be ignored
by the serial interface (DON’T CARE). Communication
with other devices on the bus should not coincide with
the conversion period (tCONV).
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
S0SD 0S S1 COM UNI SLP
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1/f
SCK
t
ACQ
CS/CONV
SCK
SDI
SDO
(LTC1863)
Hi-Z
D12D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
12345678910111213141516
1867 F06
DON'T CARE
NOT NEEDED FOR LTC1863
t
CONV
NAP MODE
SDO
(LTC1867)
MSB
MSB
DON'T CARE
DON'T CARE
DON'T CARE
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV Remaining HIGH After
the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate.
LTC1863/LTC1867
14
18637fa
Figure 7. Example 2, CS/CONV Starts a Conversion With Short Active HIGH Pulse.
With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up.
INPUT VOLTAGE (V)
OUTPUT CODE
1867 F09
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLAR
ZERO
FS = 4.096
1LSB = FS/2
n
1LSB = (LTC1863) = 1mV
1LSB = (LTC1867) = 62.5μV
Figure 8. LTC1863/LTC1867 Bipolar Transfer
Characteristics (Two’s Complement)
Figure 9. LTC1863/LTC1867 Unipolar Transfer
Characteristics (Straight Binary)
S0SD 0S S1 COM UNI SLP
MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CS/CONV
SCK
SDI
SDO
(LTC1867)
Hi-Z
12345678910111213141516
t
CONV
D12MSB = D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
1867 F07
t
CONV
DON'T CAREDON'T CARE
NOT NEEDED FOR LTC1863
t
ACQ
SDO
(LTC1863)
DON'T CARE
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLIMENT)
–1
LSB
1867 F08
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 4.096
1LSB = FS/2
n
1LSB = (LTC1863) = 1mV
1LSB = (LTC1867) = 62.5μV
APPLICATIONS INFORMATION
LTC1863/LTC1867
15
18637fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibilit y is assumed for its use. Linear Technology Corporation makes no representa-
t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s .
PACKAGE DESCRIPTION
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
LTC1863/LTC1867
16
18637fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0209 REV A • PRINTED IN USA
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