1.2 A, Ultralow Noise,
High PSRR, RF Linear Regulator
Data Sheet
ADP7157
Rev. B Document Feedback
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FEATURES
Input voltage range: 2.3 V to 5.5 V
Adjustable output voltage range (VOUT): 1.2 V to 3.3 V
Maximum load current: 1.2 A
Low noise
0.9 µV rms typical output noise from 100 Hz to 100 kHz
1.6 µV rms typical output noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR)
82 dB from 1 kHz to 100 kHz
55 dB at 1 MHz
Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V
Initial accuracy: ±0.6% at ILOAD = 10 mA
Accuracy over line, load, and temperature: ±1.5%
Operating supply current (IGND)
4.0 mA typical at 0 µA
7.0 mA typical at 1.2 A
Low shutdown current: 0.2 μA typical
Stable with a 10 µF ceramic output capacitor
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: phase-locked
loops (PLLs), voltage controlled oscillators (VCOs), and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
GENERAL DESCRIPTION
The ADP7157 is an adjustable linear regulator that operates
from 2.3 V to 5.5 V and provides up to 1.2 A of output current.
Output voltages from 1.2 V to 3.3 V are possible depending on
the model. Using an advanced proprietary architecture, the
device provides high power supply rejection and ultralow noise,
achieving excellent line and load transient response with only a
10 µF ceramic output capacitor.
The ADP7157 is available in four models that optimize power
dissipation and PSRR performance as a function of the input
and output voltage. See Table 9 and Table 10 for selection guides.
The typical output noise the ADP7157 regulator is 0.9 μV rms from
100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density from
10 kHz to 1 MHz. The ADP7157 is available in 10-lead, 3 mm ×
3 mm LFCSP and 8-lead SOIC packages, making it not only a
very compact solution, but also providing excellent thermal
performance for applications requiring up to 1.2 A of output
current in a small, low profile footprint.
TYPICAL APPLICATION CIRCUIT
EN
BYP
VREG
ADP7157
REF_SENSE
VIN VOUT
VOUT_SENSE
C
OUT
10µF
V
OUT
= 3.3V
REF
GND
C
IN
10µF
C
REG
1µF
C
BYP
1µF
C
REF
1µF
R1
V
OUT
= 1.2V × ( R1 + R2) /R2
1kΩ < R2 < 200kΩ
R2
V
IN
= 3.8V
12938-001
ON
OFF
Figure 1. Regulated 3.3 V Output from a 3.8 V Input
Table 1. Related Devices
Model
Input
Voltage
Output
Current
Fixed/
Adjustable Package
ADP7159
ADP7158
2.3 V to
5.5 V
2 A
Fixed
10-lead LFCSP/
8-lead SOIC
ADP7156 2.3 V to
5.5 V
1.2 A Fixed/
Adjustable
10-lead LFCSP/
8-lead SOIC
ADM7151
4.5 V to
16 V
800 mA
Fixed/
Adjustable
8-lead LFCSP/
8-lead SOIC
ADM7154,
ADM7155
2.3 V to
5.5 V
600 mA Fixed/
Adjustable
8-lead LFCSP/
8-lead SOIC
ADM7160 2.2 V to
5.5 V
200 mA Fixed 6-lead LFCSP/
5-lead TSOT
0.1
1
10
100
1k
10 100 1k 10k 100k 1M 10M
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
CBYP = 1µ F
CBYP = 10µ F
CBYP = 100µ F
CBYP = 1000µ F
12939-002
Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V
ADP7157 Data Sheet
Rev. B | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
Applications Information .............................................................. 14
ADIsimPower Design Tool ....................................................... 14
Capacitor Selection .................................................................... 14
Undervoltage Lockout (UVLO) ............................................... 15
Programmable Precision Enable .............................................. 16
Start-Up Time ............................................................................. 17
REF, BYP, and VREG Pins......................................................... 17
Current-Limit and Thermal Shutdown ................................... 17
Thermal Considerations ............................................................ 17
PSRR Performance ..................................................................... 20
PCB Layout Considerations .......................................................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
11/2016—Rev. A to Rev. B
Changes to Table 3 ............................................................................ 4
5/2016—Rev. 0 to Rev. A
Added Note 2 to Table 2; Renumbered Sequentially ................... 4
Change to Figure 4 ........................................................................... 6
Change to Programmable Precision Enable Section ................. 16
3/2016—Revision 0: Initial Version
Data Sheet ADP7157
Rev. B | Page 3 of 23
SPECIFICATIONS
VIN = VOUT_MAX1 + 0.5 V; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF; TA = 25°C for typical specifications;
TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE
V
IN
2.3
5.5
V
LOAD CURRENT ILOAD 1.2 A
OPERATING SUPPLY CURRENT IGND ILOAD = 0 µA 4.0 8.0 mA
ILOAD = 1.2 A 7.0 12.0 mA
SHUTDOWN CURRENT IIN-SD EN = ground 0.2 4 µA
NOISE2 VOUT = 1.2 V to 3.3 V
Output Noise OUTNOISE 10 Hz to 100 kHz 1.6 µV rms
100 Hz to 100 kHz 0.9 µV rms
Noise Spectral Density OUTNSD 10 kHz to 1 MHz 1.7 nV/√Hz
POWER SUPPLY REJECTION RATIO2 PSRR ILOAD = 1.2 A
ADP7157-01 1 kHz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V 70 dB
1 MHz, VIN = 2.3 V, VOUT = 1.8 V 52 dB
ADP7157-02 1 kHz to 100 kHz, VIN = 2.8 V, VOUT = 2.3 V 72 dB
1 MHz, VIN = 2.8 V, VOUT = 2.3 V 53 dB
ADP7157-03 1 kHz to 100 kHz, VIN = 3.4 V, VOUT = 2.9 V 75 dB
1 MHz, VIN = 3.4 V, VOUT = 2.9 V 55 dB
ADP7157-04 1 kHz to 100 kHz, VIN = 3.8 V, VOUT = 3.3 V 82 dB
1 MHz, VIN = 3.8 V, VOUT = 3.3 V 55 dB
OUTPUT VOLTAGE ACCURACY
Output Voltage3 VOUT 1.2 3.3 V
Initial Accuracy VOUT ILOAD = 10 mA, TA = 25°C −0.6 +0.6 %
10 mA < I
LOAD
< 1.2 A, T
A
= 25°C
−1.0
+1.0
%
10 mA < I
LOAD
< 1.2 A, T
A
= −40°C to +125°C
−1.5
+1.5
%
REGULATION
Line ∆VOUT/∆VIN VIN = VOUT_MAX + 0.5 V to 5.5 V −0.1 +0.1 %/V
Load4 ∆VOUT/∆IOUT IOUT = 10 mA to 1.2 A 0.3 %/A
CURRENT-LIMIT THRESHOLD5 ILIMIT
REF 22 mA
VOUT
1.4
1.8
2.4
A
DROPOUT VOLTAGE6 VDROPOUT IOUT = 600 mA, VOUT = 3.3 V 60 80 mV
IOUT = 1.2 A, VOUT = 3.3 V 120 170 mV
PULL-DOWN RESISTANCE EN = 0 V, VIN = 5.5 V
VOUT VOUT-PULL VOUT = 1 V 650 Ω
VREG VREG-PULL VREG = 1 V 31 kΩ
REF VREF-PULL VREF = 1 V 850 Ω
BYP VBYP-PULL VBYP = 1 V 650 Ω
START-UP TIME
2, 7
V
OUT
= 3.3 V
VOUT tSTART-UP 1.2 ms
VREG tREG-START-UP 0.6 ms
REF tREF-START-UP 0.5 ms
THERMAL SHUTDOWN2
Threshold TSSD TJ rising 150 °C
Hysteresis TSSD-HYS 15 °C
ADP7157 Data Sheet
Rev. B | Page 4 of 23
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising UVLORISE 2.22 2.29 V
Falling UVLOFALL 1.95 2.02 V
Hysteresis
UVLO
HYS
200
mV
VREG THRESHOLDS8
Rising VREGUVLORISE 1.94 V
Falling VREGUVLOFALL 1.60 V
Hysteresis VREGUVLOHYS 185 mV
EN INPUT PRECISION 2.3 V ≤ VIN ≤ 5.5 V
EN Input
Logic High ENHIGH 1.13 1.22 1.31 V
Logic Low ENLOW 1.05 1.13 1.22 V
Logic Hysteresis ENHYS 90 mV
LEAKAGE CURRENT
REF_SENSE IREF_SENSE_LKG 10 nA
EN IEN_LKG EN = VIN or ground 0.01 1 µA
1 VOUT_MAX is the maximum output voltage of each version of the ADP7157.
2 Guaranteed by characterization, but not production tested.
3 This output voltage specification is for ADP7157-04 version. Table 10 provides a guide for selecting one of the four versions of the ADP7157 based on voltage range.
4 This specification is based on an endpoint calculation using 10 mA and 1.2 A loads.
5 Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage
is the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
6 Dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages
above 2.3 V.
7 Start-up time is the time from the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
8 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
Table 3. Input and Output Capacitors, Recommended Specifications
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
MINIMUM CAPACITANCE TA = −40°C to +125°C
Input1 CIN 7.0 10.0 µF
Regulator1 CREG 0.7 1.0 µF
Output
1
C
OUT
7.0
10.0
µF
Bypass CBYP 0.1 1.0 µF
Reference CREF 0.7 1.0 µF
CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR) RESR TA = −40°C to +125°C
COUT, CIN 0.1 Ω
CREG, CREF 0.2 Ω
CBYP 2.0 Ω
1 The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended, and Y5V and Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADP7157
Rev. B | Page 5 of 23
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VIN to Ground −0.3 V to +7 V
VREG to Ground −0.3 V to VIN or +4 V
(whichever is less)
VOUT to Ground −0.3 V to VREG or +4 V
(whichever is less)
VOUT_SENSE to Ground −0.3 V to VREG or +4 V
(whichever is less)
VOUT to VOUT_SENSE
±0.3 V
BYP to VOUT ±0.3 V
EN to Ground −0.3 V to +7 V
BYP to Ground −0.3 V to VREG or +4 V
(whichever is less)
REF to Ground −0.3 V to VREG or +4 V
(whichever is less)
REF_SENSE to Ground −0.3 V to +4 V
Storage Temperature Range −65°C to +150°C
Operational Junction Temperature
Range
−40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7157 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA).
The maximum TJ is calculated from the TA and the PD using the
following formula:
TJ = TA + (PD × θJA)
The junction to ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The θJA value may vary, depending on
PCB material, layout, and environmental conditions. The specified
θJA values are based on a 4-layer, 4 in. × 3 in. circuit board. See
the JESD51-7 standard and the JESD51-9 standard for detailed
information on the board construction.
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Use the board temperature (TB) and
power dissipation (PD) to calculate the maximum junction
temperature (TJ) by
TJ = TB + (PD × ΨJB)
See the JESD51-8 standard and the JESD51-12 standard for
more detailed information about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type θJA θJC ΨJB Unit
10-Lead LFCSP 53.8 15.6 29.1 °C/W
8-Lead SOIC 50.4 42.3 30.1 °C/W
ESD CAUTION
ADP7157 Data Sheet
Rev. B | Page 6 of 23
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
4BYP
5
EN
2
VOUT
3
VOUT_SENSE
7REF
6 REF_SENSE
9
8
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE . T HE EXPOSE D PAD E NHANCES
THERM
A
L PERFORMANCE, AND IT IS EL ECTRICALLY
CONNE CTED TO G R OUND I NS IDE THE PACKAGE.
CONNE CT THE EP TO THE GROUND PLANE ON THE
BOARD TO ENSURE PROPER OPERATION.
1
VOUT 10
VIN
VREG
VIN
ADP7157
TOP VIEW
(Not to Scale)
12938-003
Figure 3. 10-Lead LFCSP Pin Configuration
VOUT
1
VOUT_SENSE
2
BYP
3
EN
4
VIN
8
VREG
7
REF
6
REF_SENSE
5
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
T HE PACKAGE . T HE EXPO SED PAD ENHANCES
T HE RMAL PERFORMANCE , AND I T I S ELECTRICALLY
CO NNE CTED TO G ROUND I N S IDE THE PACKAGE.
CO NNE CT T HE EP TO TH E GRO UND P LANE ON T HE
BOARD TO ENSURE PROPER OPERATI O N.
ADP7157
TOP VIEW
(No t to S cale)
12938-004
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
LFCSP SOIC
1, 2 1 VOUT Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor.
3 2 VOUT_SENSE
Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect VOUT_SENSE
as close to the load as possible.
4 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF or greater capacitor from the BYP pin to ground to
reduce noise. Do not connect a load to this pin.
5 4 EN Enable. Drive EN high to turn on the regulator, and drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN.
6 5 REF_SENSE Reference Sense. This pin sets the output voltage with an external resistor divider.
VOUT = VREF × (R1 + R2)/R2, where VREF = 1.2 V. Connect REF_SENSE to the REF pin. Do not connect
REF_SENSE to VOUT or ground.
7 6 REF Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short
REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin.
8 7 VREG Regulated Input Supply Voltage to the LDO Amplifier. Bypass VREG to ground with a 1 μF or greater
capacitor.
9, 10 8 VIN Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor.
EP Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances
thermal performance, and it is electrically connected to ground inside the package. Connect the
exposed pad to the ground plane on the board to ensure proper operation.
Data Sheet ADP7157
Rev. B | Page 7 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; VOUT = 3.3 V; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF;
TA = 25°C, unless otherwise noted.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–40 –20 020 40 60 80 100 120 140
TEMPERAT URE ( °C)
2.3V 2.5V
5.5V
5.0V
4.0V
3.0V
IIN–SD (µA)
12938-005
Figure 5. Shutdown Current (IIN-SD) vs. Temperature
at Various Input Voltages (VIN), VOUT =1.8 V
TEMPERAT URE ( °C)
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
–40 –20 020 40 60 80 100 120 140
V
OUT
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-006
Figure 6. Output Voltage (VOUT) vs. Temperature
at Various Loads, VOUT = 3.3 V
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
0.1m 1m 10m 100m 110
V
OUT
(V)
I
LOAD
(A)
12938-007
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V
OUT
(V)
V
IN
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-008
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN)
at Various Loads, VOUT = 3.3 V
TEMPERAT URE ( °C)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
–40 –20 020 40 60 80 100 120 140
I
GND
(mA)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-009
Figure 9. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 3.3 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I
GND
(mA)
I
LOAD
(A)
12938-010
0.1m 1m 10m 100m 110
Figure 10. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 3.3 V
ADP7157 Data Sheet
Rev. B | Page 8 of 23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
I
GND
(mA)
V
IN
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-011
Figure 11. Ground Current (IGND) vs. Input Voltage (VIN)
at Various Loads, VOUT = 3.3 V
12938-012
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
10m 100m 110
V
DROPOUT
(V)
I
LOAD
(A)
Figure 12. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
V
OUT
(V)
V
IN
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-013
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
VOUT = 3.3 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
I
GND
(mA)
V
IN
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-014
Figure 14. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout,
VOUT = 3.3 V
TEMPERAT URE ( °C)
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
–40 –20 020 40 60 80 100 120 140
V
OUT
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-015
Figure 15. Output Voltage (VOUT) vs. Temperature
at Various Loads, VOUT = 1.2 V
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
0.1m 1m 10m 100m 110
V
OUT
(V)
I
LOAD
(A)
12938-016
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.2 V
Data Sheet ADP7157
Rev. B | Page 9 of 23
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
V
OUT
(V)
V
IN
(V)
I
LOAD
= 0mA
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-017
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN)
at Various Loads, VOUT = 1.2 V
TEMPERAT URE ( °C)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
–40 –20 020 40 60 80 100 120 140
IGND (mA)
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 10m A
ILOAD = 0mA
12938-018
Figure 18. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 1.2 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.1m 1m 10m 100m 110
I
GND
(mA)
I
LOAD
(A)
12938-019
Figure 19. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.2 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 55.3 5.6
I
GND
(mA)
V
IN
(V)
I
LOAD
= 10mA
I
LOAD
= 0mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-020
Figure 20. Ground Current (IGND) vs. Input Voltage (VIN)
at Various Loads, VOUT = 1.2 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-021
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 3.3 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
900mV
800mV
700mV
600mV
500mV
12938-022
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 3.3 V, 1.2 A Load
ADP7157 Data Sheet
Rev. B | Page 10 of 23
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.5 0.6 0.7 0.8 0.9
PSRR (dB)
HEADROOM ( V )
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12938-023
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 3.3 V, 1.2 A Load
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-024
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 1.2 V
110 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR ( dB)
1.4V
1.3V
1.2V
1.1V
1.0V
12938-025
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 1.2 V, 1.2 A Load
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1.0 1.1 1.2 1.3 1.4
PSRR ( dB)
HEADROOM ( V )
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12938-026
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 1.2 V, 1.2 A Load
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
1µF
10µF
100µF
1000µF
12938-027
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Different CBYP Values, VOUT = 3.3 V, VIN = 4.0 V, 1.2 A Load
0
0.5
1.0
1.5
2.0
2.5
10m 100m 110
OUT P UT NO ISE ( µV rms)
LO AD CURRE NT (A)
10Hz TO 100kHz
100Hz TO 100kHz
12938-028
Figure 28. RMS Output Noise vs. Load Current (ILOAD)
Data Sheet ADP7157
Rev. B | Page 11 of 23
0
0.5
1.0
1.5
2.0
2.5
1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT NOI SE (µV rms)
OUTPUT VOLTAGE (V)
10Hz TO 100kHz
100Hz TO 100kHz
12938-029
Figure 29. RMS Output Noise vs. Output Voltage
0.1
1
10
100
1k
10 100 1k 10k 100k 1M 10M
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
C
BYP
= 1µF
C
BYP
= 10µF
C
BYP
= 100µF
C
BYP
= 1000µF
12938-032
Figure 30. Noise Spectral Density vs. Frequency at Various Values of CBYP
0.1
1
10
100
1k
10k
100k
0.1 110 100 1k 10k 100k 1M
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-033
Figure 31. Output Noise Spectral Density vs. Frequency
at Various Loads, 0.1 Hz to 1 MHz
0.1
1
10
100
1k
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
I
LOAD
= 10mA
I
LOAD
= 100m A
I
LOAD
= 600m A
I
LOAD
= 1200mA
12938-034
Figure 32. Output Noise Spectral Density vs. Frequency
at Various Loads, 10 Hz to 10 MHz
CH1 500mACH2 5. 00mV M4.00µs A CH1 700mA
1
2
T 21.10%
I
OUT
SLEW RATE = 2.5A/µs
V
OUT
12938-035
BW
BW
Figure 33. Load Transient Response, ILOAD = 100 mA to 1.2 A,
VOUT = 3.3 V, VIN = 4.0 V, Channel 1 = IOUT, Channel 2 = VOUT
CH1 500mACH2 5. 00mV M4.00µs A CH1 690mA
T 22.60%
12938-036
BWBW
1
2
I
OUT
V
OUT
SLEW RATE = 1.5A/µs
Figure 34. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 3.3 V,
VIN = 4.0 V, COUT = 22 µF, Channel 1 = IOUT, Channel 2 = VOUT
ADP7157 Data Sheet
Rev. B | Page 12 of 23
12938-037
1
2
CH1 500mA CH2 5.00mV M4.00µs A CH1 740mA
T 21.30%
BWBW
SLEW RATE = 2.5A/µs
Figure 35. Load Transient Response, ILOAD = 100 mA to 1.2 A,
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = IOUT, Channel 2 = VOUT
CH1 500mA CH2 5. 00mV M4.00µs A CH1 740mA
T 20. 7 0%
12938-038
BWBW
1
2
I
OUT
V
OUT
SLEW RATE = 2.4A/µs
Figure 36. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 1.8 V,
VIN = 2.5 V, COUT = 22 µF, Channel 1 = IOUT, Channel 2 = VOUT
CH1 1.00V CH2 5.00 mV M10.0µs A CH1 4.34V
1
2
T 21.10 %
VIN
SLEW RATE = 1V/µs
VOUT
12938-039
BW
BW
Figure 37. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A,
VOUT = 3.3 V, VIN = 3.8 V, Channel 1 = VIN, Channel 2 = VOUT
CH1 1.00V CH2 2.00 mV M10.0µs A CH1 3.00V
1
2
T 21.80 %
VIN SLEW RATE = 1V/µs
VOUT
12938-040
BWBW
Figure 38. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A,
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = VIN, Channel 2 = VOUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OUT
(V)
TIME (ms)
EN
3.3V
2.5V
1.8V
–2–1012345678
12938-041
Figure 39. VOUT Start-Up Time After VEN Rising
at Various Output Voltages, VIN = 5.0 V, CBYP = 1 F
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–202468101214161820
V
OUT
(V)
TIME (ms)
EN
1µF
4.7µF
10µF
12938-042
Figure 40. VOUT Start-Up Time Behavior at Various Values of CBYP,
VOUT = 3.3 V
Data Sheet ADP7157
Rev. B | Page 13 of 23
THEORY OF OPERATION
The ADP7157 is an ultralow noise, high PSRR linear regulator
targeting radio frequency (RF) applications. The input voltage
range is 2.3 V to 5.5 V, and the device delivers up to a 1.2 A load
current. The typical shut-down current consumption is 0.2 μA
at room temperature.
Optimized for use with 10 μF ceramic capacitors, the ADP7157
provides excellent transient performance.
VREG GND
VOUT
VIN
EN
REF
REF_SENSE
REFERENCE
SHUTDOWN
CURRENT-LIMIT,
THERMAL
PROTECT
BYP
VOUT_SENSE
INTERNAL
REGULATOR
OTA
12938-043
Figure 41. Simplified Internal Block Diagram
Internally, the ADP7157 consists of a reference, an error amplifier,
and a P-channel MOSFET pass transistor. The output current is
delivered via the PMOS pass device, which is controlled by the
error amplifier. The error amplifier compares the reference voltage
with the feedback voltage from the output and amplifies the
difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device pulls lower, allowing more
current to pass and increasing the output voltage. If the feedback
voltage is higher than the reference voltage, the gate of the
PMOS device pulls higher, allowing less current to pass and
decreasing the output voltage.
By heavily filtering the reference voltage, the ADP7157 achieves
1.7 nV/√Hz output typical from 10 kHz to 1 MHz. Because the
error amplifier is always in unity gain, the output noise is
independent of the output voltage.
The ADP7157 output voltage can be adjusted between 1.2 V and
3.3 V and is available in four models that optimize the input voltage
and output voltage ranges to keep power dissipation as low as
possible without compromising PSRR performance. The output
voltage is determined by an external voltage divider according
to the following equation:
VOUT = 1.2 V × (1 + R1/R2)
EN
BYP
VREG
ADP7157
REF_SENSE
VIN VOUT
VOUT_SENSE
C
OUT
10µF
V
OUT
= 3.3V
REF
GND
C
IN
10µF
C
REG
1µF
C
BYP
1µF
C
REF
1µF
R1
V
OUT
= 1.2V × (R1 + R2)/R2
1kΩ < R2 < 200kΩ
R2
V
IN
= 3.8V
ON
OFF
12938-044
Figure 42. Typical Adjustable Output Voltage Application Schematic
The R2 value must be greater than 1 kΩ to prevent excessive
loading of the reference voltage appearing on the REF pin. To
minimize errors in the output voltage caused by the REF_
SENSE pin input current, the R2 value must be less than 200 kΩ.
For example, when R1 and R2 each equal 100 kΩ, the output
voltage is 2.4 V. The output voltage error introduced by the
REF_SENSE pin input current is 10 mV or 0.33%, assuming a
maximum REF_SENSE pin input current of 100 nA at TA = 125°C.
The ADP7157 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is high, VOUT
turns on, and when EN is low, VOUT turns off. For automatic
startup, tie EN to VIN.
VREG
V
IN
REF
VOUT
V
OUT_SENSE
REF_SENSE
BYP
GND
EN
7V
7V 4V4V4V4V4V
4V
4V
4V
7V
4V
4V
12938-045
Figure 43. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 43).
ADP7157 Data Sheet
Rev. B | Page 14 of 23
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
The ADP7157 is supported by the ADIsimPower™ design tool set.
ADIsimPower is a collection of tools that produces complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance within minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count,
taking into consideration the operating conditions and limitations
of the IC and all real external components. For more information
about, and to obtain ADIsimPower design tools, visit
www.analog.com/ADIsimPower.
CAPACITOR SELECTION
Multilayer ceramic capacitors (MLCCs) combine small size, low
ESR, low effective series inductance (ESL), and wide operating
temperature range, making them an ideal choice for bypass
capacitors. They are not without faults, however. Depending on
the dielectric material, the capacit-ance can vary dramatically
with temperature, dc bias, and ac signal level. Therefore, selecting
the proper capacitor results in the best circuit performance.
Output Capacitor
The ADP7157 is designed for operation with ceramic capacitors
but functions with most commonly used capacitors when care
is taken with regard to the ESR value. The ESR of the output
capacitor affects the stability of the LDO control loop. A minimum
of 10 µF capacitance with an ESR of 0.2 Ω or less is recommended
to ensure the stability of the ADP7157. Output capacitance also
affects transient response to changes in load current. Using a
larger value of output capacitance improves the transient
response of the ADP7157 to large changes in load current.
Figure 44 shows the transient responses for an output
capacitance value of 10 µF.
CH1 500mACH2 5. 00mV M4.00µs A CH1 700mA
T 21.10%
12938-046
BW
BW
SLEW RATE = 2.5A/µs
IOUT
VOUT
Figure 44. Output Transient Response, VOUT = 3.3 V, COUT = 10 µF,
Channel 1 = Load Current, Channel 2 = VOUT
Input and VREG Capacitor
Connecting a 10 µF or greater capacitor from VIN to ground
reduces the circuit sensitivity to PCB layout, especially when
long input traces or high source impedance are encountered.
To maintain the best possible stability and PSRR performance,
connect a 1 µF or greater capacitor from VREG to ground.
REF Capacitor
The REF capacitor, CREF, is necessary to stabilize the reference
amplifier. Connect a 1 µF or greater capacitor between REF and
ground
BYP Capacitor
The BYP capacitor, CBYP, is necessary to filter the reference
buffer. A 1 µF capacitor is typically connected between BYP and
ground. Capacitors as small as 0.1 µF can be used; however, the
output noise voltage of the LDO increases as a result.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO. Very large values of CBYP significantly reduce
the noise below 10 Hz. Tantalum capacitors are recommended
for capacitors larger than approximately 33 µF because solid
tantalum capacitors are less prone to microphonic noise issues.
A 1 μF ceramic capacitor in parallel with the larger tantalum
capacitor is recommended to ensure good noise performance at
higher frequencies.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
110 100 1000
OUTPUT NOI S E ( µ V rms)
10Hz TO 100kHz
100Hz TO 100kHz
C
BYP
(µF)
12938-047
Figure 45. RMS Output Noise vs. Bypass Capacitance (CBYP)
Data Sheet ADP7157
Rev. B | Page 15 of 23
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
NOISE SPECTRAL DENSITY (nV/√Hz)
0.1
1
10
100
1k
CBYP = 1µ F
CBYP = 10µ F
CBYP = 100µ F
CBYP = 1000µ F
12938-048
Figure 46. Noise Spectral Density vs. Frequency at Various CBYP Values
Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP7157 if they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V to 50 V are recommended. However,
Y5V and Z5U dielectrics are not recommended because of their
poor temperature and dc bias characteristics.
Figure 47 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
CAPACITANCE ( µF)
DC BIAS V OL TAGE ( V ) 100 4 82 6
0
12
10
8
6
4
2
12938-049
Figure 47. Capacitance vs. DC Bias Voltage
Use Equation 1 to determine the worst case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 − Tempco × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
Tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 9.72 µF at 5 V, as shown in Figure 47.
Substituting these values in Equation 1 yields
CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7157, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP7157 also incorporates an internal UVLO circuit to
disable the output voltage when the input voltage is less than the
minimum input voltage rating of the regulator. The upper and
lower thresholds are internally fixed with about 200 mV of
hysteresis.
0
0.5
1.0
1.5
2.0
2.5
1.9 2.0 2.1 2.2 2.3
V
OUT
(V)
V
IN
(V)
+125°C
+25°C
–40°C
12938-050
Figure 48. Typical UVLO Behavior at Various Temperatures, VOUT = 3.3 V
Figure 48 shows the typical hysteresis of the UVLO function.
This hysteresis prevents on/off oscillations that can occur when
caused by noise on the input voltage as it passes through the
threshold points.
ADP7157 Data Sheet
Rev. B | Page 16 of 23
PROGRAMMABLE PRECISION ENABLE
The ADP7157 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. As shown in Figure 49, when a
rising voltage on EN crosses the upper threshold, nominally 1.22 V,
VOUT turns on. When a falling voltage on EN crosses the lower
threshold, nominally 1.13 V, VOUT turns off. The hysteresis of
the EN threshold is approximately 90 mV.
The ADP7157 includes the discharge resistor on each VOUT,
VREG, VREF, and BYP pin. These resistors are turned on when
the device is disabled, helping to quickly discharge the associated
capacitor.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.00 1.05 1.10 1.15 1.20 1.25 1.30
V
OUT
(V)
EN PIN VOLTAG E (V)
–40°C
–5°C
+25°C
+85°C
+125°C
12938-051
Figure 49. Typical VOUT Response to EN Pin Operation
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–2 –1 012345678
V
OUT
(V)
TIME (ms)
EN
V
OUT
12938-052
Figure 50. Typical VOUT Response to EN Pin Operation (VEN),
VOUT = 3.3 V, VIN = 5 V, CBYP = 1 µF
1.100
1.125
1.150
1.175
1.200
1.225
1.250
2.5 3.0 3.5 4.0 4.5 5.0 5.5
EN PRECISION THRES HOLD ( V )
INP UT VOLTAGE (V)
12938-053
RISING
FALLING
Figure 51. Typical EN Threshold vs. Input Voltages (VIN) for Different
Temperatures
The upper and lower thresholds are user programmable and can be
set higher than the nominal 1.22 V threshold by using two resistors.
The resistance values, REN1 and REN2, can be determined from
REN1 = REN2 × (VEN − 1.22 V)/1.22 V
where:
REN2 typically ranges from 10 kΩ to 100 kΩ.
VEN is the desired turn-on voltage.
The hysteresis voltage increases by the factor
(REN1 + REN2)/REN2
For the example shown in Figure 52, the EN threshold is 2.44 V
with a hysteresis of 200 mV.
EN
BYP
VREG
ADP7157
REF_SENSE
VIN VOUT
VOUT_SENSE
COUT
10µF
VOUT = 3. 3V
REF
GND
CIN
10µF
CREG
1µF
CBYP
1µF
CREF
1µF
R1
VOUT = 1. 2V × ( R1 + R2) /R2
1kΩ < R2 < 200kΩ
R2
VIN = 3.8V
REN2
100kΩ
REN1
100kΩ
ON
OFF
12938-054
Figure 52. Typical EN Pin Voltage Divider
Figure 52 shows the typical hysteresis of the EN pin. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
Data Sheet ADP7157
Rev. B | Page 17 of 23
START-UP TIME
The ADP7157 uses an internal soft start to limit the inrush
current when the output is enabled. The start-up time for a
3.3 V output is approximately 1.2 ms from the time the EN
active threshold is crossed to when the output reaches 90% of
its final value.
The rise time in seconds of the output voltage (10% to 90%) is
approximately 0.0012 × CBYP, where CBYP is in microfarads.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
246810 12 14 16 18 20
V
OUT
(V)
TIME (ms)
–2 0
EN
1µF
4.7µF
10µF
12938-055
Figure 53. Typical Start-Up Behavior with CBYP = 1 µF
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
20 40 60 80 100 120 140 160
V
OUT
(V)
TIME (ms)
EN
10µF
47µF
100µF
–20 0
12938-056
Figure 54. Typical Start-Up Behavior with CBYP = 1 µF to 100 µF
REF, BYP, AND VREG PINS
REF, BYP, and VREG generate voltages internally (VREF, VBYP,
and VREG) that require external bypass capacitors for proper
operation. Do not, under any circumstances, connect any loads
to these pins, because doing so compromises the noise and
PSRR performance of the ADP7157. Using larger values of CBYP,
CREF, and CREG is acceptable but can increase the start-up time,
as described in the Start-Up Time section.
CURRENT-LIMIT AND THERMAL SHUTDOWN
The ADP7157 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP7157 is designed to current limit when the
output load reaches 1.8 A (typical). When the output load
exceeds 1.8 A, the output voltage is reduced to maintain a
constant current limit.
When the ADP7157 junction temperature exceeds 150°C, the
thermal shutdown circuit turns off the output voltage, reducing
the output current to zero. Extreme junction temperature can
be the result of high current operation, poor circuit board
design, or high ambient temperature. A 15°C hysteresis is
included so that the ADP7157 does not return to operation after
thermal shutdown until the on-chip temperature falls below
135°C. When the device exits thermal shutdown, a soft start is
initiated to reduce the inrush current.
Current limit and thermal shutdown protections are intended to
protect the device against accidental overload conditions. Cases
with a hard short from VOUT to ground or an extremely long
soft-start timer typically cause the device to experience thermal
oscillations between current limit and thermal shutdown.
THERMAL CONSIDERATIONS
In applications with a low input to output voltage differential, the
ADP7157 does not dissipate much heat. However, in applications
with high ambient temperature and/or high input voltage, the
heat dissipated in the package may become large enough that it
causes the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7157 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction temperature and ambient air (θJA). The θJA number
is dependent on the package assembly compounds used, as well as
the amount of copper used to solder the package ground and the
exposed pad to the PCB.
ADP7157 Data Sheet
Rev. B | Page 18 of 23
Table 7 shows typical θJA values of the 8-lead SOIC and 10-lead
LFCSP packages for various PCB copper sizes.
Table 8 shows the typical ΨJB values of the 8-lead SOIC and
10-lead LFCSP.
Table 7. Typical θJA Values
θJA (°C/W)
Copper Size (mm2) 10-Lead LFCSP 8-Lead SOIC
251 130.2 123.8
100 93.0 90.4
500 65.8 66.0
1000 55.6 56.6
6400 44.1 45.5
1 Device soldered to minimum size pin traces.
Table 8. Typical ΨJB Values
Package ΨJB (°C/W)
10-Lead LFCSP 29.1
8-Lead SOIC 30.1
The junction temperature of the ADP7157 is calculated from the
following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation caused by ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following equation:
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA) (4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 150°C.
The heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins and
exposed pad of the ADP7157. Adding thermal planes
underneath the package also improves thermal performance.
However, as shown in Table 7, a point of diminishing returns is
eventually reached, beyond which an increase in the copper
area does not yield significant reduction in the junction to
ambient thermal resistance.
Figure 55 to Figure 60 show junction temperature calculations
for different ambient temperatures, power dissipation, and areas
of PCB copper.
0
20
40
60
80
100
120
140
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
JUNCTION TEM P E R ATURE ( °C)
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAXIMUM
12938-057
Figure 55. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 25°C
20
40
60
80
100
120
140
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
JUNCTION TEM P E R ATURE ( °C)
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAXIMUM
12938-058
Figure 56. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 50°C
JUNCTION TEM P ERAT URE ( °C)
80
85
90
95
100
105
110
115
120
125
130
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAXIMUM
12938-059
Figure 57. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 85°C
Data Sheet ADP7157
Rev. B | Page 19 of 23
JUNCTION TEM P E R ATURE ( °C)
0
20
40
60
80
100
120
140
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAXIMUM
12938-060
Figure 58. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
40
50
60
70
80
90
100
110
120
130
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
JUNCTI ON T E M P E R ATURE (° C)
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAXIMUM
12938-061
Figure 59. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
80
85
90
95
100
105
110
115
120
125
130
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
JUNCTI ON T E M P E R ATURE (° C)
TOTAL POWER DISSIPATION (W)
T
J
MAXIMUM
6400mm
2
500mm
2
25mm
2
12938-062
Figure 60. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Thermal Characterization Parameter (ΨJB)
When board temperature is known, use the thermal character-
ization parameter, ΨJB, to estimate the junction temperature rise
(see Figure 61 and Figure 62). Use the board temperature (TB)
and the power dissipation (PD) to calculate the maximum
junction temperature (TJ) by
TJ = TB + (PD × ΨJB) (5)
The typical ΨJB value is 29.1°C/W for the 10-lead LFCSP
package and 30.1°C/W for the 8-lead SOIC package.
0
20
40
60
80
100
120
140
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
JUNCTI ON T E M P E R ATURE (° C)
TOTAL POWER DISSIPATION (W)
T
B
= 25° C
T
B
= 50° C
T
B
= 65° C
T
B
= 85° C
T
J
MAXIMUM
12938-063
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP
0
20
40
60
80
100
120
140
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
JUNCTI ON T E M P E R ATURE (° C)
TOTAL POWER DISSIPATION (W)
TJ MAXIMUM
TB = 25° C
TB = 50° C
TB = 65° C
TB = 85° C
12938-064
Figure 62. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
ADP7157 Data Sheet
Rev. B | Page 20 of 23
PSRR PERFORMANCE
The ADP7157 is available in four models that optimize power
dissipation and PSRR performance as a function of input and
output voltage. See Table 9 and Table 10 for selection guides.
It is recommended to select the corresponding product model for a
particular output voltage range to achieve optimized PSRR
performance. For example, select the ADP7157-04 model for
VOUT = 3.3V to achieve >80 dB PSRR (10 Hz to 100 kHz) with
500 mV headroom.
When considering a VOUT = 1.8 V case, note that all four product
models can generate a 1.8 V output, but the ADP7157-01 model
provides the best PSRR performance, though other models, like
the ADP7157-04, are still capable of generating 1.8 V output for
PSRR relaxed applications.
The ADP7157 supports a 2.3 V to 5.5 V input range. Typically, a
minimum 500 mV headroom is required to achieve the best PSRR
performance above the maximum output voltage (VOUT_MAX) at
1.2 A. For example, ADP7157-04 requires a minimum 3.8 V
input voltage to achieve the best PSRR performance for a 3.3 V
output at 1.2 A.
Table 9. Model Selection Guide for PSRR
Model VOUT_MAX (V)
PSRR (dB) at 1.2 A; VIN = VOUT_MAX + 0.5 V PSRR (dB) at 1.2 A; VIN = VOUT_MAX + 0.6 V
10 kHz
100 kHz
1 MHz
10 kHz
100 kHz
1 MHz
ADP7157-01
1.8
70
78
52
75
85
55
ADP7157-02 2.3 72 70 53 75 83 57
ADP7157-03 2.9 75 78 55 79 94 60
ADP7157-04 3.3 82 72 55 84 86 60
Table 10. Model Selection Guide for Input Voltage
Model Adjustable VOUT Range (V) VOUT Range (V) for Optimized PSRR VREG (V) VIN Range (V)
ADP7157-01 1.2 to 1.8 1.2 to 1.8 2.1 2.3 to 5.5
ADP7157-02 1.2 to 2.3 1.8 to 2.3 2.6 2.8 to 5.5
ADP7157-03 1.2 to 2.9 2.3 to 2.9 3.2 3.4 to 5.5
ADP7157-04 1.2 to 3.3 2.9 to 3.3 3.6 3.8 to 5.5
Data Sheet ADP7157
Rev. B | Page 21 of 23
PCB LAYOUT CONSIDERATIONS
Place the input capacitor as close as possible to the VIN pin and
ground. Place the output capacitor as close as possible to the
VOUT pin and ground. Place the bypass capacitors (CREG, CREF,
and CBYP) for VREG, VREF, and VBYP close to the respective pins
(VREG, REF, and BYP) and ground. The use of a 0805, a 0603,
or a 0402 size capacitor achieves the smallest possible footprint
solution on boards where area is limited. Maximize the amount of
ground metal for the exposed pad, and use as many vias as
possible on the component side to improve thermal dissipation.
12938-065
Figure 63. Sample 10-Lead LFCSP PCB Layout
12938-066
Figure 64. Sample 8-Lead SOIC PCB Layout
ADP7157 Data Sheet
Rev. B | Page 22 of 23
OUTLINE DIMENSIONS
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0. 15)
FO R P ROPE R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
02-05-2013-C
TOP VIEW BOTTOM VIEW
0.20 M I N
Figure 65. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
COMPLIANT TO JEDE C S TANDARDS MS-012-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 M AX
0.05 NO M
3.81 REF
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
Figure 66. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Data Sheet ADP7157
Rev. B | Page 23 of 23
ORDERING GUIDE
Model
1, 2
Temperature Range
Output Voltage Range (V)
Package Description
Package Option
Branding
ADP7157ACPZ-01-R7 −40°C to +125°C 1.2 to 1.8 10-Lead LFCSP CP-10-9 LSX
ADP7157ACPZ-02-R7 −40°C to +125°C 1.2 to 2.3 10-Lead LFCSP CP-10-9 LT0
ADP7157ACPZ-03-R7 −40°C to +125°C 1.2 to 2.9 10-Lead LFCSP CP-10-9 LT1
ADP7157ACPZ-04-R7 −40°C to +125°C 1.2 to 3.3 10-Lead LFCSP CP-10-9 LT2
ADP7157ARDZ-01-R7 −40°C to +125°C 1.2 to 1.8 8-Lead SOIC_N_EP RD-8-1
ADP7157ARDZ-02-R7 −40°C to +125°C 1.2 to 2.3 8-Lead SOIC_N_EP RD-8-1
ADP7157ARDZ-03-R7 −40°C to +125°C 1.2 to 2.9 8-Lead SOIC_N_EP RD-8-1
ADP7157ARDZ-04-R7 −40°C to +125°C 1.2 to 3.3 8-Lead SOIC_N_EP RD-8-1
ADP7157CP-04-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
2 To order a device with voltage options other than the listed options, contact your local Analog Devices sales or distribution representative.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12938-0-11/16(B)