DS1682S+ - MAXIM INTEGRATED PRODUCTS

1 of 14 REV: 081005

GENERAL DESCRIPTION

The DS1682 is an integrated elapsed-time recorder

containing a factory-calibrated, temperature-

compensated RC time base that eliminates the need

for an external crystal. Using EEPROM technology

to maintain data in the absence of power, the DS1682

requires no backup power source. The DS1682

detects and records the number of events on the

EVENT pin and the total cumulative event time since

the DS1682 was last reset to 0. The ALARM pin

alerts the user when the total time accumulated

equals the user-programmed alarm value. The

polarity of the open-drain ALARM pin can be

programmed to either drive low or to become high

impedance upon an alarm condition. The DS1682 is

ideal for applications that monitor the total amount of

time that a device has been in operation and/or the

number of uses since inception of service, repair, or

the last calibration.

APPLICATIONS

High-Temp, Rugged, Industrial Applications Where

Vibration or Shock Could Damage a Quartz

Crystal

Any System Where Time-of-Use is Important

(Warranty Tracking)

ORDERING INFORMATION

PART* PIN-PACKAGE TOP

MARK†

DS1682S 8 SO DS1682

DS1682S+ 8 SO DS1682

DS1682S/T&R 8 SO (Tape and Reel) DS1682

DS1682S+T&R 8 SO (Tape and Reel) DS1682

* All devices are specified over the -40°C to +85°C operating

range.

† A “‘+” anywhere on the top mark denotes a lead(Pb)-free device.

+ Denotes a lead(Pb)-free/RoHS-compliant device.

FEATURES

 Records the Total Time that the Event Input has

Been Active and the Number of Events that have

Occurred

 32-Bit, Nonvolatile, Elapsed Time Counter

(ETC) Monitors Event Duration with Quarter-

Second Resolution and Provides 34 Years of

Total Time Accumulation

 Programmable Elapsed Time ALARM Output

 Nonvolatile 17-Bit Event Counter Records the

Total Number of Times an Event has Occurred

 Calibrated, Temperature-Compensated RC Time

Base Accurate to 2% Typical

 10 Bytes of EEPROM User Memory

 Write Disable Function to Prevent the Memory

from Being Changed or Erased

 2-Wire Serial Communication

 Wide 2.5V to 5.5V Power-Supply Range

 Useful in Time-of-Use Warranty, Calibration,

Repair, and Maintenance Applications

PIN CONFIGURATION

DS1682

Total-Elapsed-Time Recorde

with Alarm

www.maxim-ic.com

SDA

SCL

EVENT

GND

VCC

7 N.C.

N.C.

LARM

DS1682

(

150 mils

)

TOP VIEW

DS1682 Total-Elapsed-Time Recorder with Alarm

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Figure 1. DS1682 Block Diagram

PIN DESCRIPTION

PIN NAME FUNCTION

1 EVENT

Event Input. The EVENT pin is the input the DS1682 monitors to determine when

an event occurs. When the pin is pulled high, the contents of the EEPROM are

transferred to the ETC and the oscillator starts. The ETC begins to count in quarter-

second increments. When the EVENT pin falls to logic 0, the event counter

increments, and the event counter, ETC, and user-memory data are stored in the

EEPROM array. When the EVENT pin changes states, the 2-wire bus is

unavailable for communications for tEW (falling) and tER (rising). The EVENT input

is also deglitched (tG) to prevent short noise spikes from triggering an event.

2, 7 N.C. No Connect. This pin is not connected internally.

3 ALARM

Active-Low Alarm Output. The DS1682 monitors the values in the ETC for the

programmed value in the alarm register. When the ETC matches the alarm value,

the alarm flag (AF) is set. Once set, the alarm flag cannot be reset. See the

operating descriptions for the AOS and AP bits for details about the operation of

the ALARM pin.

4 GND Ground

5 SCL

2-Wire Serial-Clock Input. The SCL pin is the serial-clock input for the 2-wire

synchronous communications channel. The SCL pin is an input that requires an

external pullup resistor.

6 SDA

2-Wire Input/Output. The SDA pin is the data input/output signal for the 2-wire

synchronous communications channel. The SDA pin is an open-drain I/O, which

requires an external pullup resistor.

8 VCC +2.5V to +5.5V Input Supply

OSCILLATOR

AND

DIVIDER

CONTROL

LOGIC

AND

EVENT

GLITCH

FILTER EVENT COUNTER

SERIAL

INTERFACE

USER, CONTROL, AND

CONFIGURATION

REGISTERS

EVENT

SDA

SCL

LARM

ALARM REGS

AND

COMPARE LOGIC

ELAPSED TIME

COUNTER (ETC)

EEPROM ARRAY

VCC

Dallas

Semiconductor

DS1682

DS1682 Total-Elapsed-Time Recorder with Alarm

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OPERATION

The block diagram in Figure 1 shows the relationship between the major functional blocks, the serial

interface, and the EEPROM memory section of the DS1682. Upon power-up, the DS1682 transfers the

contents of the EEPROM into the counters and memory registers where the data can be read and written

through the serial interface. The content of the counters and memory registers are written into the

EEPROM memory when the EVENT pin transitions from a logic high to a logic low.

The DS1682 uses a calibrated, temperature-compensated RC time base to increment an ETC while an

event is active. When the event becomes active, the contents of the nonvolatile EEPROM are transferred

to the ETC and event counter and the oscillator starts. As the event continues, the ETC is incremented in

quarter-second increments. When the event becomes inactive, the event counter is incremented and the

contents of the ETC and event counter are written to the nonvolatile EEPROM.

The ALARM output can be used to indicate when the ETC has matched the value in the alarm register.

The DS1682 can be configured to prevent clearing the alarm and the elapsed time and event counters.

The user memory can be separately write-protected.

User-modified data is not stored in EEPROM until an event becomes inactive.

Figure 2 shows the DS1682 measuring total run time and operating from a battery with the alarm tied to

an LED and a pushbutton switch to trigger the alarm output.

Figure 2. Total Run Time

Figure 3 shows the DS1682 in a total time-of-use application where power may be removed at the same

time as the end of the event. The VCC slew rate at power-down is fast with respect to tEW. A capacitor

maintains VCC on the DS1682 above 2.5V until the EEPROM write completes. A Schottky diode blocks

current from the capacitor to other devices connected to VCC.

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The VCC holding capacitor value of 30μF is calculated using the maximum EEPROM write current and

EEPROM write time. This assumes that the VCC slew rate allows time from EVENT trip point to VCC at

2.5V on the DS1682 is at least tEW.

Figure 4 shows the DS1682 in a total time-of-use application with power that can be removed at the same

time as the end of the event. In this application, the VCC slew rate at power-down is slow with respect to

tEW. The external RST IC ends the event as VCC begins to drop. VCC must remain above 2.5V until the

end of tEW.

Figure 3. Total Time-of-Use Application with Fast VCC Slew Rate

Figure 4. Total Time-of-Use Application with Slow VCC Slew Rate

DS1682 Total-Elapsed-Time Recorder with Alarm

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Table 1. Memory Map

ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION

00 0 AF WDF WMDF AOS RE AP ECMSB

Configuration

01 Low Byte

02 Low-Middle Byte

03 High-Middle Byte

04 High Byte

Alarm Register

05 Low Byte

06 Low-Middle Byte

07 High-Middle Byte

08 High Byte

Elapsed Time

Counter (ETC)

09 Low Byte

0A High Byte Event Counter

0B Byte 1

0C Byte 2

0D Byte 3

0E Byte 4

0F Byte 5

10 Byte 6

11 Byte 7

12 Byte 8

13 Byte 9

14 Byte 10

User Memory

Not Used (reads 00h) Not Used

1D Reset Command Reset Command

1E Write Disable Write Disable

1F Write Memory Disable Memory Disable

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EVENT LOGGING

When the DS1682 is powered up, the event time and count values recorded in the EEPROM are

transferred to the ETC and event counter, and the device waits for an event. When an event triggers the

input by transitioning the EVENT pin from a low to a high level, the following occurs:

1) The RC oscillator starts.

2) The alarm, ETC, and event counter are transferred from EEPROM to RAM.

3) Note: Reading the RAM during the transfer results in invalid data.

4) After tES, the ETC increments. An event greater than tG but less than tES increments the event counter

but not the ETC (zero-length event).

5) The ETC increments every TEI. The ETC holds time in quarter-second resolution.

6) When the EVENT pin goes low, the event counter increments, the oscillator stops, and the ETC and

event counter are transferred to EEPROM. The 2-wire bus is not available for tEW.

The ETC stops counting and does not roll over once FFFFFFFFh, or approximately 34 years, is reached.

See Figure 5 for timing.

Figure 5. Event Input Timing

DEVICE SETUP

Once installed in a system, the DS1682 can be programmed to record events as required by the

application, and can be tested by generating events and monitoring the results. Afterwards, it can be

“locked” to prevent alteration of the event and alarm registers and the alarm condition.

The following is a typical sequence:

1) Write the configuration register, alarm registers, and user memory to the desired values.

2) Write-protect the alarm, ETC, and event counter registers with the write disable command if needed.

3) Write-protect the user memory with the write-memory-disable command, if needed.

4) Issue a reset (described in the Reset Command section).

The alarm, ETC and event counter registers, and user memory, once locked, cannot be changed.

Upon reset, the ETC and event counter registers are cleared. The device clears the RE bit, and the

configuration register becomes read-only. Additional resets are ignored.

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ALARM

The alarm register is a 32-bit register that holds time in quarter-second resolution. When a nonzero

number is programmed into the alarm register, the ALARM function is enabled and the DS1682 monitors

the values in the ETC for the programmed value in the alarm register. When the ETC matches the alarm

value, the alarm flag is set.

EEPROM ARRAY

When power is applied, the contents of the EEPROM are transferred to the configuration register, alarm

VCC minimum for tEW to ensure the EEPROM is properly written.

The EEPROM array for the ETC and the event counter is made up of three banks. Each bank can be

written a maximum of 50k times. The device switches between banks based upon the value in the event

counter. Resetting the event counter before the counter reaches 50,000 will cause additional writes to the

first bank, which can allow writes in excess of 50k. If the event counter is set to greater than 50k or 100k

prior to reset, the device stays on the selected bank. This could result in writes in excess of 50k to one

bank.

The configuration and alarm registers and the user memory are held in one bank of EEPROM. Writes at

the end of an event only occur if the data has changed in one or more of those registers.

User-modified data in any of the registers is stored in EEPROM only if the data was written while an

event was active and is stored when the event ends.

EVENT COUNTER REGISTER

This 17-bit event counter register set provides the total number of data samples logged during the life of

the product up to 131,072 separate events. The event counter consists of 2 bytes of memory in the

memory map plus the event counter MSB bit (ECMSB) in the configuration register. Once the event

counter reaches 1FFFFh, event counting stops.

RESET COMMAND

If RE is set to a 1, a reset occurs when a reset command is sent through the 2-wire bus. A reset command

is issued by writing 55h twice into memory location 1Dh. The writes need not be consecutive. Cycling

power on VCC prior to the second write terminates the reset sequence.

Upon reset, the ETC and event counter registers are cleared. The AF, RE, and ECMSB bits are cleared by

the device, and the configuration register becomes read-only. The data are written to the EEPROM, and

additional resets are ignored.

When a reset command is issued, no additional command should be issued during the EEPROM write

time (tEW).

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CONFIGURATION REGISTER

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 AF WDF WMDF AOS RE AP ECMSB

Note: The configuration register is not stored in EEPROM until an event becomes inactive. RE does not need to be

stored in EEPROM to reset the device.

Bit 6: Alarm Flag (AF). The alarm flag is set to a 1 when the ETC value matches the alarm register.

Once the AF bit is set to a 1, it cannot be set to a 0. This bit is read-only.

Bit 5: Write Disable Flag (WDF). When the write disable command is written to AAh twice at memory

location 1Eh, the WDF is set to a 1 and cannot be cleared or reset. When WDF is set to a 1, the alarm,

ETC, and event counter registers are read-only. This bit is read-only. The writes need not be consecutive.

Cycling power on VCC prior to the second write terminates the reset sequence.

Bit 4: Write-Memory-Disable Flag (WMDF). When the write-memory-disable command is written to

F0h twice at memory location 1Fh, the WMDF is set to a 1 and cannot be reset or cleared. Once the

WMDF is set to a 1, the 10-byte user memory becomes read-only. This bit is read-only. The writes need

not be consecutive. Cycling power on VCC prior to the second write terminates the reset sequence.

Bit 3: Alarm Output Select (AOS). If AOS is 0 and AF is true, the DS1682 activates the ALARM

output during an event when AF becomes true. The DS1682 also activates the ALARM output by pulling

the pin low four times at power-up, at the start and end of an event, or when the ALARM pin is pulled

low and released. This output mode can be used to flash an LED or to communicate with another device

to indicate that an alarm has occurred. AP has no affect on the output when AOS is 0.

If AOS is a 1 and AF is true, the ALARM output is constant when the alarm is active. AP determines the

polarity of the output.

Bit 2: Reset Enable (RE). The reset enable bit allows the device to be reset by enabling the reset

command. The sections of the DS1682 that are reset are then dependent on the value in the WDF. With

the WDF set to 0 and the reset enable bit set to a 1, the reset command clears the ETC, EEPROM, and

event counter. When the reset enable bit is set to a 0, the reset command is disabled.

Bit 1: Alarm Polarity (AP). When the alarm polarity bit in the configuration register is set to 0, the

ALARM output is high impedance during the period that the value in the ETC is less than the alarm

to a 1, the ALARM output is driven low during the period that the ETC is less than the alarm value.

When the ETC matches the alarm value, the ALARM pin becomes high impedance. The AP bit has no

affect if AOS is set to a 0.

Bit 0: Event Counter MSB (ECMSB). This bit is read-only.

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USER MEMORY

There are 10 bytes of user-programmable, EEPROM memory. Once the write-memory disable flag is set

to 1, the memory becomes read-only. User memory is not stored in EEPROM until an event becomes

inactive.

2-WIRE SERIAL DATA BUS

The DS1682 supports a bidirectional, 2-wire bus and data-transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device receiving data, a receiver. The device that controls

the message is called a master, and the devices controlled by the master are slaves. A master device that

generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions

must control the bus. The DS1682 operates as a slave on the 2-wire bus. Connections to the bus are made

through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 6):

 Data transfer can be initiated only when the bus is not busy.

 During data transfer, the data line must remain stable whenever the clock line is high. Changes in the

data line while the clock line is high are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy: Both data and clock lines remain high.

Start Data Transfer: A change in the state of the data line, from high to low, while the clock is high,

defines a START condition.

Stop Data Transfer: A change in the state of the data line, from low to high, while the clock line is high,

defines the STOP condition.

Data Valid: The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the high period of the clock signal. The data on the line must be changed

during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions are not limited, and are

determined by the master device. The information is transferred byte-wise and each receiver

acknowledges with a ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a

fast mode (400kHz clock rate) are defined.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after it

receives each byte. The master device must generate an extra clock pulse, which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of

course, setup and hold times must be considered. A master must signal an end-of-data to the slave by not

DS1682 Total-Elapsed-Time Recorder with Alarm

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generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the

slave must leave the data line high to enable the master to generate the STOP condition.

Depending upon the state of the R/W bit, two types of data transfer are possible:

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is

the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each

received byte.

Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the

slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes

transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes

other than the last byte. A “not acknowledge” is returned at the end of the last received byte.

The master device generates all of the serial clock pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START

condition is also the beginning of the next serial transfer, the bus is not released.

Figure 6. Timing Diagram: Data Transfer on 2-Wire Serial Bus

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The DS1682 can operate in the following two modes:

Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After

each byte is received, the receiver transmits an acknowledge bit. START and STOP conditions are

recognized as the beginning and end of a serial transfer. The slave address byte is the first byte received

after the master generates a START condition. The address byte contains the 7-bit DS1682 address,

which is 1101011, followed by the direction bit (R/W). The second byte from the master is the register

address. This sets the register pointer. The master then transmits each byte of data, with the DS1682

acknowledging each byte received. The register pointer increments after each byte is written. The master

generates a STOP condition to terminate the data write (Figure 7).

Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver

mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data

is transmitted on SDA by the DS1682 while the serial clock is input on SCL. The slave address byte is the

first byte received after the master generates a START condition. The address byte contains the 7-bit

DS1682 address, followed by the direction bit (R/W). After receiving a valid slave address byte and

direction bit, the DS1682 generates an acknowledge on the SDA line. The DS1682 begins to transmit

data on each SCL pulse starting with the register address pointed to by the register pointer. As the master

reads each byte, it must generate an acknowledge. The register pointer increments after each byte is read.

The DS1682 must receive a “not acknowledge” on the last byte to end a read (Figure 8).

Figure 7. Data Write—Slave Receiver Mode

Figure 8. Data Read—Slave Transmitter Mode

–READ/WRITE OR DIRECTION BIT

S 1101011 0 A XXXXXXXX AXXXXXXXX AXXXXXXXX AXXXXXXXX P

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

SLAVE

ADDRESS REGISTER

ADDRESS

S–START

–ACKNOWLEDGE

P– STOP

DATA (n) DATA (n + 1) DATA (n + x)

S 1101011 1 A XXXXXXXX AXXXXXXXX AXXXXXXXX AXXXXXXXX /A

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

SLAVE

ADDRESS

S—START

—- ACKNOWLEDGE

P—- STOP

/A — NOT ACKNOWLEDGE

— READ/WRITE OR DIRECTION BIT

DATA (n) DATA (n + 1) DATA (n + x) DATA (n + 2)

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground…….…………………………………………-0.3V to +6V

Operating Temperature Range……………………………………………….……………..-40°C to +85°C

Storage Temperature Range…………………………………………………..…………...-55°C to +125°C

Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in

the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods of time can affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = -40°C to +85°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power-Supply Voltage VCC 2.5 5.5 V

Input Trip Point VETP 0.3 x

VCC

0.5 x

VCC

0.7 x

VCC V

Event Trip-Point Hysteresis VHYS 1% of

VCC %

DC ELECTRICAL CHARACTERISTICS

(VCC = 2.5V to 5.5V, TA = -40C to +85C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ILI -1 +1 A

ALARM Output (IOL = 10mA) VOL 0.8 V

SDA Output (IOL = 4mA) VOL 0.8 V

Active Supply Current

(Event Active) ICCA (Note 1) 120 300 A

VCC = 5.5V 6 15

Standby Current

(Event Inactive) (Note 1) ICCS VCC = 3.0V 2 4 A

EEPROM Write Current IEE (Note 1) 150 300 A

EVENT TIMING

(VCC = 2.5V to 5.5V, TA = -40C to +85C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Time Event Minimum tG (Note 1) 10 35 70 ms

Time Event Start tES (Note 1) 112 125 137 ms

Time Event Increment tEI (Note 1) 237.5 250 262.5 ms

Time Event Max tEM 34 years

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AC ELECTRICAL CHARACTERISTICS

(VCC = 2.5V to 5.5V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EEPROM Endurance EE (Note 2) 50k writes

EEPROM Write Time tEW (Notes 1, 3, 4) 150 300 ms

EEPROM Transfer to RAM tER (Notes 1, 5) 1 ms

ALARM Output Active-

Low Pulse Width tSL (Note 1) 62.5 ms

ALARM Output Active-

High Pulse Width tSH (Note 1) 437.5 ms

ALARM Input Pulled Low

and Released Pulse Width tSPL (Note 1) 500 ms

Fast mode 400

SCL Clock Frequency fSCL Standard mode 100 kHz

Fast mode 1.3

Bus Free Time Between a

STOP and START

Condition

tBUF Standard mode 4.7 s

Fast mode 0.6

Hold Time (Repeated)

START Condition (Note 6) tHD:STA Standard mode 4.0 s

Fast mode 1.3

LOW Period of SCL tLOW Standard mode 4.7 s

Fast mode 0.6

HIGH Period of SCL tHIGH Standard mode 4.0 s

Fast mode 0.6

Setup Time for a Repeated

START tSU:STA Standard mode 4.7 s

Fast mode 0

Data Hold Time (Notes 7, 8) tHD:DAT Standard mode 0 s

Fast mode 100

Data Setup Time (Note 9) tSU:DAT Standard mode 250 ns

Fast Mode 20 +

0.1CB 300

Rise Time of SDA and SCL

Signals (Note 10) tR

Standard mode 20 +

0.1CB 1000

Fast mode 20 +

0.1CB 300

Fall Time of SDA and SCL

Signals (Note 10) tF

Standard mode 20 +

0.1CB 300

Fast mode 0.6

Setup Time for STOP tSU:STO Standard mode 4.0 s

Input Capacitance (Note 1) CI/O 10 pF

Capacitive Load for Each

Bus Line (Note 10) CB 400 pF

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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

TIMING DIAGRAM

Note 1: Typical values are at +25°C, VCC = 4.0V.

Note 2: The elapsed time and event counters are backed by three EEPROM arrays, which are used

sequentially, allowing up to 3 x EE. The configuration register, alarm trip-point register and user

memory use a single array, limiting them to one EE.

Note 3: A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended.

A typical value is 0.01μF. VCC must be maintained above VCC minimum, including transients, during

EEPROM writes.

Note 4: VCC must be at or above 2.5V for tEW after the end of an event to ensure data transfer to the EEPROM.

Note 5: Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.

Note 6: After this period, the first clock pulse is generated.

Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the

VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.

Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL

signal.

Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must

be met. This is automatically the case if the device does not stretch the tLOW. If such a device does

stretch tLOW, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns

before the SCL line is released.

Note 10: CB—total capacitance of one bus line in pF.

CHIP INFORMATION

TRANSISTOR COUNT: 26,032

PROCESS: CMOS

PACKAGE INFORMATION

For the latest package information and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

8 SO S8+5 21-0041