1
LT1795
1795fa
The LT
®
1795 is a dual current feedback amplifier with high
output current and excellent large signal characteristics.
The combination of high slew rate, 500mA output drive
and up to ±15V operation enables the device to deliver
significant power at frequencies in the 1MHz to 2MHz
range. Short-circuit protection and thermal shutdown
insure the device’s ruggedness. The LT1795 is stable with
large capacitive loads and can easily supply the large
currents required by the capacitive loading. A shutdown
feature switches the device into a high impedance, low
current mode, reducing power dissipation when the de-
vice is not in use. For lower bandwidth applications, the
supply current can be reduced with a single external
resistor.
The LT1795 comes in the very small, thermally enhanced,
20-lead TSSOP package for maximum port density in line
driver applications.
TYPICAL APPLICATION
U
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
Dual 500mA/50MHz
Current Feedback Line Driver
Amplifier
ADSL HDSL2, G.lite Drivers
Buffers
Test Equipment Amplifiers
Video Amplifiers
Cable Drivers
, LTC and LT are registered trademarks of Linear Technology Corporation.
500mA Output Drive Current
50MHz Bandwidth, A
V
= 2, R
L
= 25
900V/
µ
s Slew Rate, A
V
= 2, R
L
= 25
Low Distortion: –75dBc at 1MHz
High Input Impedance, 10M
Wide Supply Range, ±5V to ±15V
Full Rate, Downstream ADSL Supported
Low Power Shutdown Mode
Power Saving Adjustable Supply Current
Stable with C
L
= 10,000pF
Power Enhanced Small Footprint Packages
TSSOP-20, S0-20 Wide
Available in a 20-Lead TSSOP Package
1795 TA01
+
1/2
LT1795
–IN
+
1/2
LT1795
+IN
V
+
V
12.5
1:2*
165
1k
1k
12.5
100
* MIDCOM 50215 OR EQUIVALENT
Low Loss, High Power Central Office ADSL Line Driver
2
LT1795
1795fa
Supply Voltage ...................................................... ±18V
Input Current ...................................................... ±15mA
Output Short-Circuit Duration (Note 2)............ Indefinite
Operating Temperature Range ................ 40°C to 85°C
ORDER PART
NUMBER
T
JMAX
= 150° C, θ
JA
40°C/W (Note 4)
ABSOLUTE AXI U RATI GS
W
WW
U
The denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, ±5V VS ±15V, pulse tested, VSHDN = 2.5V, VSHDNREF = 0V unless otherwise noted. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage ±3±13 mV
±4.5 ±17 mV
Input Offset Voltage Matching ±1±3.5 mV
±1.5 ±5.0 mV
Input Offset Voltage Drift 10 µV/°C
I
IN+
Noninverting Input Current ±2±5µA
±8±20 µA
Noninverting Input Current Matching ±0.5 ±2µA
±1.5 ±7µA
I
IN
Inverting Input Current ±10 ±70 µA
±20 ±100 µA
Inverting Input Current Matching ±10 ±30 µA
±20 ±50 µA
e
n
Input Noise Voltage Density f = 10kHz, R
F
=1k, R
G
= 10, R
S
= 03.6 nV/Hz
+i
n
Input Noise Current Density f = 10kHz, R
F
=1k, R
G
= 10, R
S
= 10k2 pA/Hz
–i
n
Input Noise Current Density f = 10kHz, R
F
=1k, R
G
= 10, R
S
= 10k30 pA/Hz
ELECTRICAL CHARACTERISTICS
(Note 1)
Specified Temperature Range (Note 3)... 40°C to 85°C
Junction Temperature...........................................150°C
Storage Temperature Range ................. 65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
PACKAGE/ORDER I FOR ATIO
UUW
ORDER PART
NUMBER
LT1795CFE
LT1795IFE
1
2
3
4
5
6
7
8
9
10
TOP VIEW
S PACKAGE
20-LEAD PLASTIC SW
20
19
18
17
16
15
14
13
12
11
COMP
V+
OUT
V
V
V
V
–IN
+IN
SHDN
COMP
V+
OUT
V
V
V
V
–IN
+IN
SHDNREF
T
JMAX
= 150° C, θ
JA
= 40°C/W (Note 4)
LT1795CSW
LT1795ISW
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
V
NC
–IN
+IN
SHDN
SHDNREF
+IN
–IN
NC
V
V
NC
OUT
V
+
COMP
COMP
V
+
OUT
NC
V
FE PACKAGE
20-LEAD PLASTIC TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
UNDERSIDE METAL INTERNALLY CONNECTED TO V
(PCB CONNECTION OPTIONAL)
3
LT1795
1795fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
R
IN+
Input Resistance V
IN
= ±12V, V
S
= ±15V 1.5 10 M
V = ±2V, V
S
= ±5V 0.5 5 M
C
IN+
Input Capacitance V
IN
= ±15V 2 pF
Input Voltage Range (Note 5) V
S
= ±15V ±12 ±13.5 V
V
S
= ±5V ±2±3.5 V
CMRR Common Mode Rejection Ratio V
S
= ±15V, V
CM
= ±12V 55 62 dB
V
S
= ±5V, V
CM
= ±2V 50 60 dB
Inverting Input Current V
S
= ±15V, V
CM
= ±12V 110µA/V
Common Mode Rejection V
S
= ±5V, V
CM
= ±2V 110µA/V
PSRR Power Supply Rejection Ratio V
S
= ±5V to ±15V 60 77 dB
Noninverting Input Current V
S
= ±5V to ±15V 30 500 nA/V
Power Supply Rejection
Inverting Input Current V
S
= ±5V to ±15V 15µA/V
Power Supply Rejection
A
V
Large-Signal Voltage Gain V
S
= ±15V, V
OUT
= ±10V, R
L
= 2555 68 dB
V
S
= ±5V, V
OUT
= ±2V, R
L
= 1255 68 dB
R
OL
Transresistance, V
OUT
/I
IN
V
S
= ±15V, V
OUT
= ±10V, R
L
= 2575 200 k
V
S
= ±5V, V
OUT
= ±2V, R
L
= 1275 200 k
V
OUT
Maximum Output Voltage Swing V
S
= ±15V, R
L
= 25Ω±11.5 ±12.5 V
±10.0 ±11.5 V
V
S
= ±5V, R
L
= 12Ω±2.5 ±3V
±2.0 ±3V
I
OUT
Maximum Output Current V
S
= ±15V, R
L
= 10.5 1 A
I
S
Supply Current Per Amplifier V
S
= ±15V, V
SHDN
= 2.5V 29 34 mA
42 mA
Supply Current Per Amplifier, V
S
= ±15V 15 20 mA
R
SHDN
= 51k, (Note 6) 25 mA
Positive Supply Current, Shutdown V
S
= ±15V, V
SHDN
= 0.4V 1 200 µA
Output Leakage Current, Shutdown V
S
= ±15V, V
SHDN
= 0.4V 1 200 µA
Channel Separation V
S
= ±15V, V
OUT
= ±10V, R
L
= 2580 110 dB
HD
2
, HD
3
2nd and 3rd Harmonic Distortion f = 1MHz, V
O
= 20V
P-P
, R
L
= 50, A
V
= 2 –75 dBc
Differential Mode
SR Slew Rate (Note 7) A
V
= 4, R
L
= 400400 900 V/µs
Slew Rate A
V
= 4, R
L
= 25900 V/µs
BW Small-Signal BW A
V
= 2, V
S
= ±15V, Peaking 1.5dB 65 MHz
R
F
= R
G
= 910, R
L
= 100
A
V
= 2, V
S
= ±15V, Peaking 1.5dB 50 MHz
R
F
= R
G
= 820, R
L
= 25
The denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, ±5V VS ±15V, pulse tested, VSHDN = 2.5V, VSHDNREF = 0V unless otherwise noted. (Note 3)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Applies to short-circuits to ground only. A short-circuit between
the output and either supply may permanently damage the part when
operated on supplies greater than ±10V.
Note 3: The LT1795C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and 85°C. The
LT1795I is guaranteed to meet the extended temperature limits.
Note 4: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
Note 5: Guaranteed by the CMRR tests.
Note 6: R
SHDN
is connected between the SHDN pin and V
+
.
Note 7: Slew rate is measured at ±5V on a ±10V output signal while
operating on ±15V supplies with R
F
= 1k, R
G
= 333 (A
V
= +4) and
R
L
= 400.
4
LT1795
1795fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SHDN Pin Current vs Voltage
TEMPERATURE (°C)
–50
40
35
30
25
20
15
10
5
025 75
LT1795 G01
–25 0 50 100 125
SUPPLY CURRENT PER AMPLIFIER (mA)
R
SD
= 0
R
SD
= 51k
V
S
= ±15V
A
V
= 1
R
L
=
TEMPERATURE (°C)
–50
OUTPUT SATURATION VOLTAGE (V)
V
+
–1
–2
–3
–4
4
3
2
1
V
050 75
LT1795 G02
–25 25 100 125
V
S
= ±15V R
L
= 2k
R
L
= 25
R
L
= 25
R
L
= 2k
TEMPERATURE (°C)
–50
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6 25 75
LT1795 G03
–25 0 50 100 125
OUTPUT SHORT-CIRCUIT CURRENT (A)
SINKING
SOURCING
V
S
= ±15V
Supply Current vs Ambient
Temperature
VOLTAGE APPLIED AT SHDN PIN (V)
0 1 2 3 4 5
CURRENT INTO SHDN PIN (mA)
1795 G04
0.6
0.5
0.4
0.3
0.2
0.1
0
V
S
= ±15V
V
SHDNREF
= 0V
Output Saturation Voltage vs
Junction Temperature
Output Short-Circuit Current vs
Junction Temperature
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G05
IQ = 5mA
IQ = 10mA
IQ = 15mA
IQ = 20mA
AV = 2 DIFFERENTIAL
VOUT = 20VP-P
VS = ±15V
RLOAD = 50
IQ PER AMPLIFIER
DISTORTION (dBc)
FREQUENCY (Hz)
DISTORTION (dBc)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G06
I
Q
= 10mA
I
Q
= 15mA
I
Q
= 20mA
A
V
= 2 DIFFERENTIAL
V
OUT
= 20V
P-P
V
S
= ±15V
R
LOAD
= 50
I
Q
PER AMPLIFIER I
Q
= 5mA
Second Harmonic Distortion vs
Frequency
Third Harmonic Distortion vs
Frequency
SMALL-SIGNAL BANDWIDTH
UU
W
–3dB BW
AVRFRG(MHz)
–1 976 976 30
1 1.15k 32
2 976 976 32
10 649 72 27
RSD = 0, IS = 30mA per Amplifer, VS = ±15V,
Peaking 1dB, RL = 25
–3dB BW
AVRFRG(MHz)
–1 976 976 44
1 1.15k 53
2 976 976 48
10 649 72 46
RSD = 51k, IS = 15mA per Amplifer, VS = ±15V,
Peaking 1dB, RL = 25
5
LT1795
1795fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G11
I
Q
= 5mA
A
V
= 10 DIFFERENTIAL
V
OUT
= 20V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 20mA
I
Q
= 10mA
I
Q
= 15mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G12
I
Q
= 5mA
I
Q
= 10mA
I
Q
= 15mA
A
V
= 10 DIFFERENTIAL
V
OUT
= 20V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 20mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G10
I
Q
= 5mA
I
Q
= 10mA
I
Q
= 15mA
A
V
= 2 DIFFERENTIAL
V
OUT
= 20V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 20mA
Third Harmonic Distortion vs
Frequency
Third Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
Third Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G13
AV = 2 DIFFERENTIAL
VOUT = 4VP-P
VS = ±12V
RLOAD = 50
IQ PER AMPLIFIER
DISTORTION (dBc)
IQ = 5mA
IQ = 20mA IQ = 15mA
IQ = 10mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G14
A
V
= 2 DIFFERENTIAL
V
OUT
= 4V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 5mA
I
Q
= 10mA
I
Q
= 15mA
I
Q
= 20mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G15
A
V
= 10 DIFFERENTIAL
V
OUT
= 4V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 5mA
I
Q
= 10mA
I
Q
= 20mA
I
Q
= 15mA
Second Harmonic Distortion vs
Frequency
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G07
I
Q
= 5mA
I
Q
= 15mA
A
V
= 10 DIFFERENTIAL
V
OUT
= 20V
P-P
V
S
= ±15V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 20mA
I
Q
= 10mA
Third Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
FREQUENCY (Hz)
DISTORTION (dBc)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G08
IQ = 5mA
IQ = 10mA
IQ = 20mA
AV = 10 DIFFERENTIAL
VOUT = 20VP-P
VS = ±15V
RLOAD = 50
IQ PER AMPLIFIER
IQ = 15mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G09
I
Q
= 5mA
I
Q
= 15mA
I
Q
= 20mA
A
V
= 2 DIFFERENTIAL
V
OUT
= 20V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 10mA
6
LT1795
1795fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Third Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G19
A
V
= 10 DIFFERENTIAL
V
OUT
= 4V
P-P
V
S
= ±5V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 5mA
I
Q
= 10mA
I
Q
= 15mA
I
Q
= 20mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G20
AV = 10 DIFFERENTIAL
VOUT = 4VP-P
VS = ±5V
RLOAD = 50
IQ PER AMPLIFIER
DISTORTION (dBc)
IQ = 5mA
IQ = 10mA
IQ = 15mA
IQ = 20mA
Third Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
Third Harmonic Distortion vs
Frequency
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100
–110 100k 1M
LT1795 G16
DISTORTION (dBc)
A
V
= 10 DIFFERENTIAL
V
OUT
= 4V
P-P
V
S
= ±12V
R
LOAD
= 50
I
Q
PER AMPLIFIER
I
Q
= 5mA
I
Q
= 20mA
I
Q
= 10mA
I
Q
= 15mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G17
AV = 2 DIFFERENTIAL
VOUT = 4VP-P
VS = ±5V
RLOAD = 50
IQ PER AMPLIFIER
DISTORTION (dBc)
IQ = 5mA
IQ = 10mA
IQ = 15mA
IQ = 20mA
FREQUENCY (Hz)
10k
–40
–50
–60
–70
–80
–90
–100 100k 1M
LT1795 G18
A
V
= 2 DIFFERENTIAL
V
OUT
= 4V
P-P
V
S
= ±5V
R
LOAD
= 50
I
Q
PER AMPLIFIER
DISTORTION (dBc)
I
Q
= 5mA
I
Q
= 10mA
I
Q
= 15mA
I
Q
= 20mA
SUPPLY CURRENT PER AMPLIFIER (mA)
7.5
SLEW RATE (V/µs)
20 30
1795 • G21
10 15 25
1200
1000
800
600
400
200
0
RISING
FALLING
VS = ±15V
TA =25°C
AV = 4
RLOAD = 25
RF = 1k
–3dB Bandwidth vs
Supply Current
SUPPLY CURRENT PER AMPLIFIER (mA)
7.5
25
–3dB BANDWIDTH (MHz)
30
40
45
50
20 30
1795 • G22
35
10 15 25
VS = ±15V
TA =25°C
AV = 4
RLOAD = 25
RF = 1k
Slew Rate vs Supply Current
7
LT1795
1795fa
APPLICATIO S I FOR ATIO
WUU U
The LT1795 is a dual current feedback amplifier with high
output current drive capability. The amplifier is designed
to drive low impedance loads such as twisted-pair trans-
mission lines with excellent linearity.
SHUTDOWN/CURRENT SET
If the shutdown/current set feature is not used, connect
SHDN to V
+
and SHDNREF to ground.
The SHDN and SHDNREF pins control the biasing of the
two amplifiers. The pins can be used to either turn off the
amplifiers completely, reducing the quiescent current to
less then 200µA, or to control the quiescent current in
normal operation.
When V
SHDN
= V
SHDNREF
, the device is shut down. The
device will interface directly with 3V or 5V CMOS logic
when SHDNREF is grounded and the control signal is
applied to the SHDN pin. Switching time between the
active and shutdown states is about 1.5µs.
Figures 1 to 4 illustrate how the SHDN and SHDNREF pins
can be used to reduce the amplifier quiescent current. In
both cases, an external resistor is used to set the current.
The two approaches are equivalent, however the required
resistor values are different. The quiescent current will be
approximately 115 times the current in the SHDN pin and
230 times the current in the SHDNREF pin. The voltage
across the resistor in either condition is V
+
– 1.5V. For
example, a 50k resistor between V
+
and SHDN will set the
Figure 1. RSHDN Connected Between V + and SHDN (Pin 10);
SHDNREF (Pin 11) = GND. See Figure 2
Figure 2. LT1795 Amplifier Supply Current vs RSHDN. RSHDN
Connected Between V+ and SHDN, SHDNREF = GND (See
Figure 1)
10 SHDN
R
SHDN
V
+
11 SHDNREF
1795 F01
R
SHDN
(k)
0 25 50 75 100 125 150 175 200 225
AMPLIFIER SUPPLY CURRENT,
I
SY
– mA (BOTH AMPLIFIERS)
1795 F02
80
70
60
50
40
30
20
10
0
T
A
= 25°C
V
S
= ±15V
Figure 4. LT1795 Amplifier Supply Current vs RSHDNREF.
RSHDNREF Connected Between SHDNREF and GND,
SHDN = V+ (See Figure 3)
R
SHDNREF
(k)
50 100 150 200 250 300 350 400 450 500
AMPLIFIER SUPPLY CURRENT,
I
SY
– mA (BOTH AMPLIFIERS)
1795 F04
80
70
60
50
40
30
20
10
0
T
A
= 25°C
V
S
= ±15V
Figure 3. RSHDNREF Connected Between SHDNREF (Pin 11)
and GND; SHDN (Pin 10) = V+. See Figure 4
10 SHDN
V
+
11 SHDNREF
1795 F03
R
SHDNREF
8
LT1795
1795fa
APPLICATIO S I FOR ATIO
WUU U
Figure 5. Setting Amplifier Supply Current
Level with ON/OFF Control, Version 1
Figure 6. Setting Multiple Amplifier Supply
Current Levels with ON/OFF Control, Version 2
10 SHDN INTERNAL
LOGIC THRESHOLD
~1.4V
R
SHDN
V
+
11 SHDNREF
1795 F05
R
B
10k Q1
OFF
(0V)
ON
(3.3V/5V)
Q1: 2N3904 OR EQUIVALENT
10 SHDN
R
PULLUP
>500k
R
SHDN2
V
+
11 SHDNREF
1795 F06
R
B2
10k Q1B
ON
OFF
R
B1
10k Q1A
ON
OFF
Q1A, Q1B: ROHM IMX1 or FMG4A (W/INTERNAL R
B
)
R
SHDN1
(3.3V/5V)(3.3V/5V)
(0V) (0V)
Figure 7. Setting Amplifier Supply Current Level
with ON/OFF Control, Version 3
10
SHDN
R
EXT
11
SHDNREF
1795 F07
ON
OFF
I
SY
CONTROL
INTERNAL
LOGIC THRESHOLD
~ 1.4V
I
PROG
0.5mA
FOR R
EXT
= 0
(SEE SHDN PIN
CURRENT vs
VOLTAGE
CHARACTERISTIC)
(3.3V/5V)
(0V) I
PROG
Figure 8. Partial Shutdown
10
SHDN
R1
R2
11
SHDNREF
1795 F08
ON
OFF
I
SY
CONTROL
INTERNAL
LOGIC THRESHOLD
~ 1.4V
(3.3V/5V)
(0V)
V
CC
Figure 8 illustrates a partial shutdown with direct logic
control. By keeping the output stage slightly biased on, the
output impedance remains low, preserving the line termi-
nation. The design equations are:
RV
II
RVV
VVI I I
H
S
ON SOFF
CC SHDN
SHDN H S ON SOFF SOFF
1115
2115
=
() ()
=
()
( ) () ()
+
()
•–
/•
where
V
H
= Logic High Level
(I
S
)
ON
= Supply Current Fully On
(I
S
)
OFF
= Supply Current Partially On
V
SHDN
= Shutdown Pin Voltage 1.4V
V
CC
= Positive Supply Voltage
THERMAL CONSIDERATIONS
The LT1795 contains a thermal shutdown feature that
protects against excessive internal (junction) temperature.
If the junction temperature of the device exceeds the
protection threshold, the device will begin cycling between
normal operation and an off state. The cycling is not
harmful to the part. The thermal cycling occurs at a slow
rate, typically 10ms to several seconds, which depends on
the power dissipation and the thermal time constants of the
package and heat sinking. Raising the ambient tempera-
quiescent current to 33mA with V
S
= ±15V. If ON/OFF
control is desired in addition to reduced quiescent current,
then the circuits in Figures 5 to 7 can be employed.
9
LT1795
1795fa
APPLICATIO S I FOR ATIO
WUU U
ture until the device begins thermal shutdown gives a
good indication of how much margin there is in the
thermal design.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. For the TSSOP package, power is
dissipated through the exposed heatsink. For the SO
package, power is dissipated from the package primarily
through the V
pins (4 to 7 and 14 to 17). These pins
should have a good thermal connection to a copper plane,
either by direct contact or by plated through holes. The
copper plane may be an internal or external layer. The
thermal resistance, junction-to-ambient will depend on
the total copper area connected to the device. For example,
the thermal resistance of the LT1795 connected to a 2 × 2
inch, double sided 2 oz copper plane is 40°C/W.
CALCULATING JUNCTION TEMPERATURE
The junction temperature can be calculated from the
equation:
T
J
= (P
D
)(θ
JA
) + T
A
where
T
J
= Junction Temperature
T
A
= Ambient Temperature
P
D
= Device Dissipation
θ
JA
= Thermal Resistance (Junction-to-Ambient)
Differential Input Signal Swing
The differential input swing is limited to about ±5V by an
ESD protection device connected between the inputs. In
normal operation, the differential voltage between the
input pins is small, so this clamp has no effect. However,
in the shutdown mode, the differential swing can be the
same as the input swing. The clamp voltage will then set
the maximum allowable input voltage.
POWER SUPPLY BYPASSING
To obtain the maximum output and the minimum distor-
tion from the LT1795, the power supply rails should be
well bypassed. For example, with the output stage supply-
ing 0.5A current peaks into the load, a 1 power supply
impedance will cause a droop of 0.5V, reducing the
available output swing by that amount. Surface mount
tantalum and ceramic capacitors make excellent low ESR
bypass elements when placed close to the chip. For
frequencies above 100kHz, use 1µF and 100nF ceramic
capacitors. If significant power must be delivered below
100kHz, capacitive reactance becomes the limiting factor.
Larger ceramic or tantalum capacitors, such as 4.7µF, are
recommended in place of the 1µF unit mentioned above.
Inadequate bypassing is evidenced by reduced output
swing and “distorted” clipping effects when the output is
driven to the rails. If this is observed, check the supply pins
of the device for ripple directly related to the output
waveform. Significant supply modulation indicates poor
bypassing.
Capacitance on the Inverting Input
Current feedback amplifiers require resistive feedback
from the output to the inverting input for stable operation.
Take care to minimize the stray capacitance between the
output and the inverting input. Capacitance on the invert-
ing input to ground will cause peaking in the frequency
response (and overshoot in the transient response), but it
does not degrade the stability of the amplifier.
Feedback Resistor Selection
The optimum value for the feedback resistors is a function
of the operating conditions of the device, the load imped-
ance and the desired flatness of response. The Typical AC
Performance tables give the values which result in less
than 1dB of peaking for various resistive loads and oper-
ating conditions. If this level of flatness is not required, a
higher bandwidth can be obtained by use of a lower
feedback resistor.
For resistive loads, the COMP pin should be left open (see
Capacitive Loads section).
Capacitive Loads
The LT1795 includes an optional compensation network
for driving capacitive loads. This network eliminates most
of the output stage peaking associated with capacitive
loads, allowing the frequency response to be flattened.
10
LT1795
1795fa
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
Figure 9 shows the effect of the network on a 200pF load.
Without the optional compensation, there is a 6dB peak at
85MHz caused by the effect of the capacitance on the
output stage. Adding a 0.01µF bypass capacitor between
the output and the COMP pins connects the compensation
APPLICATIONS INFORMATION
WUU U
Figure 9
FREQUENCY (MHz)
1
VOLTAGE GAIN (dB)
14
12
10
8
6
4
2
0
–2
–4
–6 10 100
1795 F09
V
S
= ±15V
C
L
= 200pF
R
F
= 3.4k
NO
COMPENSATION
R
F
= 1k
COMPENSATION
R
F
= 3.4k
COMPENSATION
PACKAGE DESCRIPTIO
U
and greatly reduces the peaking. A lower value feedback
resistor can now be used, resulting in a response which is
flat to ±1dB to 45MHz. The network has the greatest effect
for C
L
in the range of 0pF to 1000pF.
Although the optional compensation works well with
capacitive loads, it simply reduces the bandwidth when it
is connected with resistive loads. For instance, with a 25
load, the bandwidth drops from 48MHz to 32MHz when
the compensation is connected. Hence, the compensation
was made optional. To disconnect the optional compensa-
tion, leave the COMP pin open.
DEMO BOARD
A demo board (DC261A) is available for evaluating the
performence of the LT1795. The board is configured as a
differential line driver/receiver suitable for xDSL applica-
tions. For details, consult your local sales representative.
S20 (WIDE) 0502
NOTE 3
.496 – .512
(12.598 – 13.005)
NOTE 4
20
N
19 18 17 16 15 14 13
12345678
.394 – .419
(10.007 – 10.643)
910
N/2
1112
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330) .016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
1 2 3 N/2
.050 BSC
.030 ±.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
11
LT1795
1795fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
FE20 (CA) TSSOP 0203
0.09 – 0.20
(.0036 – .0079)
0° – 8°
RECOMMENDED SOLDER PAD LAYOUT
0.45 – 0.75
(.018 – .030)
4.30 – 4.50*
(.169 – .177)
6.40
BSC
134
5
6
7
8910
111214 13
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.95
(.195)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
12
LT1795
1795fa
PART NUMBER DESCRIPTION COMMENTS
LT1497 Dual 125mA, 50MHz Current Feedback Amplifier 900V/µs Slew Rate
LT1207 Dual 250mA, 60MHz Current Feedback Amplifier Shutdown/Current Set Function
LT1886 Dual 200mA, 700MHz Voltage Feedback Amplifier Low Distortion: –72dBc at 200kHz
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1999
LT/TP 0603 1K REVA • PRINTED IN USA
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V+
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V
CCRCCOMP–IN+IN
SHDN
SHDNREF
TO ALL
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SOURCES
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