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FEATURES
APPLICATIONS
1
2
3
4
8
7
6
5
DIN
SCLK
CS
OUTA
VDD
OUTB
REF
AGND
D, JG PACKAGE
(TOP VIEW)
192013 2
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
OUTB
NC
REF
NC
NC
SCLK
NC
CS
NC
NC
DIN
NC
NC
OUTA
NC
AGND
NC
NC
FK PACKAGE
(TOP VIEW)
DD
V
DESCRIPTION
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITHINTERNAL REFERENCE AND POWER DOWN
•Dual 12-Bit Voltage Output DAC•Programmable Internal Reference•Programmable Settling Time:– 1 µs in Fast Mode,– 3.5 µs in Slow Mode•Compatible With TMS320 and SPI™ SerialPorts
•Differential Nonlinearity <0.5 LSB Typ•Monotonic Over Temperature
•Digital Servo Control Loops•Digital Offset and Gain Adjustment•Industrial Process Control•Machine and Motion Control Devices•Mass Storage Devices
The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allowsglueless interface to TMS320, SPI™, QSPI™, and Microwire™ serial ports. It is programmed with a 16-bit serialstring containing 4 control and 12 data bits.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class ABoutput stage to improve stability and reduce settling time. The programmable settling time of the DAC allows thedesigner to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, theTLV5638 simplifies overall system design.
Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implementedwith a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an8-pin SOIC package to reduce board space in standard commercial, industrial, and automotive temperatureranges. It is also available in JG and FK packages in the military temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI, QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Serial
Interface
and
Control
12-Bit
DAC B
Latch
SCLK
DIN
CS
OUTA
Power-On
Reset
x2
12
2-Bit
Control
Latch
Power
and Speed
Control
2
Voltage
Bandgap
PGA With
Output Enable
12-Bit
DAC A
Latch
12
REF AGND VDD
2
12 12
OUTB
x2
Buffer
12
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
AVAILABLE OPTIONS
PACKAGET
A
SOIC CERAMIC DIP 20 PAD LCCC(D) (JG) (FK)
0°C to 70°C TLV5638CD — —40°C to 85°C TLV5638ID — —TLV5638QD40°C to 125°C — —TLV5638QDR55°C to 125°C — TLV5638MJG TLV5638MFK
FUNCTIONAL BLOCK DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
Terminal Functions
TERMINAL
I/O/P DESCRIPTIONNAME NO.
AGND 5 P GroundCS 3 I Chip select. Digital input active low, used to enable/disable inputsDIN 1 I Digital serial data inputOUT A 4 O DAC A analog voltage outputOUT B 7 O DAC B analog voltage outputREF 6 I/O Analog reference voltage input/outputSCLK 2 I Digital serial clock inputV
DD
8 P Positive power supply
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage (V
DD
to AGND) 7 VReference input voltage range -0.3 V to V
DD
+ 0.3 VDigital input voltage range -0.3 V to V
DD
+ 0.3 VOperating free-air temperature range, T
A
TLV5638C 0°C to 70°CTLV5638I -40°C to 85°CTLV5638Q -40°C to 125°CTLV5638M -55°C to 125°CStorage temperature range, T
stg
-65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under, , absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under, , recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
≤25°C DERATING FACTOR T
A
= 70°C T
A
= 85°C T
A
= 125°CPACKAGE
POWER RATING ABOVE T
A
= 25°C
(1)
POWER RATING POWER RATING POWER RATING
D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mWFK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mWJG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW
(1) This is the inverse of the traditional Junction-to-Ambient thermal Resistance (R θ
JA
). Thermal Resistances are not production tested andare for informational purposes only.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
MIN NOM MAX UNIT
V
DD
= 5 V 4.5 5 5.5 VSupply voltage, V
DD
V
DD
= 3 V 2.7 3 3.3 VPower on reset, POR 0.55
(1)
2
(1)
VV
DD
= 2.7 V 2 VHigh-level digital input voltage, V
IH
V
DD
= 5.5 V 2.4V
DD
= 2.7 V 0.6 VLow-level digital input voltage, V
IL
TLV5638C and TLV5638I 1V
DD
= 5.5 V VTLV5638Q and TLV5638M 0.8Reference voltage, V
ref
to REF terminal V
DD
= 5 V
(2)
AGND 2.048 V
DD
-1.5 VReference voltage, V
ref
to REF terminal V
DD
= 3 V
(2)
AGND 1.024 V
DD
-1.5 VLoad resistance, R
L
2 k ΩLoad capacitance, C
L
100 pFClock frequency, f
CLK
20 MHzTLV5638C 0 70TLV5638I 40 85Operating free-air temperature, T
A
°CTLV5638Q 40 125TLV5638M 55 125
(1) This parameter is not tested for Q and M suffix devices.(2) Due to the x2 output buffer, a reference input voltage ≥(V
DD
-0.4 V)/2 causes clipping of the transfer function. The output buffer of theinternal reference must be disabled, if an external reference is used.
over recommended operating conditions, V
ref
= 2.048 V, V
ref
= 1.024 V (unless otherwise noted)
POWER SUPPLY
TLV5638C, ITLV5638MPARAMETER TEST CONDITIONS UNITMIN TYP MAX
Fast 4.3 7V
DD
= 5 V,
mAInt. ref.
Slow 2.2 3.6Fast 3.8 6.3V
DD
= 3 V,
mANo load,
Int. ref.
Slow 1.8 3.0I
DD
Power supply current All inputs = AGND or V
DD
,
Fast 3.9 6.3V
DD
= 5 V,DAC latch = 0x800
mAExt. ref.
Slow 1.8 3.0Fast 3.5 5.7V
DD
= 3 V,
mAExt. ref.
Slow 1.5 2.6Power-down supply current 0.01 10 µAZero scale,
(1)
65PSRR Power supply rejection ratio dBFull scale,
(2)
65
(1) Power supply rejection ratio at zero scale is measured by varying V
DD
and is given by: PSRR = 20 log [(E
ZS
(V
DD
max) -E
ZS
(V
DD
min))/V
DD
max](2) Power supply rejection ratio at full scale is measured by varying V
DD
and is given by: PSRR = 20 log [(E
G
(V
DD
max) -E
G
(V
DD
min))/V
DD
max]
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ELECTRICAL CHARACTERISTICS (Continued)
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
over recommended operating conditions, V
ref
= 2.048 V, V
ref
= 1.024 V (unless otherwise noted)
STATIC DAC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 bitsC and I
±1.7 ±4 LSBsuffixesIntegral nonlinearity, end point ad-INL See
(1)justed
Q and M
±1.7 ±6 LSBsuffixesDNL Differential nonlinearity See
(2)
±0.4 ±1 LSBZero-scale error (offset error at zeroE
ZS
See
(3)
±24 mVscale)
Zero-scale-error temperature coef-E
ZS
TC See
(4)
10 ppm/°Cficient
% fullE
G
Gain error See
(5)
±0.6
scale VE
G
T
C
Gain error temperature coefficient See
(6)
10 ppm/°C
OUTPUT SPECIFICATIONS
V
O
Output voltage R
L
= 10 k Ω0 V
DD
-0.4 V% fullOutput load regulation accuracy V
O
= 4.096 V, 2.048 V, R
L
= 2 k Ω±0.25
scale V
REFERENCE PIN CONFIGURED AS OUTPUT (REF)
Vref(OUTL) Low reference voltage 1.003 1.024 1.045 VVref(OUTH) High reference voltage V
DD
> 4.75 V 2.027 2.048 2.069 VIref(source) Output source current 1 mAIref(sink) Output sink current -1 mALoad capacitance 100 pFPSRR Power supply rejection ratio -65 dB
REFERENCE PIN CONFIGURED AS INPUT (REF)
V
I
Input voltage 0 V
DD
-1.5 VR
I
Input resistance 10 M ΩC
I
Input capacitance 5 pFFast 1.3 MHzReference input bandwidth REF = 0.2 V
pp
+ 1.024 V dc
Slow 525 kHzReference feedthrough REF = 1 V
pp
at 1.024 V dc
(7)
-80 dB
DIGITAL INPUTS
I
IH
HIgh-level digital input current V
I
= V
DD
1 µAI
IL
Low-level digital input current V
I
= 0 V -1 µAC
i
Input capacitance 8 pF
(1) The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output fromthe line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.(2) The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSBamplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)as a change in the digital input code.(3) Zero-scale error is the deviation from zero voltage output when the digital input code is zero.(4) Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
ZS
(T
max
)-E
ZS
(T
min
)]/V
ref
× 10
6
/(T
max
- T
min
).(5) Gain error is the deviation from the ideal output (2V
ref
- 1 LSB) with an output load of 10 k Ωexcluding the effects of the zero-error.(6) Gain temperature coefficient is given by: E
G
TC = [E
G
(T
max
)-E
G
(T
min
)]/V
ref
× 10
6
/(T
max
- T
min
).(7) Reference feedthrough is measured at the DAC output with an input code = 0x000.
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ELECTRICAL CHARACTERISTICS (Continued)
DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER MEASURMENT INFORMATION
twL
SCLK
CS
DIN D15 D14 D13 D12 D1 D0 XX
1
X2 3 4 5 15 16 X
twH
tsu(D) th(D)
tsu(CS-CK)
tsu(C16-CS)
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
over recommended operating conditions, V
ref
= 2.048 V, V
ref
= 1.024 V (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fast 1 3t
s(FS)
Output settling time, full scale R
L
= 10 k Ω, C
L
= 100 pF, See
(1)
µsSlow 3.5 7Fast 0.5 1.5t
s(CC)
Output settling time, code to code R
L
= 10 k Ω, C
L
= 100 pF, See
(2)
µsSlow 1 2Fast 12SR Slew rate R
L
= 10 k Ω, C
L
= 100 pF, See
(3)
V/µsSlow 1.8Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = V
DD
5 nV-sSNR Signal-to-noise ratio 69 74S/(N+D) Signal-to-noise + distortion 58 67f
s
= 480 kSPS, f
out
= 1 kHz, R
L
= 10 k Ω,
dBC
L
= 100 pFTHD Total harmonic distortion 69 57Spurious free dynamic range 57 72
(1) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.(2) Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change ofone count. Not tested, assured by design.(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
MIN NOM MAX UNIT
t
su(CS-CK)
Setup time, CS low before first negative SCLK edge 10 nst
su(C16-CS)
Setup time, 16
th
negative SCLK edge (when D0 is sampled) before CS rising edge 10 nst
wH
SCLK pulse width high 25 nst
wL
SCLK pulse width low 25 nst
su(D)
Setup time, data ready before SCLK falling edge 10 nst
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
2.5
2
1.5
0.5
–40 –30–20 –10 0 10 20
3.5
4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
30 50 60 90
3
1
40 70 80
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = Full Scale (Both DACs)
– Supply Current – mAIDD
TA – Free-Air Temperature – °C
1.4
1
0.4
00 10 20 30 40
– Power Down Supply Current – mA
2.2
2.4
POWER DOWN SUPPLY CURRENT
vs
TIME
2.6
50 60 70 80
2
1.8
1.6
1.2
0.8
0.6
0.2
t – T ime – µs
IDD
2.5
2
1.5
0.5
–40 –30–20 –10 0 10 20
3.5
4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
30 50 60 90
3
1
40 70 80
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = Full Scale (Both DACs)
– Supply Current – mAIDD
TA – Free-Air Temperature – °C
2.058
2.054
2.052
2.05 0 0.5 1 1.5 2 2.5 3
– Output Voltage – V
2.06
2.062
Source Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.064
3.5 4
2.056
VO
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 4095
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
Figure 2. Figure 3.
Figure 4. Figure 5.
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4.122
4.12
4.116
4.114 0 0.5 1 1.5 2 2.5 3
4.124
4.126
4.128
3.5 4
4.118
– Output Voltage – V
Source Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 4095
3.5
2
1
00 0.5 1 1.5 2 2.5 3
4
4.5
5
3.5 4
3
2.5
1.5
0.5
– Output Voltage – V
Sink Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 0
–40
–50
–80
–100
100 1000
THD+N – Total Harmonic Distortion and Noise – dB
–20
–10
f – Frequency – Hz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
10000 100000
–30
–60
–70
–90
Fast Mode
Slow Mode
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
Figure 6. Figure 7.
Figure 8. Figure 9.
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–40
–50
–80
–100
100 1000
THD – Total Harmonic Distortion – dB
–20
–10
f – Frequency – Hz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
10000 100000
–30
–60
–70
–90 Fast Mode
Slow Mode
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
–1
–4 0 1024 2048
2
3
INTEGRAL NONLINEARITY ERROR
4
3072 4096
INL – Integral Nonlinearity Error – LSB
Digital Code
1
0
–2
–3
–0.4
–10 1024 2048
0.6
0.8
DIFFERENTIAL NONLINEARITY ERROR
1
3072 4096
0.4
0.2
0
–0.2
–0.6
–0.8
DNL – Differential Nonlinearily Error – LSB
Digital Code
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
Figure 10.
Figure 11.
Figure 12.
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APPLICATION INFORMATION
GENERAL FUNCTION
2 REF CODE
0x1000 [V]
SERIAL INTERFACE
TMS320
DSP FSX
CLKX
DX
TLV5638
SCLK
DIN
CS SPI I/O
SCK
MOSI
TLV5638
SCLK
DIN
CS Microwire
I/O
SK
SO
TLV5638
SCLK
DIN
CS
SERIAL CLOCK FREQUENCY AND UPDATE RATE
fsclkmax 1
twhmin twlmin 20 MHz
fupdatemax 1
16 twhmin twlmin1.25 MHz
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serialinterface, a speed and power-down control logic, a programmable internal reference, a resistor string, and arail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A poweron reset initially puts the internal latches to a defined state (all bits zero).
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the fallingedges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to thetarget latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI™, and Microwire™.
Figure 13. Three-Wire Interface
Notes on SPI™ and Microwire™: Before the controller starts the data transfer, the software has to generate afalling edge on the pin connected to CS. If the word width is 8 bits (SPI™ and Microwire™), two write operationsmust be performed to program the TLV5638. After the write operation(s), the holding registers or the controlregister are updated automatically on the 16
th
positive clock edge.
The maximum serial clock frequency is given by:
The maximum update rate is:
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of theTLV5638 has to be considered, too.
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DATA FORMAT
REGISTERED SELECT BITS
DATA BITS: DAC A, DAC B and BUFFER
DATA BITS: CONTROL
REFERENCE BITS
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
APPLICATION INFORMATION (continued)
The 16-bit data word for the TLV5638 consists of two parts:•Program bits (D15..D12)•New data (D11..D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R1 SPD PWR R0 12 Data bits
SPD: Speed control bit 1 →fast mode 0 →slow modePWR: Power control bit 1 →power down 0 →normal operation
The following table lists the possible combination of the register select bits:
R1 R0 REGISTER
0 0 Write data to DAC B and BUFFER0 1 Write data to BUFFER1 0 Write data to DAC A and update DAC B with BUFFER content1 1 Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,then the 12 data bits determine the new DAC value:
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
New DAC Value
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X X X X X REF1 REF0
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
REF1 REF0 REFERENCE
0 0 External0 1 1.024 V1 0 2.048 V1 1 External
CAUTION:
If external reference voltage is applied to the REF pin, external reference MUSTbe selected.
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EXAMPLES OF OPERATION:
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
1. Set DAC A output, select fast mode, select internal reference at 2.048 V:a. Set reference voltage to 2.048 V (CONTROL register)D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0
b. Write new DAC A value and update DAC A output:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 New DAC A output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program theCONTROL register again.2. Set DAC B output, select fast mode, select external reference:a. Select external reference (CONTROL register):D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
b. Write new DAC B value to BUFFER and update DAC B output:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 New BUFFER content and DAC B output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program theCONTROL register again.3. Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal referenceat 1.024 V:a. Set reference voltage to 1.024 V (CONTROL register)D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
b. Write data for DAC B to BUFFER:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 1 New DAC B value
c. Write new DAC A value and update DAC A and B simultaneously:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 New DAC A value
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program theCONTROL register again.1. Set power-down mode:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X 1 X X X X X X X X X X X X X
X = Don't care
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LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES
DAC Code
Output
Voltage
0 V
Negative
Offset
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. Witha positive offset, the output voltage changes on the first code change. With a negative offset, the output voltagemay not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage toovercome the negative offset voltage, resulting in the transfer function shown in Figure 14 .
Figure 14. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed thedotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) afteroffset and full scale are adjusted out or accounted for in some way. However, single supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity ismeasured between full-scale code and the lowest code that produces a positive output voltage.
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DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error (E
ZS
)
Gain Error (E
G
)
Total Harmonic Distortion (THD)
Signal-to-Noise Ratio + Distortion (S/N+D)
Spurious Free Dynamic Range (SFDR)
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximumdeviation of the output from the line between zero and full scale excluding the effects of zero code and full-scaleerrors.
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between themeasured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltagechanges in the same direction (or remains constant) as a change in the digital input code.
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
Gain error is the error in slope of the DAC transfer function.
THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. Thevalue for THD is expressed in decibels.
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below theNyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value ofthe largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
14
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9957601Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9957601QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
TLV5638CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV5638MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLV5638QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 2
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5638, TLV5638M :
•Catalog: TLV5638
•Enhanced Product: TLV5638-EP, TLV5638-EP
•Military: TLV5638M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5638CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV5638IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV5638QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5638CDR SOIC D 8 2500 367.0 367.0 35.0
TLV5638IDR SOIC D 8 2500 367.0 367.0 35.0
TLV5638QDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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