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L9638
October 2004
1 FEATURES
■Single-wire transceiver for LIN-protocol
■Transmission rate up to 20 kbaud
■Operating power supply voltage range 6V ≤ Vs
≤ 26V (40V for transients)
■Low quiescent current in sleep mode (typ.10µA)
■Wake-up through LIN-bus, Enable input (from
µC CMOS compatible) or Wake-up input (edge
driven)
■Wide input and output range -24V ≤ VLIN ≤ Vs
■Integrated pull/down/up resistors for LIN, TxD,
RxD, EN, INH
■Inhibit output with low resistance (<40Ω) versus
Vs and short circuit protection
■CMOS compatible TxD, RxD Interface
■EMI robustness optimised
■Thermal shutdown and LIN short circuit
protection
2 DESCRIPTION
The L9638 is a monolithic integrated circuit for
LIN-bus interface function between the protocol
handler in the controller and the physical bus in
automotive applications.
As well as it can be used in standard ISO 9141
systems.
SO-8
LIN BUS TRANSCEIVER
Figure 1. Block Diagram
VS
TxD
WUP
RxD LIN
INH
EN
Internal
Voltage
Regulator
Int.5V
GND
Glitch
Filter
Glitch
Filter
VS_D
Control
Logic
Protection
VS_D
VS
TxD
WUP
RxD LIN
INH
EN
Internal
Voltage
Regulator
Int.5V
GND
Glitch
Filter
VS
TxD
WUP
RxD LIN
INH
EN
Internal
Voltage
Regulator
Int.5V
GND
Glitch
Filter
Glitch
Filter
VS_D
Control
Logic
Protection
VS_D
T
a
bl
e 1.
O
r
d
er
C
o
d
es
Part Number Package
L9638D SO-8
L9638D013TR Tape & Reel
Rev. 4
L9638
2/14
Table 2. Pin Description
Figure 2. Pin Connection
Table 3. Absolute Maximum Ratings
Table 4. Thermal Data
Pin No. Pin Name Function
1 RxD Receive data Output
2 EN Enable Input
Digital control signal for low power modes
3 WUP Wake-Up Input
Local wake-up from sleep mode sensitive to positive and negative edges
4 TxD Transmit data Input
5 GND Ground
6 LIN Bidirectional I/O
7 Vs Supply voltage
8 INH Inhibit Output, battery related high side switch for controlling external Voltage
Regulator
Symbol Parameter Value Unit
VSSupply Voltage -0.3 to 40 V
VLIM Pin Voltage -24 to 40 V
VINH ,WUP Pin Voltage -0.3 to 40 V
VRxD ,TxD, EN Pin Voltage -0.3 to 6 V
VESD HBM: all pins withstand ±2KV; pin 6 (LIN) is able to withstand
±8kV versus GND and +8/-5kV versus VS
Symbol Parameter Value Unit
TJ_OP Operating junction temperature -40 to150 °C
Rth j-amb Thermal steady state junction to ambient resistance 145 K/W
TJ_SD Thermal shutdown temperature 170 ±20 °C
Tstg Storage temperature -55 to 150 °C
RxD
EN
WUP
TxD GND
LIN
Vs
INH1
3
2
4
6
5
7
8
D04AT514
3/14
L9638
Table 5. Electrical Characteristics
(VS = 6V to 26V; TJ = -40 to 150 °C unless otherwise specified)
Item Symbol Parameter Test Condition Min. Typ. Max. Unit
1Supplies
1.1 VSSupply Voltage 6 26 V
1.2 ISleep Supply Vs Curent in sleep
mode
VEN = VEN low 10 30 µA
1.3 IShort Supply Vs Curent with bus
short circuit
VEN = VEN low 150 500 1700 µA
1.4 IDStand-by Supply Vs Current in Stand-
by Mode with bus recessive
VLIN = VLINHigh
VEN = VENLow
VTxD = VTxDHigh
30 100 200 µA
1.5 IDStand-by Supply Vs Current in Stand-
by Mode with bus dominant
(Receive only Mode)
VLIN = VLINLow
VEN = VENLow
0.5 1.1 2.5 mA
1.6 IsNormal Supply Vs Current in
Normal Mode with bus
recessive
VEN = VENHigh
VLIN = VLINHigh
VTxD = VTxDHigh
300 500 700 µA
1.7 IsNormal Supply Vs Current in
Normal Mode with bus
dominant
VEN = VENHigh
VLIN = VLINLow
VTxD = VTxDLow
0.9 1.8 3.5 mA
2LIN Bus Interface
2.1 VBUSDom Receive Threshold Voltage
recessive to dominant state
VLIN<18V 0.40.450.5 Vs
2.2 VBUSRec Receive Threshold Voltage
dominant to recessive state
VLIN ≥8V 0.50.550.6 Vs
2.3 VHYS Receive Threshold
Hysteresis
VBUSRec-VBUSDom 0.05 0.1 0.17 Vs
2.4 VBUScnt Tolerance centre value of
Receiver
(VBUSRec+VBUSDom)/2 0.475 0.5 0.525 Vs
2.5 ILINON Input Current dominant
state
VTxD = VTxDLow
VLIN = VS
40 100 160 mA
2.5.1 ILINOff Input Current recessive
state
VTxD = VTxDHigh
VLIN = Vs
-10 10 µA
2.5.2 ILINOff Input Current recessive
state
VTxD = VTxDHigh; VS = 12V;
VLIN = 0V (Bus dominant )
-1 mA
2.6 VLINDom Drive Voltage dominant
state
VTxD = VTxDLow
ILIN = 40mA
1.2 V
2.7 RLIN Output pull up resistor 20 30 47 kΩ
2.8 fLIN-RxD Transmission Frequency RVs-LIN =1100Ω
CLIN-GND =10nF
20 kHz
2.9 dVLIN/dt Slew rate rising edge From 10% to 90% of VLIN 123V/µs
L9638
4/14
2.10 dVLIN/dt Slew rate falling edge From 90% to 10% of VLIN -3 -2 -1 V/µs
2.11 tsym Rising/ Falling edge
symmetry
tsym= tslope_fall - tslope_rise -5 -5 µs
2.12 ttrans_pd Propagation delay of
transmitter
See Fig.2
ttrans_pd = max (ttrans_pdr,
trans_pdf)
4µs
2.13 trec_pd Propagation delay of
receiver
See Fig.2
trec_pd = max (trec_pdr, trec_pdf)
6µs
2.14 trec_sym Symmetry of receiver
propagation delay rising
edge w.r.t. falling edge
See Fig.2
trec_sym= (trec_pdf -trec_pdr)
-2 2 µs
2.15 ttrans_sym Symmetry of transmitter
propagation delay rising
edge w.r.t. falling edge
See Fig.2
ttrans_sym = (ttrans_pdf -ttrans_pdr)
-2 2 µs
2.16 tLINgs Bus wake-up glitch
suppression time
See Fig.3 VLIN = VLINLow 40 100 µs
3Transmission Input TxD
3.1 VTxDLow Input Voltage dominant
state
1.5 V
3.2 VTxDHigh Input Voltage recessive
state
3.5 V
3.3 RTxD TxD pull up resistor 5 10 25 KΩ
4Receive Output RxD
4.1 VRxDLow Output Voltage dominant
state
IRxD = 2mA 1.5 V
4.2 VRxDHigh Output Voltage recessive
state
IRxD≥10µA4.5V
4.3 RRxD RxD pull up resistor 5 10 25 kΩ
5Inhibit Output INH
5.1 RON(INH) Switch on resistance
between Vs and INH
IINH=-15mA; Vs=13.5V 20 40 Ω
5.2 ION(INH) INH output current Normal or stand-by mode 15 30 50 mA
5.3 ROFF(INH) Switch off INH pull down
resistor
51025kΩ
6Wake Up Input WUP
6.1 VWUPLow Low level input voltage 1.5 V
6.2 VWUPHigh High level input voltage 3.5 Vs+0.
3
V
Table 5. Electrical Characteristics (continued)
(VS = 6V to 26V; TJ = -40 to 150 °C unless otherwise specified)
Item Symbol Parameter Test Condition Min. Typ. Max. Unit
5/14
L9638
Note: 1. Room temperature evaluated - no 100% tested
6.3 tWUPgs Remote wake-up delay time Transitioning on WUP 40 100 µs
7Enable Input EN
7.1 VENLow Low level input voltage 1.5 V
7.2 VENHigh High level input voltage 3.5 V
7.3 REN EN pull down resistor 5 10 25 KΩ
7.4 tgts Go to sleep delay time VEN = VENlow 40 100 µs
7.5 tENgs EN wake-up glitch
suppression time
VEN = VENhigh 40 100 µs
8AC Timing Parameters
8.1 D1 Duty Cycle 1 THRec(max) = 0.744 x VSUP;
THDom(max) = 0.581 x VSUP;
Vsup = 7.0 to 18V; tbit = 50µs;
D1 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.396
8.2 D2 Duty Cycle 2 THRec(min) = 0.284 x VSUP;
THDom(min) = 0.422 x VSUP;
Vsup = 7.6 to 18V; tbit = 50µs;
D2 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.581
8.3 D3 Duty Cycle 3 THRec(max) = 0.778 x VSUP;
THDom(max) = 0.616 x VSUP;
Vsup = 7.0 to 18V; tbit = 96µs;
D3 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.417
8.4 D4 Duty Cycle 4 THRec(min) = 0.251 x VSUP;
THDom(min) = 0.389 x VSUP;
Vsup = 7.6 to 18V; tbit = 96µs;
D4 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.591
9Fault Conditions
9.1 ILIN_NO_GND LIN current with GND
disconnected
GND = Vs = 12V
0V< VLIM < 18V (1)
-1 1 mA
9.2 ILIN_NO_Vs LIN current with VS
grounded
V = GND, 0V < VLIN < 18V
(1)
100 µA
Table 5. Electrical Characteristics (continued)
(VS = 6V to 26V; TJ = -40 to 150 °C unless otherwise specified)
Item Symbol Parameter Test Condition Min. Typ. Max. Unit
L9638
6/14
3 TIMING DIAGRAM
Figure 3. Definition of Bus Timing Parameters
7/14
L9638
Figure 4. Typical Bus Timing
Figure 5. Typical Wake-up Timing
t
VTxD
t
VLIN
t
VRxD
ttrans_pdf ttrans_pdr
Receive Dominant Threshold
Receive Recessive Threshold
trec_pdr
trec_pdf
90%
10%
t
VTxD
t
VLIN
t
VRxD
ttrans_pdf ttrans_pdr
Receive Dominant Threshold
Receive Recessive Threshold
trec_pdr
trec_pdf
90%
10%
VLIN
t
t<tLINgs gstLIN
VRxD
t
VINH
t
L9638
8/14
4 FUNCTIONAL DESCRIPTION
The L9638 is a monolithic bus driver designed to provide bidirectional serial communication in Local In-
terconnect Network (LIN).
In addition to the integrated physical layer (specified in LIN specification rev. 2.0), further control in- and
output functions simplify various system requirements like controlled power saving modes or additional
external wake up capability.
4.1 Operating modes
There are four possible modes of operation: normal, standby, sleep and short circuit. The transitions be-
tween the various operation modes are described in the diagram.
4.2 Standby mode
This mode is reached after power up the system or due to a received wake-up condition from sleep mode.
The device is able to receive at RxD, but could not transmit any data. This prevents the disturbance of the
LIN bus line due to a not correctly working µC. Entering the standby mode, the INH output will set to HIGH
by simultaneous switching off the internal pull down resistor to reduce the current consumption. This al-
lows the control of connected power supply devices.
Therefore for systems, that will be controlled only by the LIN bus line (particular ECUs, that works as slave
node) a power management can easy build up on that function. It is recommended to power up the sys-
tem before the communication will start, otherwise additional delay times have to be regarded.
Because of integrated filtering of external WUP input, the INH output can alternatively be used to simplify
a software filtering procedure to detect an external edge sensitive signal by connecting INH versus a se-
ries resistor to an interrupt capable input of the µC.
4.3 Normal mode
This mode can only be reached from standby or sleep mode by setting the EN input to HIGH. Transmis-
sion and receiving of data stream via the LIN line is possible. An integrated pull up resistor in series with
a diode at LIN provides either required recessive state (HIGH) as well as a protection against reverse pow-
er supply. In master node application, a LOW ohmic resistor in series with a diode has to be connected
externally between LIN and battery to allow the maximum transmission rate.
The receiver converts the battery supply related signal at LIN to a logic supply compatible output at RxD.
Integrated filter in addition with the supply voltage related threshold and hysteresis provide optimal noise
suppression.
The transmitter shifts the logic supply related data stream at TxD to battery level at LIN. A read back func-
tion is possible by evaluating the mirrored state from the LIN line at the output RxD.
4.4 Short circuit mode
The L9638 provides a special operation mode for shorted LIN bus lines to ground. In that case, the whole
LIN network is blocked. If the protocol handler in the µC detects a "time out" condition, that could be un-
ambiguously identified as a short to ground condition in the bus line, the whole LIN node could be discon-
nected from the network by setting EN input to LOW.
This will switch INH output from active HIGH to LOW. Additionally RxD output, that remains in the domi-
nant state and maybe block the µC will set to HIGH ohmic state.
The L9638 won't accept any transition at TxD. This short circuit mode will be stable until the dominant state
on LIN will be cleared. In that case, the device will switch to the sleep mode. According to that, the current
consumption of a blocked LIN network will be reduced to the resulting short circuit current in the LIN line.
Especially for sporadically happening shorts due to damaged cable isolation, the LIN network will be au-
tomatically reset. Therefore no special power up procedure is required.
9/14
L9638
4.5 Sleep mode
This mode allows the lowest current consumption of the transceiver. It'll be reached either by setting the
EN input to LOW (assuming no occurring wake-up event) while being in the normal mode or in case of a
removed short to ground at LIN while being in the short circuit mode.
The INH output will be switched from HIGH to LOW. A further transmission via TxD is prevented. The de-
vice is waiting on any wake-up requests either by LIN (dominant level) or WUP (rising or falling edge). This
will set the device from sleep mode to standby mode. An implemented filter prevents unwished wake-ups
due to occurring glitches or EMI at LIN or WUP.
4.6 Wake-up
The L9638 provides several wake-up conditions from sleep mode:
– Remote wake-up by a dominant level at LIN
– Local wake-up by a falling or rising edge at WUP
– Mode change by setting EN to HIGH
The INH output will be set from LOW to HIGH after each kind of valid wake-up conditions. For remote
wake-up via LIN, RxD will be activated and set as well to a dominant state.
This allows fast reaction for powered µC with connected interrupt capable receive inputs.
4.7 Fail-safe features
To prevent possible states, that will block the communication line in case of a failed µC operation, the
L9638 has implemented some special fail-safe features:
– After detected a clear short to ground state at the LIN pin by the protocol handler in the µC, the trans-
ceiver or the complete power supply of the ECU control logic could be switched off by setting the EN
input from HIGH to LOW. The device will stay in that special short circuit mode until the state of the
LIN bus will switch back from dominant to recessive. No power up or special reset procedures are
required to clear that fail-safe state. L9638 could be reactivated with the usual wake-up signals.
– The TxD and EN inputs support default recessive bus states by internal pull up or down sources
– The output stage of the transmitter is current limited to protect against a shorten LIN to battery
– A thermal shutdown protects the device against over temperature caused destruction. In case of a
permanent overload condition, the output stage will be switched off after reaching the shut down tem-
perature and reactivated after cooling down to the switch on temperature.
– Defined output status in under voltage, loss of Vs or GND condition with no impact to the bus line or
the connected µC
L9638
10/14
Figure 6. State Diagram
0 0 float 0 1 Vs
NORMAL
EN
WUP
WUP
EN
LIN
Power-up
1 1 float 1 1 Vs
TX
mode
RX
mode
1 0 float 0 1 Vs
1 1 float 1 1 Vs
HiZ HiZ X 0 0 0
SHORT CIRCUIT
TxD RxD WUP LIN EN INH
HiZ HiZ X 1 0 0
SLEEP
float 0 float 0 0 Vs
STANDBY
(with LIN=1)
if t(EN=0 after 1->0)
>tgts
and no wake up event
EN
EN
TxD RxD WUP LIN EN INH
TxD RxD WUP LIN EN INH
TxD RxD WUP LIN EN INH
float 1 float 1 0 Vs
X
don’t
care, input signal is stable high or low
HiZ
internal pull up is switched off;
TxD
input signal may be high or low or transitioning
RxD
output signal is high impedance.
float
input signal may be high or low or transitioning
if t(EN=1 after 0->1)
>tENgs
(with LIN=0)
if t(EN=0 after 1->0)
>tgts
if t(LIN=0 after 1->0)
>tLINgs
tdelay
=tWUPgs
if (LIN=1)
0 0 float 0 1 Vs
NORMAL
EN
WUP
WUP
EN
LIN
Power-up
1 1 float 1 1 Vs
TX
mode
RX
mode
1 0 float 0 1 Vs
1 1 float 1 1 Vs
HiZ HiZ X 0 0 0
SHORT CIRCUIT
TxD RxD WUP LIN EN INH
HiZ HiZ X 1 0 0
SLEEP
float 0 float 0 0 Vs
STANDBY
(with LIN=1)
if t(EN=0 after 1->0)
>tgts
and no wake up event
EN
EN
TxD RxD WUP LIN EN INH
TxD RxD WUP LIN EN INH
TxD RxD WUP LIN EN INH
float 1 float 1 0 Vs
X
don’t
care, input signal is stable high or low
HiZ
internal pull up is switched off;
TxD
input signal may be high or low or transitioning
RxD
output signal is high impedance.
float
input signal may be high or low or transitioning
if t(EN=1 after 0->1)
>tENgs
(with LIN=0)
if t(EN=0 after 1->0)
>tgts
if t(LIN=0 after 1->0)
>tLINgs
tdelay
=tWUPgs
if (LIN=1)
11/14
L9638
Figure 7. Typical Application Circuit
WUP
TXD
INH
VS
EN
RXD
GND
LIN
L9638D
VCR
Vo
WD
VS
EN
RES
GND
L4979D
VCW
µC
EN
TXD
RXD
GND
WD
RES
VCC
VBAT
VS
CO
CTW
CS
CTR
CLIN
EXTERNAL
SWITCH
RSRLIN
LIN
BUS
1
2
3
45
6
7
8
1
2
3
4
5
6
7
8
Suggested Values
CS =100 nF CTW = 47 nF CLIN_MASTER = 1 nF RS = 100 kΩ
CTR = 1 nF CO = 10 µF CLIN_SLAVE = 220 pF RLIN = 1 kΩ
L9638
12/14
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D
(1)
4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
Note: (1) Dimensions D does not include mold flash, protru-
sions or gate burrs.
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).
SO-8
0016023 C
13/14
L9638
Table 6. Revision History
Date Revision Description of Changes
April 2004 1 First Issue
April 2004 2 Changed maturity from Product Preview in Final;
Corrected Order Codes;
Changed min. value of the item 1.4 of the Table 4 in the page 3.
October 2004 3 Add VESD in table 3;
Changed numbers item of the table 5 and add item 9
October 2004 4 Updated figure 7 on page11/14.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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L9638
