74LVT573DB,112 - NXP Semiconductors

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

74LVT573, 74LVTH573 Rev. 1.7.0

January 2008

74LVT573, 74LVTH573

Low Voltage Octal Transparent Latch with 3-STATE Outputs

Features

■

Input and output interface capability to systems at

5V V

■

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH573),

also available without bushold feature (74LVT573)

■

Live insertion/extraction permitted

■

Power Up/Down high impedance provides glitch-free

bus loading

■

Outputs source/sink –32mA/+64mA

■

Functionally compatible with the 74 series 573

■

Latch-up performance exceeds 500mA

■

ESD performance:

– Human-body model

2000V

– Machine model

200V

– Charged-device model

1000V

General Description

The LVT573 and LVTH573 consist of eight latches

with 3-STATE outputs for bus organized system applica-

tions. The latches appear transparent to the data when

Latch Enable (LE) is HIGH. When LE is low, the data

satisfying the input timing requirements is latched. Data

appears on the bus when the Output Enable (OE) is

LOW. When OE is HIGH, the bus output is in the high

impedance state.

The LVTH573 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These octal latches are designed for low-voltage (3.3V)

applications, but with the capability to provide a TTL

interface to a 5V environment. The LVT573 and

LVTH573 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining a low power dissipation.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LVT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVT573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LVT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74LVTH573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVTH573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVTH573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LVTH573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74LVT573, 74LVTH573 Rev. 1.7.0 2

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Connection Diagram

Pin Description

Functional Description

The LVT573 and LVTH573 contain eight D-type latches

with 3-STATE standard outputs. When the Latch Enable

(LE) input is HIGH, data on the D

inputs enters the

latches. In this condition the latches are transparent, i.e.,

a latch output will change state each time its D-type input

changes. When LE is LOW, the latches store the infor-

mation that was present on the D-type inputs a setup

time preceding the HIGH-to-LOW transition of LE. The

3-STATE standard outputs are controlled by the Output

Enable (OE) input. When OE is LOW, the standard out-

puts are in the 2-state mode. When OE is HIGH, the

standard outputs are in the high impedance mode but

this does not interfere with entering new data into the

latches.

Logic Symbols

IEEE/IEC

Truth Table

HIGH Voltage Level

LOW Voltage Level

High Impedance

Immaterial

Previous O

before HIGH to LOW transition

of Latch Enable

Pin Names Description

–D

Data Inputs

LE Latch Enable Input

OE Output Enable Input

–O

3-STATE Latch Outputs

Inputs Outputs

LE OE D

XHX Z

HLL L

HLH H

LLX O

74LVT573, 74LVTH573 Rev. 1.7.0 3

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

74LVT573, 74LVTH573 Rev. 1.7.0 4

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Note:

1. I

Absolute Maximum Rating must be observed.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

Supply Voltage –0.5V to +4.6V

DC Input Voltage –0.5V to +7.0V

DC Output Voltage

Output in 3-STATE –0.5V to +7.0V

Output in HIGH or LOW State

(1)

–0.5V to +7.0V

DC Input Diode Current, V

GND –50mA

DC Output Diode Current, V

GND –50mA

DC Output Current, V

Output at HIGH State 64mA

Output at LOW State 128mA

DC Supply Current per Supply Pin ±64mA

GND

DC Ground Current per Ground Pin ±128mA

STG

Storage Temperature –65°C to +150°C

Symbol Parameter Min Max Units

Supply Voltage 2.7 3.6 V

Input Voltage 0 5.5 V

HIGH-Level Output Current –32 mA

LOW-Level Output Current 64 mA

Free-Air Operating Temperature –40 85 °C

∆

V Input Edge Rate, V

0.8V–2.0V, V

3.0V 0 10 ns/V

74LVT573, 74LVTH573 Rev. 1.7.0 5

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

DC Electrical Characteristics

Notes:

2. All typical values are at V

3.3V, T

25°C.

3. Applies to bushold versions only (74LVTH573).

4. An external driver must source at least the specified current to switch from LOW-to-HIGH.

5. An external driver must sink at least the specified current to switch from HIGH-to-LOW.

6. This is the increase in supply current for each input that is at the specified voltage level rather than V

or GND.

Symbol Parameter V

(V) Conditions

–40°C to +85°C

UnitsMin. Typ.

(2)

Max.

Input Clamp Diode Voltage 2.7 I

–18mA –1.2 V

Input HIGH Voltage 2.7–3.6 V

≤

0.1V or

≥

– 0.1V

2.0 V

Input LOW Voltage 2.7–3.6 0.8 V

Output HIGH Voltage 2.7–3.6 I

–100µA V

– 0.2 V

2.7 I

–8mA 2.4

3.0 I

–32mA 2.0

Output LOW Voltage 2.7 I

100µA 0.2 V

24mA 0.5

3.0 I

16mA 0.4

32mA 0.5

64mA 0.55

I(HOLD)(3)

Bushold Input Minimum

Drive

3.0 V

0.8V 75 µA

2.0V –75

I(OD)(3)

Bushold Input Over-Drive

Current to Change State

3.0

(4)

500 µA

(5)

–500

Input Current 3.6 V

5.5V 10 µA

Control Pins 3.6 V

0V or VCC ±1

Data Pins 3.6 VI = 0V –5

VI = VCC 1

IOFF Power Off Leakage Current 0 0V ≤ VI or VO ≤ 5.5V ±100 µA

IPU/PD Power up/down 3-STATE

Output Current

0–1.5 VO = 0.5V to 3.0V,

VI = GND or VCC

±100 µA

IOZL 3-STATE Output Leakage

Current

3.6 VO = 0.5V –5 µA

IOZH 3-STATE Output Leakage

Current

3.6 VO = 3.0V 5 µA

IOZH+ 3-STATE Output Leakage

Current

3.6 VCC < VO ≤ 5.5V 10 µA

ICCH Power Supply Current 3.6 Outputs HIGH 0.19 mA

ICCL Power Supply Current 3.6 Outputs LOW 5 mA

ICCZ Power Supply Current 3.6 Outputs Disabled 0.19 mA

ICCZ+Power Supply Current 3.6 VCC ≤ VO ≤ 5.5V,

Outputs Disabled

0.19 mA

∆ICC Increase in Power Supply

Current(6) 3.6 One Input at VCC – 0.6V,

Other Inputs at VCC or

GND

0.2 mA

74LVT573, 74LVTH573 Rev. 1.7.0 6

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Dynamic Switching Characteristics(7)

Notes:

7. Characterized in SOIC package. Guaranteed parameter, but not tested.

8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.

AC Electrical Characteristics

Notes:

9. All typical values are at VCC = 3.3V, TA = 25°C.

10. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).

Capacitance(11)

Note:

11. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.

Symbol Parameter VCC (V)

Conditions TA = 25°C

UnitsCL = 50pF, RL = 500Ω Min. Typ. Max.

VOLP Quiet Output Maximum

Dynamic VOL

3.3 (8) 0.8 V

VOLV Quiet Output Minimum

Dynamic VOL

3.3 (8) –0.8 V

Symbol Parameter

TA = –40°C to +85°C

CL = 50pF, RL = 500Ω

Units

VCC = 3.3V ± 0.3V VCC = 2.7V

Min. Typ.(9) Max. Min. Max.

tPHL Propagation Delay, Dn to On1.5 4.4 1.5 4.9 ns

tPLH 1.5 4.1 1.5 4.7

tPHL Propagation Delay, LE to On1.9 4.4 1.9 4.9 ns

tPLH 1.9 4.4 1.9 5.0

tPZL Output Enable Time 1.5 5.1 1.5 6.6 ns

tPZH 1.5 5.1 1.5 5.9

tPLZ Output Disable Time 2.0 4.6 2.0 4.9 ns

tPHZ 2.0 4.9 2.0 5.5

tSSetup Time, Dn to LE 0.7 0.6 ns

tHHold Time, Dn to LE 1.5 1.7 ns

tWLE Pulse Width 3.0 3.0 ns

tOSHL, tOSLH Output to Output Skew(10) 1.0 1.0 ns

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 4pF

COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 6 pF

74LVT573, 74LVTH573 Rev. 1.7.0 7

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Physical Dimensions

Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

0.10 C

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

PIN ONE

INDICATOR

0.25

110

BC A

20 11

X 45°

8°

0°

SEATING PLANE

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

LAND PATTERN RECOMMENDATION

F) DRAWING FILENAME: MKT-M20BREV3

0.65

1.27

2.25

9.50

13.00

12.60

11.43

7.60

7.40

10.65

10.00

0.51

0.35 1.27

2.65 MAX

0.30

0.10

0.33

0.20

0.75

0.25

(R0.10)

1.27

0.40

(1.40)

0.25

D) CONFORMS TO ASME Y14.5M-1994

74LVT573, 74LVTH573 Rev. 1.7.0 8

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Physical Dimensions (Continued)

Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT573, 74LVTH573 Rev. 1.7.0 9

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Physical Dimensions (Continued)

Figure 3. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT573, 74LVTH573 Rev. 1.7.0 10

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs

Physical Dimensions (Continued)

Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT573, 74LVTH573 Rev. 1.7.0 11

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Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EZSWITCH™ *

™

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FlashWriter®*

FPS™

FRFET®

Global Power ResourceSM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC®

OPTOPLANAR®

PDP-SPM™

Power220®

POWEREDGE®

Power-SPM™

PowerTrench®

Programmable Active Droop™

QFET®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SupreMOS™

SyncFET™®

The Power Franchise®

TinyBoost™

TinyBuck™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

*EZSWITCH™ and FlashWriter®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary First Production

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs