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FEATURES
DB, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
VCCB
VCCB
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
RHL PACKAGE
(TOP VIEW)
1 24
12 13
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
VCCB
OE
B1
B2
B3
B4
B5
B6
B7
B8
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND V
GND
CCB
VCCA
DESCRIPTION/ORDERING INFORMATION
SN74LVC8T2458-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
•Control Inputs V
IH
/V
IL
Levels Are Referenced •Latch-Up Performance Exceeds 100 mA Perto V
CCA
Voltage JESD 78, Class II•V
CC
Isolation Feature – If Either V
CC
Input Is at •ESD Protection Exceeds JESD 22GND, All Are in the High-Impedance State
– 4000-V Human-Body Model (A114-A)•Fully Configurable Dual-Rail Design Allows
– 200-V Machine Model (A115-A)Each Port to Operate Over the Full 1.65-V to
– 1000-V Charged-Device Model (C101)5.5-V Power-Supply Range
This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245is optimized to operate with V
CCA
and V
CCB
set at 1.65 V to 5.5 V. The A port is designed to track V
CCA
. V
CCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V
CCB
. V
CCB
accepts any supplyvoltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RHL Tape and reel SN74LVC8T245RHLR NH245SSOP – DBR Tape and reel SN74LVC8T245DBR NH245SSOP (QSOP) – DBQ Tape and reel SN74LVC8T245DBQR NH245–40 °C to 85 °C
Tube SN74LVC8T245PWTSSOP – PW NH245Tape and reel SN74LVC8T245PWRTVSOP – DGV Tape and reel SN74LVC8T245DGVR NH245
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
SN74LVC8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels ofthe direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-portoutputs or place both output ports into the high-impedance mode. The device transmits data from the A bus tothe B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs areactivated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW levelapplied to prevent excess I
CC
and I
CCZ
.
The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, all outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS OUTPUT CIRCUITS
OPERATIONOE DIR A PORT B PORT
L L Enabled Hi-Z B data to A busL H Hi-Z Enabled A data to B busH X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os are always active.
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Absolute Maximum Ratings
(1)
SN74LVC8T2458-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CCA
Supply voltage range –0.5 6.5 VV
CCB
I/O ports (A port) –0.5 6.5V
I
Input voltage range
(2)
I/O ports (B port) –0.5 6.5 VControl inputs –0.5 6.5A port –0.5 6.5Voltage range applied to any outputV
O
Vin the high-impedance or power-off state
(2)
B port –0.5 6.5A port –0.5 V
CCA
+ 0.5V
O
Voltage range applied to any output in the high or low state
(2) (3)
VB port –0.5 V
CCB
+ 0.5I
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CCA
, V
CCB
, and GND ±100 mADB package 63DBQ package 61θ
JA
Package thermal impedance
(4)
DGV package 86 °C/WPW package 88RHL package 43T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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Recommended Operating Conditions
(1) (2) (3) (4)
SN74LVC8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
V
CCI
V
CCO
MIN MAX UNIT
V
CCA
1.65 5.5Supply voltage VV
CCB
1.65 5.51.65 V to 1.95 V V
CCI
×0.652.3 V to 2.7 V 1.7High-level
V
IH
Data inputs
(5)
Vinput voltage
3 V to 3.6 V 24.5 V to 5.5 V V
CCI
×0.71.65 V to 1.95 V V
CCI
×0.352.3 V to 2.7 V 0.7Low-level
V
IL
Data inputs
(5)
Vinput voltage
3 V to 3.6 V 0.84.5 V to 5.5 V V
CCI
×0.31.65 V to 1.95 V V
CCA
×0.652.3 V to 2.7 V 1.7High-level Control inputsV
IH
Vinput voltage (referenced to V
CCA
)
(6)
3 V to 3.6 V 24.5 V to 5.5 V V
CCA
×0.71.65 V to 1.95 V V
CCA
×0.352.3 V to 2.7 V 0.7Low-level Control inputsV
IL
Vinput voltage (referenced to V
CCA
)
(6)
3 V to 3.6 V 0.84.5 V to 5.5 V V
CCA
×0.3V
I
Input voltage Control inputs 0 5.5 VActive state 0 V
CCO
VInput/output
V
I/O
voltage
3-State 0 5.5 V1.65 V to 1.95 V –42.3 V to 2.7 V –8I
OH
High-level output current mA3 V to 3.6 V –244.5 V to 5.5 V –321.65 V to 1.95 V 42.3 V to 2.7 V 8I
OL
Low-level output current mA3 V to 3.6 V 244.5 V to 5.5 V 321.65 V to 1.95 V 202.3 V to 2.7 V 20Input transition∆t/ ∆v Data inputs ns/Vrise or fall rate
3 V to 3.6 V 104.5 V to 5.5 V 5T
A
Operating free-air temperature –40 85 °C
(1) V
CCI
is the V
CC
associated with the data input port.(2) V
CCO
is the V
CC
associated with the output port.(3) All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably V
CCI
or GND) to ensureproper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literaturenumber SCBA004.(4) All unused control inputs must be held at V
CCA
or GND to ensure proper device operation and minimize power comsumption.(5) For V
CCI
values not specified in the data sheet, V
IH
min = V
CCI
×0.7 V, V
IL
max = V
CCI
×0.3 V.(6) For V
CCA
values not specified in the data sheet, V
IH
min = V
CCA
×0.7 V, V
IL
max = V
CCA
×0.3 V.
4
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Electrical Characteristics
(1) (2)
SN74LVC8T2458-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CCA
V
CCB
MIN TYP MAX MIN MAX UNIT
I
OH
= –100 µA, V
I
= V
IH
1.65 V to 4.5 V 1.65 V to 4.5 V V
CCO
– 0.1I
OH
= –4 mA, V
I
= V
IH
1.65 V 1.65 V 1.2V
OH
I
OH
= –8 mA, V
I
= V
IH
2.3 V 2.3 V 1.9 VI
OH
= –24 mA, V
I
= V
IH
3 V 3 V 2.4I
OH
= –32 mA, V
I
= V
IH
4.5 V 4.5 V 3.8I
OL
= 100 µA, V
I
= V
IL
1.65 V to 4.5 V 1.65 V to 4.5 V 0.1I
OL
= 4 mA, V
I
= V
IL
1.65 V 1.65 V 0.45V
OL
I
OL
= 8 mA, V
I
= V
IL
2.3 V 2.3 V 0.3 VI
OL
= 24 mA, V
I
= V
IL
3 V 3 V 0.55I
OL
= 32 mA, V
I
= V
IL
4.5 V 4.5 V 0.55I
I
DIR V
I
= V
CCA
or GND 1.65 V to 5.5 V 1.65 V to 5.5 V ±1±2µA0 V 0 to 5.5 V ±1±2A or BI
off
V
I
or V
O
= 0 to 5.5 V µAport
0 to 5.5 V 0 V ±1±2A or B V
O
= V
CCO
or GND,I
OZ
1.65 V to 5.5 V 1.65 V to 5.5 V ±1±2µAport OE = V
IH
1.65 V to 5.5 V 1.65 V to 5.5 V 15I
CCA
V
I
= V
CCI
or GND, I
O
= 0 5 V 0 V 15 µA0 V 5 V –21.65 V to 5.5 V 1.65 V to 5.5 V 15I
CCB
V
I
= V
CCI
or GND, I
O
= 0 5 V 0 V –2 µA0 V 5 V 15I
CCA
+ I
CCB
V
I
= V
CCI
or GND, I
O
= 0 1.65 V to 5.5 V 1.65 V to 5.5 V 25 µAOne A port at V
CCA
– 0.6 V,A port 50DIR at V
CCA
, B port = open∆I
CCA
3 V to 5.5 V 3 V to 5.5 V µADIR at V
CCA
– 0.6 V,DIR B port = open, 50A port at V
CCA
or GNDOne B port at V
CCB
– 0.6 V,∆I
CCB
B port 3 V to 5.5 V 3 V to 5.5 V 50 µADIR at GND, A port = openControlC
i
V
I
= V
CCA
or GND 3.3 V 3.3 V 4 5 pFinputs
A or BC
io
V
O
= V
CCA/B
or GND 3.3 V 3.3 V 8.5 10 pFport
(1) V
CCO
is the V
CC
associated with the output port.(2) V
CCI
is the V
CC
associated with the input port.
5
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Switching Characteristics
Switching Characteristics
SN74LVC8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
over recommended operating free-air temperature range, V
CCA
= 1.8 V ±0.15 V (unless otherwise noted) (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
A B 1.7 21.9 1.3 9.2 1 7.4 0.8 7.1 nst
PHL
t
PLH
B A 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 nst
PHL
t
PHZ
OE A 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 nst
PLZ
t
PHZ
OE B 2.4 32.2 1.9 13.1 1.7 12 1.3 10.3 nst
PLZ
t
PZH
OE A 0.4 24 0.4 23.8 0.4 23.7 0.4 23.7 nst
PZL
t
PZH
OE B 1.8 32 1.5 16 1.2 12.6 0.9 10.8 nst
PZL
over recommended operating free-air temperature range, V
CCA
= 2.5 V ±0.2 V (unless otherwise noted) (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
A B 1.5 21.4 1.2 9 0.8 6.2 0.6 4.8 nst
PHL
t
PLH
B A 1.2 9.3 1 9.1 1 8.9 0.9 8.8 nst
PHL
t
PHZ
OE A 1.4 9 1.4 9 1.4 9 1.4 9 nst
PLZ
t
PHZ
OE B 2.3 29.6 1.8 11 1.7 9.3 0.9 6.9 nst
PLZ
t
PZH
OE A 1 10.9 1 10.9 1 10.9 1 10.9 nst
PZL
t
PZH
OE B 1.7 28.2 1.5 12.9 1.2 9.4 1 6.9 nst
PZL
6
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Switching Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC8T2458-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
over recommended operating free-air temperature range, V
CCA
= 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
A B 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 nst
PHL
t
PLH
B A 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6 nst
PHL
t
PHZ
OE A 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 nst
PLZ
t
PHZ
OE B 2.1 29 1.7 10.3 1.5 8.6 0.8 6.3 nst
PLZ
t
PZH
OE A 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 nst
PZL
t
PZH
OE B 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 nst
PZL
over recommended operating free-air temperature range, V
CCA
= 5 V ±0.5 V (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
A B 1.5 21.4 1 8.8 0.7 6 0.4 4.2 nst
PHL
t
PLH
B A 0.7 7 0.4 4.8 0.3 4.5 0.3 4.3 nst
PHL
t
PHZ
OE A 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 nst
PLZ
t
PHZ
OE B 2 28.7 1.6 9.7 1.4 8 0.7 5.7 nst
PLZ
t
PZH
OE A 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 nst
PZL
t
PZH
OE B 1.5 27.6 1.3 11.4 1 8.1 0.9 6 nst
PZL
T
A
= 25 °C
V
CCA
= V
CCA
= V
CCA
= V
CCA
=TEST
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VPARAMETER UNITCONDITIONS
TYP TYP TYP TYP
A-port input, B-port output 2 2 2 3C
pdA
(1)
C
L
= 0,B-port input, A-port output 12 13 13 16f = 10 MHz, pFA-port input, B-port output 13 13 14 16t
r
= t
f
= 1 nsC
pdB
(1)
B-port input, A-port output 2 2 2 3
(1) Power dissipation capacitance per transceiver
7
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PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2 × VCCO
Open
GND
RL
RL
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2VCCA/2
VCCI/2 VCCI/2 VCCI
0 V
VCCO/2 VCCO/2VOH
VOL
0 V
VCCO/2 VOL + VTP
VCCO/2 VOH − VTP
0 V
VCCI
0 V
VCCI/2 VCCI/2
tw
Input
VCCA
VCCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
VCCO RL0.15 V
0.15 V
0.3 V
0.3 V
VTP
CL
15 pF
15 pF
15 pF
15 pF
SN74LVC8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES584A – JUNE 2005 – REVISED AUGUST 2005
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74LVC8T245DBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
74LVC8T245RHLRG4 ACTIVE QFN RHL 24 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVC8T245DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVC8T245DBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245DBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245DWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245NSR ACTIVE SO NS 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245NSRG4 ACTIVE SO NS 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245PW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245PWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC8T245PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC8T245RHLR ACTIVE QFN RHL 24 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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OTHER QUALIFIED VERSIONS OF SN74LVC8T245 :
•Automotive: SN74LVC8T245-Q1
•Enhanced Product: SN74LVC8T245-EP
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC8T245DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC8T245DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVC8T245DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC8T245DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC8T245NSR SO NS 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 Q1
SN74LVC8T245PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVC8T245RHLR QFN RHL 24 1000 180.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC8T245DBQR SSOP DBQ 24 2500 367.0 367.0 38.0
SN74LVC8T245DBR SSOP DB 24 2000 367.0 367.0 38.0
SN74LVC8T245DGVR TVSOP DGV 24 2000 367.0 367.0 35.0
SN74LVC8T245DWR SOIC DW 24 2000 367.0 367.0 45.0
SN74LVC8T245NSR SO NS 24 2000 367.0 367.0 45.0
SN74LVC8T245PWR TSSOP PW 24 2000 367.0 367.0 38.0
SN74LVC8T245RHLR QFN RHL 24 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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